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b53: support setting port link
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/platform_data/b53.h>
28
29 #include "b53_regs.h"
30 #include "b53_priv.h"
31
32 /* buffer size needed for displaying all MIBs with max'd values */
33 #define B53_BUF_SIZE 1188
34
35 struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39 };
40
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 { },
77 };
78
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123 { }
124 };
125
126 /* MIB counters */
127 static const struct b53_mib_desc b53_mibs[] = {
128 { 8, 0x00, "TxOctets" },
129 { 4, 0x08, "TxDropPkts" },
130 { 4, 0x10, "TxBroadcastPkts" },
131 { 4, 0x14, "TxMulticastPkts" },
132 { 4, 0x18, "TxUnicastPkts" },
133 { 4, 0x1c, "TxCollisions" },
134 { 4, 0x20, "TxSingleCollision" },
135 { 4, 0x24, "TxMultipleCollision" },
136 { 4, 0x28, "TxDeferredTransmit" },
137 { 4, 0x2c, "TxLateCollision" },
138 { 4, 0x30, "TxExcessiveCollision" },
139 { 4, 0x38, "TxPausePkts" },
140 { 8, 0x50, "RxOctets" },
141 { 4, 0x58, "RxUndersizePkts" },
142 { 4, 0x5c, "RxPausePkts" },
143 { 4, 0x60, "Pkts64Octets" },
144 { 4, 0x64, "Pkts65to127Octets" },
145 { 4, 0x68, "Pkts128to255Octets" },
146 { 4, 0x6c, "Pkts256to511Octets" },
147 { 4, 0x70, "Pkts512to1023Octets" },
148 { 4, 0x74, "Pkts1024to1522Octets" },
149 { 4, 0x78, "RxOversizePkts" },
150 { 4, 0x7c, "RxJabbers" },
151 { 4, 0x80, "RxAlignmentErrors" },
152 { 4, 0x84, "RxFCSErrors" },
153 { 8, 0x88, "RxGoodOctets" },
154 { 4, 0x90, "RxDropPkts" },
155 { 4, 0x94, "RxUnicastPkts" },
156 { 4, 0x98, "RxMulticastPkts" },
157 { 4, 0x9c, "RxBroadcastPkts" },
158 { 4, 0xa0, "RxSAChanges" },
159 { 4, 0xa4, "RxFragments" },
160 { 4, 0xa8, "RxJumboPkts" },
161 { 4, 0xac, "RxSymbolErrors" },
162 { 4, 0xc0, "RxDiscarded" },
163 { }
164 };
165
166 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
167 {
168 unsigned int i;
169
170 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
171
172 for (i = 0; i < 10; i++) {
173 u8 vta;
174
175 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
176 if (!(vta & VTA_START_CMD))
177 return 0;
178
179 usleep_range(100, 200);
180 }
181
182 return -EIO;
183 }
184
185 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
186 u16 untag)
187 {
188 if (is5325(dev)) {
189 u32 entry = 0;
190
191 if (members) {
192 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
193 members;
194 if (dev->core_rev >= 3)
195 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
196 else
197 entry |= VA_VALID_25;
198 }
199
200 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
201 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
202 VTA_RW_STATE_WR | VTA_RW_OP_EN);
203 } else if (is5365(dev)) {
204 u16 entry = 0;
205
206 if (members)
207 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
208 members | VA_VALID_65;
209
210 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
211 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
212 VTA_RW_STATE_WR | VTA_RW_OP_EN);
213 } else {
214 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
215 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
216 (untag << VTE_UNTAG_S) | members);
217
218 b53_do_vlan_op(dev, VTA_CMD_WRITE);
219 }
220 }
221
222 void b53_set_forwarding(struct b53_device *dev, int enable)
223 {
224 u8 mgmt;
225
226 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
227
228 if (enable)
229 mgmt |= SM_SW_FWD_EN;
230 else
231 mgmt &= ~SM_SW_FWD_EN;
232
233 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
234 }
235
236 static void b53_enable_vlan(struct b53_device *dev, int enable)
237 {
238 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
239
240 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
241 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
242 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
243
244 if (is5325(dev) || is5365(dev)) {
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
246 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
247 } else if (is63xx(dev)) {
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
250 } else {
251 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
253 }
254
255 mgmt &= ~SM_SW_FWD_MODE;
256
257 if (enable) {
258 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
259 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
260 vc4 &= ~VC4_ING_VID_CHECK_MASK;
261 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
262 vc5 |= VC5_DROP_VTABLE_MISS;
263
264 if (is5325(dev))
265 vc0 &= ~VC0_RESERVED_1;
266
267 if (is5325(dev) || is5365(dev))
268 vc1 |= VC1_RX_MCST_TAG_EN;
269
270 if (!is5325(dev) && !is5365(dev)) {
271 if (dev->allow_vid_4095)
272 vc5 |= VC5_VID_FFF_EN;
273 else
274 vc5 &= ~VC5_VID_FFF_EN;
275 }
276 } else {
277 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
278 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
279 vc4 &= ~VC4_ING_VID_CHECK_MASK;
280 vc5 &= ~VC5_DROP_VTABLE_MISS;
281
282 if (is5325(dev) || is5365(dev))
283 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
284 else
285 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
286
287 if (is5325(dev) || is5365(dev))
288 vc1 &= ~VC1_RX_MCST_TAG_EN;
289
290 if (!is5325(dev) && !is5365(dev))
291 vc5 &= ~VC5_VID_FFF_EN;
292 }
293
294 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
295 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
296
297 if (is5325(dev) || is5365(dev)) {
298 /* enable the high 8 bit vid check on 5325 */
299 if (is5325(dev) && enable)
300 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
301 VC3_HIGH_8BIT_EN);
302 else
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
304
305 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
306 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
307 } else if (is63xx(dev)) {
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
309 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
310 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
311 } else {
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
315 }
316
317 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
318 }
319
320 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
321 {
322 u32 port_mask = 0;
323 u16 max_size = JMS_MIN_SIZE;
324
325 if (is5325(dev) || is5365(dev))
326 return -EINVAL;
327
328 if (enable) {
329 port_mask = dev->enabled_ports;
330 max_size = JMS_MAX_SIZE;
331 if (allow_10_100)
332 port_mask |= JPM_10_100_JUMBO_EN;
333 }
334
335 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
336 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
337 }
338
339 static int b53_flush_arl(struct b53_device *dev)
340 {
341 unsigned int i;
342
343 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
344 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
345
346 for (i = 0; i < 10; i++) {
347 u8 fast_age_ctrl;
348
349 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
350 &fast_age_ctrl);
351
352 if (!(fast_age_ctrl & FAST_AGE_DONE))
353 return 0;
354
355 mdelay(1);
356 }
357
358 pr_warn("time out while flushing ARL\n");
359
360 return -EINVAL;
361 }
362
363 static void b53_enable_ports(struct b53_device *dev)
364 {
365 unsigned i;
366
367 b53_for_each_port(dev, i) {
368 u8 port_ctrl;
369 u16 pvlan_mask;
370
371 /*
372 * prevent leaking packets between wan and lan in unmanaged
373 * mode through port vlans.
374 */
375 if (dev->enable_vlan || is_cpu_port(dev, i))
376 pvlan_mask = 0x1ff;
377 else if (is531x5(dev) || is5301x(dev))
378 /* BCM53115 may use a different port as cpu port */
379 pvlan_mask = BIT(dev->sw_dev.cpu_port);
380 else
381 pvlan_mask = BIT(B53_CPU_PORT);
382
383 /* BCM5325 CPU port is at 8 */
384 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
385 i = B53_CPU_PORT;
386
387 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
388 /* disable unused ports 6 & 7 */
389 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
390 else if (i == B53_CPU_PORT)
391 port_ctrl = PORT_CTRL_RX_BCST_EN |
392 PORT_CTRL_RX_MCST_EN |
393 PORT_CTRL_RX_UCST_EN;
394 else
395 port_ctrl = 0;
396
397 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
398 pvlan_mask);
399
400 /* port state is handled by bcm63xx_enet driver */
401 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
402 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
403 port_ctrl);
404 }
405 }
406
407 static void b53_enable_mib(struct b53_device *dev)
408 {
409 u8 gc;
410
411 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
412
413 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
414
415 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
416 }
417
418 static int b53_apply(struct b53_device *dev)
419 {
420 int i;
421
422 /* clear all vlan entries */
423 if (is5325(dev) || is5365(dev)) {
424 for (i = 1; i < dev->sw_dev.vlans; i++)
425 b53_set_vlan_entry(dev, i, 0, 0);
426 } else {
427 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
428 }
429
430 b53_enable_vlan(dev, dev->enable_vlan);
431
432 /* fill VLAN table */
433 if (dev->enable_vlan) {
434 for (i = 0; i < dev->sw_dev.vlans; i++) {
435 struct b53_vlan *vlan = &dev->vlans[i];
436
437 if (!vlan->members)
438 continue;
439
440 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
441 }
442
443 b53_for_each_port(dev, i)
444 b53_write16(dev, B53_VLAN_PAGE,
445 B53_VLAN_PORT_DEF_TAG(i),
446 dev->ports[i].pvid);
447 } else {
448 b53_for_each_port(dev, i)
449 b53_write16(dev, B53_VLAN_PAGE,
450 B53_VLAN_PORT_DEF_TAG(i), 1);
451
452 }
453
454 b53_enable_ports(dev);
455
456 if (!is5325(dev) && !is5365(dev))
457 b53_set_jumbo(dev, dev->enable_jumbo, 1);
458
459 return 0;
460 }
461
462 static void b53_switch_reset_gpio(struct b53_device *dev)
463 {
464 int gpio = dev->reset_gpio;
465
466 if (gpio < 0)
467 return;
468
469 /*
470 * Reset sequence: RESET low(50ms)->high(20ms)
471 */
472 gpio_set_value(gpio, 0);
473 mdelay(50);
474
475 gpio_set_value(gpio, 1);
476 mdelay(20);
477
478 dev->current_page = 0xff;
479 }
480
481 static int b53_switch_reset(struct b53_device *dev)
482 {
483 u8 cpu_port = dev->sw_dev.cpu_port;
484 u8 mgmt;
485
486 b53_switch_reset_gpio(dev);
487
488 if (is539x(dev)) {
489 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
490 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
491 }
492
493 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
494
495 if (!(mgmt & SM_SW_FWD_EN)) {
496 mgmt &= ~SM_SW_FWD_MODE;
497 mgmt |= SM_SW_FWD_EN;
498
499 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
500 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
501
502 if (!(mgmt & SM_SW_FWD_EN)) {
503 pr_err("Failed to enable switch!\n");
504 return -EINVAL;
505 }
506 }
507
508 /* enable all ports */
509 b53_enable_ports(dev);
510
511 /* configure MII port if necessary */
512 if (is5325(dev)) {
513 u8 mii_port_override;
514
515 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
516 &mii_port_override);
517 /* reverse mii needs to be enabled */
518 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
519 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
520 mii_port_override | PORT_OVERRIDE_RV_MII_25);
521 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
522 &mii_port_override);
523
524 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
525 pr_err("Failed to enable reverse MII mode\n");
526 return -EINVAL;
527 }
528 }
529 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
530 u8 mii_port_override;
531
532 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
533 &mii_port_override);
534 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
535 mii_port_override | PORT_OVERRIDE_EN |
536 PORT_OVERRIDE_LINK);
537 } else if (is5301x(dev)) {
538 if (cpu_port == 8) {
539 u8 mii_port_override;
540
541 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
542 &mii_port_override);
543 mii_port_override |= PORT_OVERRIDE_LINK |
544 PORT_OVERRIDE_RX_FLOW |
545 PORT_OVERRIDE_TX_FLOW |
546 PORT_OVERRIDE_SPEED_2000M |
547 PORT_OVERRIDE_EN;
548 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
549 mii_port_override);
550
551 /* TODO: Ports 5 & 7 require some extra handling */
552 } else {
553 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
554 u8 gmii_po;
555
556 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
557 gmii_po |= GMII_PO_LINK |
558 GMII_PO_RX_FLOW |
559 GMII_PO_TX_FLOW |
560 GMII_PO_EN |
561 GMII_PO_SPEED_2000M;
562 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
563 }
564 }
565
566 b53_enable_mib(dev);
567
568 return b53_flush_arl(dev);
569 }
570
571 /*
572 * Swconfig glue functions
573 */
574
575 static int b53_global_get_vlan_enable(struct switch_dev *dev,
576 const struct switch_attr *attr,
577 struct switch_val *val)
578 {
579 struct b53_device *priv = sw_to_b53(dev);
580
581 val->value.i = priv->enable_vlan;
582
583 return 0;
584 }
585
586 static int b53_global_set_vlan_enable(struct switch_dev *dev,
587 const struct switch_attr *attr,
588 struct switch_val *val)
589 {
590 struct b53_device *priv = sw_to_b53(dev);
591
592 priv->enable_vlan = val->value.i;
593
594 return 0;
595 }
596
597 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
598 const struct switch_attr *attr,
599 struct switch_val *val)
600 {
601 struct b53_device *priv = sw_to_b53(dev);
602
603 val->value.i = priv->enable_jumbo;
604
605 return 0;
606 }
607
608 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
609 const struct switch_attr *attr,
610 struct switch_val *val)
611 {
612 struct b53_device *priv = sw_to_b53(dev);
613
614 priv->enable_jumbo = val->value.i;
615
616 return 0;
617 }
618
619 static int b53_global_get_4095_enable(struct switch_dev *dev,
620 const struct switch_attr *attr,
621 struct switch_val *val)
622 {
623 struct b53_device *priv = sw_to_b53(dev);
624
625 val->value.i = priv->allow_vid_4095;
626
627 return 0;
628 }
629
630 static int b53_global_set_4095_enable(struct switch_dev *dev,
631 const struct switch_attr *attr,
632 struct switch_val *val)
633 {
634 struct b53_device *priv = sw_to_b53(dev);
635
636 priv->allow_vid_4095 = val->value.i;
637
638 return 0;
639 }
640
641 static int b53_global_get_ports(struct switch_dev *dev,
642 const struct switch_attr *attr,
643 struct switch_val *val)
644 {
645 struct b53_device *priv = sw_to_b53(dev);
646
647 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
648 priv->enabled_ports);
649 val->value.s = priv->buf;
650
651 return 0;
652 }
653
654 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
655 {
656 struct b53_device *priv = sw_to_b53(dev);
657
658 *val = priv->ports[port].pvid;
659
660 return 0;
661 }
662
663 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
664 {
665 struct b53_device *priv = sw_to_b53(dev);
666
667 if (val > 15 && is5325(priv))
668 return -EINVAL;
669 if (val == 4095 && !priv->allow_vid_4095)
670 return -EINVAL;
671
672 priv->ports[port].pvid = val;
673
674 return 0;
675 }
676
677 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
678 {
679 struct b53_device *priv = sw_to_b53(dev);
680 struct switch_port *port = &val->value.ports[0];
681 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
682 int i;
683
684 val->len = 0;
685
686 if (!vlan->members)
687 return 0;
688
689 for (i = 0; i < dev->ports; i++) {
690 if (!(vlan->members & BIT(i)))
691 continue;
692
693
694 if (!(vlan->untag & BIT(i)))
695 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
696 else
697 port->flags = 0;
698
699 port->id = i;
700 val->len++;
701 port++;
702 }
703
704 return 0;
705 }
706
707 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
708 {
709 struct b53_device *priv = sw_to_b53(dev);
710 struct switch_port *port;
711 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
712 int i;
713
714 /* only BCM5325 and BCM5365 supports VID 0 */
715 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
716 return -EINVAL;
717
718 /* VLAN 4095 needs special handling */
719 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
720 return -EINVAL;
721
722 port = &val->value.ports[0];
723 vlan->members = 0;
724 vlan->untag = 0;
725 for (i = 0; i < val->len; i++, port++) {
726 vlan->members |= BIT(port->id);
727
728 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
729 vlan->untag |= BIT(port->id);
730 priv->ports[port->id].pvid = val->port_vlan;
731 };
732 }
733
734 /* ignore disabled ports */
735 vlan->members &= priv->enabled_ports;
736 vlan->untag &= priv->enabled_ports;
737
738 return 0;
739 }
740
741 static int b53_port_get_link(struct switch_dev *dev, int port,
742 struct switch_port_link *link)
743 {
744 struct b53_device *priv = sw_to_b53(dev);
745
746 if (is_cpu_port(priv, port)) {
747 link->link = 1;
748 link->duplex = 1;
749 link->speed = is5325(priv) || is5365(priv) ?
750 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
751 link->aneg = 0;
752 } else if (priv->enabled_ports & BIT(port)) {
753 u32 speed;
754 u16 lnk, duplex;
755
756 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
757 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
758
759 lnk = (lnk >> port) & 1;
760 duplex = (duplex >> port) & 1;
761
762 if (is5325(priv) || is5365(priv)) {
763 u16 tmp;
764
765 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
766 speed = SPEED_PORT_FE(tmp, port);
767 } else {
768 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
769 speed = SPEED_PORT_GE(speed, port);
770 }
771
772 link->link = lnk;
773 if (lnk) {
774 link->duplex = duplex;
775 switch (speed) {
776 case SPEED_STAT_10M:
777 link->speed = SWITCH_PORT_SPEED_10;
778 break;
779 case SPEED_STAT_100M:
780 link->speed = SWITCH_PORT_SPEED_100;
781 break;
782 case SPEED_STAT_1000M:
783 link->speed = SWITCH_PORT_SPEED_1000;
784 break;
785 }
786 }
787
788 link->aneg = 1;
789 } else {
790 link->link = 0;
791 }
792
793 return 0;
794
795 }
796
797 static int b53_port_set_link(struct switch_dev *sw_dev, int port,
798 struct switch_port_link *link)
799 {
800 struct b53_device *dev = sw_to_b53(sw_dev);
801
802 /*
803 * TODO: BCM63XX requires special handling as it can have external phys
804 * and ports might be GE or only FE
805 */
806 if (is63xx(dev))
807 return -ENOTSUPP;
808
809 if (port == sw_dev->cpu_port)
810 return -EINVAL;
811
812 if (!(BIT(port) & dev->enabled_ports))
813 return -EINVAL;
814
815 if (link->speed == SWITCH_PORT_SPEED_1000 &&
816 (is5325(dev) || is5365(dev)))
817 return -EINVAL;
818
819 if (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)
820 return -EINVAL;
821
822 return switch_generic_set_link(sw_dev, port, link);
823 }
824
825 static int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
826 {
827 struct b53_device *priv = sw_to_b53(dev);
828
829 if (priv->ops->phy_read16)
830 return priv->ops->phy_read16(priv, addr, reg, value);
831
832 return b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);
833 }
834
835 static int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
836 {
837 struct b53_device *priv = sw_to_b53(dev);
838
839 if (priv->ops->phy_write16)
840 return priv->ops->phy_write16(priv, addr, reg, value);
841
842 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);
843 }
844
845 static int b53_global_reset_switch(struct switch_dev *dev)
846 {
847 struct b53_device *priv = sw_to_b53(dev);
848
849 /* reset vlans */
850 priv->enable_vlan = 0;
851 priv->enable_jumbo = 0;
852 priv->allow_vid_4095 = 0;
853
854 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
855 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
856
857 return b53_switch_reset(priv);
858 }
859
860 static int b53_global_apply_config(struct switch_dev *dev)
861 {
862 struct b53_device *priv = sw_to_b53(dev);
863
864 /* disable switching */
865 b53_set_forwarding(priv, 0);
866
867 b53_apply(priv);
868
869 /* enable switching */
870 b53_set_forwarding(priv, 1);
871
872 return 0;
873 }
874
875
876 static int b53_global_reset_mib(struct switch_dev *dev,
877 const struct switch_attr *attr,
878 struct switch_val *val)
879 {
880 struct b53_device *priv = sw_to_b53(dev);
881 u8 gc;
882
883 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
884
885 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
886 mdelay(1);
887 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
888 mdelay(1);
889
890 return 0;
891 }
892
893 static int b53_port_get_mib(struct switch_dev *sw_dev,
894 const struct switch_attr *attr,
895 struct switch_val *val)
896 {
897 struct b53_device *dev = sw_to_b53(sw_dev);
898 const struct b53_mib_desc *mibs;
899 int port = val->port_vlan;
900 int len = 0;
901
902 if (!(BIT(port) & dev->enabled_ports))
903 return -1;
904
905 if (is5365(dev)) {
906 if (port == 5)
907 port = 8;
908
909 mibs = b53_mibs_65;
910 } else if (is63xx(dev)) {
911 mibs = b53_mibs_63xx;
912 } else {
913 mibs = b53_mibs;
914 }
915
916 dev->buf[0] = 0;
917
918 for (; mibs->size > 0; mibs++) {
919 u64 val;
920
921 if (mibs->size == 8) {
922 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
923 } else {
924 u32 val32;
925
926 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
927 &val32);
928 val = val32;
929 }
930
931 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
932 "%-20s: %llu\n", mibs->name, val);
933 }
934
935 val->len = len;
936 val->value.s = dev->buf;
937
938 return 0;
939 }
940
941 static struct switch_attr b53_global_ops_25[] = {
942 {
943 .type = SWITCH_TYPE_INT,
944 .name = "enable_vlan",
945 .description = "Enable VLAN mode",
946 .set = b53_global_set_vlan_enable,
947 .get = b53_global_get_vlan_enable,
948 .max = 1,
949 },
950 {
951 .type = SWITCH_TYPE_STRING,
952 .name = "ports",
953 .description = "Available ports (as bitmask)",
954 .get = b53_global_get_ports,
955 },
956 };
957
958 static struct switch_attr b53_global_ops_65[] = {
959 {
960 .type = SWITCH_TYPE_INT,
961 .name = "enable_vlan",
962 .description = "Enable VLAN mode",
963 .set = b53_global_set_vlan_enable,
964 .get = b53_global_get_vlan_enable,
965 .max = 1,
966 },
967 {
968 .type = SWITCH_TYPE_STRING,
969 .name = "ports",
970 .description = "Available ports (as bitmask)",
971 .get = b53_global_get_ports,
972 },
973 {
974 .type = SWITCH_TYPE_INT,
975 .name = "reset_mib",
976 .description = "Reset MIB counters",
977 .set = b53_global_reset_mib,
978 },
979 };
980
981 static struct switch_attr b53_global_ops[] = {
982 {
983 .type = SWITCH_TYPE_INT,
984 .name = "enable_vlan",
985 .description = "Enable VLAN mode",
986 .set = b53_global_set_vlan_enable,
987 .get = b53_global_get_vlan_enable,
988 .max = 1,
989 },
990 {
991 .type = SWITCH_TYPE_STRING,
992 .name = "ports",
993 .description = "Available Ports (as bitmask)",
994 .get = b53_global_get_ports,
995 },
996 {
997 .type = SWITCH_TYPE_INT,
998 .name = "reset_mib",
999 .description = "Reset MIB counters",
1000 .set = b53_global_reset_mib,
1001 },
1002 {
1003 .type = SWITCH_TYPE_INT,
1004 .name = "enable_jumbo",
1005 .description = "Enable Jumbo Frames",
1006 .set = b53_global_set_jumbo_enable,
1007 .get = b53_global_get_jumbo_enable,
1008 .max = 1,
1009 },
1010 {
1011 .type = SWITCH_TYPE_INT,
1012 .name = "allow_vid_4095",
1013 .description = "Allow VID 4095",
1014 .set = b53_global_set_4095_enable,
1015 .get = b53_global_get_4095_enable,
1016 .max = 1,
1017 },
1018 };
1019
1020 static struct switch_attr b53_port_ops[] = {
1021 {
1022 .type = SWITCH_TYPE_STRING,
1023 .name = "mib",
1024 .description = "Get port's MIB counters",
1025 .get = b53_port_get_mib,
1026 },
1027 };
1028
1029 static struct switch_attr b53_no_ops[] = {
1030 };
1031
1032 static const struct switch_dev_ops b53_switch_ops_25 = {
1033 .attr_global = {
1034 .attr = b53_global_ops_25,
1035 .n_attr = ARRAY_SIZE(b53_global_ops_25),
1036 },
1037 .attr_port = {
1038 .attr = b53_no_ops,
1039 .n_attr = ARRAY_SIZE(b53_no_ops),
1040 },
1041 .attr_vlan = {
1042 .attr = b53_no_ops,
1043 .n_attr = ARRAY_SIZE(b53_no_ops),
1044 },
1045
1046 .get_vlan_ports = b53_vlan_get_ports,
1047 .set_vlan_ports = b53_vlan_set_ports,
1048 .get_port_pvid = b53_port_get_pvid,
1049 .set_port_pvid = b53_port_set_pvid,
1050 .apply_config = b53_global_apply_config,
1051 .reset_switch = b53_global_reset_switch,
1052 .get_port_link = b53_port_get_link,
1053 .set_port_link = b53_port_set_link,
1054 .phy_read16 = b53_phy_read16,
1055 .phy_write16 = b53_phy_write16,
1056 };
1057
1058 static const struct switch_dev_ops b53_switch_ops_65 = {
1059 .attr_global = {
1060 .attr = b53_global_ops_65,
1061 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1062 },
1063 .attr_port = {
1064 .attr = b53_port_ops,
1065 .n_attr = ARRAY_SIZE(b53_port_ops),
1066 },
1067 .attr_vlan = {
1068 .attr = b53_no_ops,
1069 .n_attr = ARRAY_SIZE(b53_no_ops),
1070 },
1071
1072 .get_vlan_ports = b53_vlan_get_ports,
1073 .set_vlan_ports = b53_vlan_set_ports,
1074 .get_port_pvid = b53_port_get_pvid,
1075 .set_port_pvid = b53_port_set_pvid,
1076 .apply_config = b53_global_apply_config,
1077 .reset_switch = b53_global_reset_switch,
1078 .get_port_link = b53_port_get_link,
1079 .set_port_link = b53_port_set_link,
1080 .phy_read16 = b53_phy_read16,
1081 .phy_write16 = b53_phy_write16,
1082 };
1083
1084 static const struct switch_dev_ops b53_switch_ops = {
1085 .attr_global = {
1086 .attr = b53_global_ops,
1087 .n_attr = ARRAY_SIZE(b53_global_ops),
1088 },
1089 .attr_port = {
1090 .attr = b53_port_ops,
1091 .n_attr = ARRAY_SIZE(b53_port_ops),
1092 },
1093 .attr_vlan = {
1094 .attr = b53_no_ops,
1095 .n_attr = ARRAY_SIZE(b53_no_ops),
1096 },
1097
1098 .get_vlan_ports = b53_vlan_get_ports,
1099 .set_vlan_ports = b53_vlan_set_ports,
1100 .get_port_pvid = b53_port_get_pvid,
1101 .set_port_pvid = b53_port_set_pvid,
1102 .apply_config = b53_global_apply_config,
1103 .reset_switch = b53_global_reset_switch,
1104 .get_port_link = b53_port_get_link,
1105 .set_port_link = b53_port_set_link,
1106 .phy_read16 = b53_phy_read16,
1107 .phy_write16 = b53_phy_write16,
1108 };
1109
1110 struct b53_chip_data {
1111 u32 chip_id;
1112 const char *dev_name;
1113 const char *alias;
1114 u16 vlans;
1115 u16 enabled_ports;
1116 u8 cpu_port;
1117 u8 vta_regs[3];
1118 u8 duplex_reg;
1119 u8 jumbo_pm_reg;
1120 u8 jumbo_size_reg;
1121 const struct switch_dev_ops *sw_ops;
1122 };
1123
1124 #define B53_VTA_REGS \
1125 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1126 #define B53_VTA_REGS_9798 \
1127 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1128 #define B53_VTA_REGS_63XX \
1129 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1130
1131 static const struct b53_chip_data b53_switch_chips[] = {
1132 {
1133 .chip_id = BCM5325_DEVICE_ID,
1134 .dev_name = "BCM5325",
1135 .alias = "bcm5325",
1136 .vlans = 16,
1137 .enabled_ports = 0x1f,
1138 .cpu_port = B53_CPU_PORT_25,
1139 .duplex_reg = B53_DUPLEX_STAT_FE,
1140 .sw_ops = &b53_switch_ops_25,
1141 },
1142 {
1143 .chip_id = BCM5365_DEVICE_ID,
1144 .dev_name = "BCM5365",
1145 .alias = "bcm5365",
1146 .vlans = 256,
1147 .enabled_ports = 0x1f,
1148 .cpu_port = B53_CPU_PORT_25,
1149 .duplex_reg = B53_DUPLEX_STAT_FE,
1150 .sw_ops = &b53_switch_ops_65,
1151 },
1152 {
1153 .chip_id = BCM5395_DEVICE_ID,
1154 .dev_name = "BCM5395",
1155 .alias = "bcm5395",
1156 .vlans = 4096,
1157 .enabled_ports = 0x1f,
1158 .cpu_port = B53_CPU_PORT,
1159 .vta_regs = B53_VTA_REGS,
1160 .duplex_reg = B53_DUPLEX_STAT_GE,
1161 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1162 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1163 .sw_ops = &b53_switch_ops,
1164 },
1165 {
1166 .chip_id = BCM5397_DEVICE_ID,
1167 .dev_name = "BCM5397",
1168 .alias = "bcm5397",
1169 .vlans = 4096,
1170 .enabled_ports = 0x1f,
1171 .cpu_port = B53_CPU_PORT,
1172 .vta_regs = B53_VTA_REGS_9798,
1173 .duplex_reg = B53_DUPLEX_STAT_GE,
1174 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1175 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1176 .sw_ops = &b53_switch_ops,
1177 },
1178 {
1179 .chip_id = BCM5398_DEVICE_ID,
1180 .dev_name = "BCM5398",
1181 .alias = "bcm5398",
1182 .vlans = 4096,
1183 .enabled_ports = 0x7f,
1184 .cpu_port = B53_CPU_PORT,
1185 .vta_regs = B53_VTA_REGS_9798,
1186 .duplex_reg = B53_DUPLEX_STAT_GE,
1187 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1188 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1189 .sw_ops = &b53_switch_ops,
1190 },
1191 {
1192 .chip_id = BCM53115_DEVICE_ID,
1193 .dev_name = "BCM53115",
1194 .alias = "bcm53115",
1195 .vlans = 4096,
1196 .enabled_ports = 0x1f,
1197 .vta_regs = B53_VTA_REGS,
1198 .cpu_port = B53_CPU_PORT,
1199 .duplex_reg = B53_DUPLEX_STAT_GE,
1200 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1201 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1202 .sw_ops = &b53_switch_ops,
1203 },
1204 {
1205 .chip_id = BCM53125_DEVICE_ID,
1206 .dev_name = "BCM53125",
1207 .alias = "bcm53125",
1208 .vlans = 4096,
1209 .enabled_ports = 0x1f,
1210 .cpu_port = B53_CPU_PORT,
1211 .vta_regs = B53_VTA_REGS,
1212 .duplex_reg = B53_DUPLEX_STAT_GE,
1213 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1214 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1215 .sw_ops = &b53_switch_ops,
1216 },
1217 {
1218 .chip_id = BCM53128_DEVICE_ID,
1219 .dev_name = "BCM53128",
1220 .alias = "bcm53128",
1221 .vlans = 4096,
1222 .enabled_ports = 0x1ff,
1223 .cpu_port = B53_CPU_PORT,
1224 .vta_regs = B53_VTA_REGS,
1225 .duplex_reg = B53_DUPLEX_STAT_GE,
1226 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1227 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1228 .sw_ops = &b53_switch_ops,
1229 },
1230 {
1231 .chip_id = BCM63XX_DEVICE_ID,
1232 .dev_name = "BCM63xx",
1233 .alias = "bcm63xx",
1234 .vlans = 4096,
1235 .enabled_ports = 0, /* pdata must provide them */
1236 .cpu_port = B53_CPU_PORT,
1237 .vta_regs = B53_VTA_REGS_63XX,
1238 .duplex_reg = B53_DUPLEX_STAT_63XX,
1239 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1240 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1241 .sw_ops = &b53_switch_ops,
1242 },
1243 {
1244 .chip_id = BCM53010_DEVICE_ID,
1245 .dev_name = "BCM53010",
1246 .alias = "bcm53011",
1247 .vlans = 4096,
1248 .enabled_ports = 0x1f,
1249 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1250 .vta_regs = B53_VTA_REGS,
1251 .duplex_reg = B53_DUPLEX_STAT_GE,
1252 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1253 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1254 .sw_ops = &b53_switch_ops,
1255 },
1256 {
1257 .chip_id = BCM53011_DEVICE_ID,
1258 .dev_name = "BCM53011",
1259 .alias = "bcm53011",
1260 .vlans = 4096,
1261 .enabled_ports = 0x1bf,
1262 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1263 .vta_regs = B53_VTA_REGS,
1264 .duplex_reg = B53_DUPLEX_STAT_GE,
1265 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1266 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1267 .sw_ops = &b53_switch_ops,
1268 },
1269 {
1270 .chip_id = BCM53012_DEVICE_ID,
1271 .dev_name = "BCM53012",
1272 .alias = "bcm53011",
1273 .vlans = 4096,
1274 .enabled_ports = 0x1bf,
1275 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1276 .vta_regs = B53_VTA_REGS,
1277 .duplex_reg = B53_DUPLEX_STAT_GE,
1278 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1279 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1280 .sw_ops = &b53_switch_ops,
1281 },
1282 {
1283 .chip_id = BCM53018_DEVICE_ID,
1284 .dev_name = "BCM53018",
1285 .alias = "bcm53018",
1286 .vlans = 4096,
1287 .enabled_ports = 0x1f,
1288 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1289 .vta_regs = B53_VTA_REGS,
1290 .duplex_reg = B53_DUPLEX_STAT_GE,
1291 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1292 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1293 .sw_ops = &b53_switch_ops,
1294 },
1295 {
1296 .chip_id = BCM53019_DEVICE_ID,
1297 .dev_name = "BCM53019",
1298 .alias = "bcm53019",
1299 .vlans = 4096,
1300 .enabled_ports = 0x1f,
1301 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1302 .vta_regs = B53_VTA_REGS,
1303 .duplex_reg = B53_DUPLEX_STAT_GE,
1304 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1305 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1306 .sw_ops = &b53_switch_ops,
1307 },
1308 };
1309
1310 static int b53_switch_init(struct b53_device *dev)
1311 {
1312 struct switch_dev *sw_dev = &dev->sw_dev;
1313 unsigned i;
1314 int ret;
1315
1316 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1317 const struct b53_chip_data *chip = &b53_switch_chips[i];
1318
1319 if (chip->chip_id == dev->chip_id) {
1320 sw_dev->name = chip->dev_name;
1321 if (!sw_dev->alias)
1322 sw_dev->alias = chip->alias;
1323 if (!dev->enabled_ports)
1324 dev->enabled_ports = chip->enabled_ports;
1325 dev->duplex_reg = chip->duplex_reg;
1326 dev->vta_regs[0] = chip->vta_regs[0];
1327 dev->vta_regs[1] = chip->vta_regs[1];
1328 dev->vta_regs[2] = chip->vta_regs[2];
1329 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1330 sw_dev->ops = chip->sw_ops;
1331 sw_dev->cpu_port = chip->cpu_port;
1332 sw_dev->vlans = chip->vlans;
1333 break;
1334 }
1335 }
1336
1337 if (!sw_dev->name)
1338 return -EINVAL;
1339
1340 /* check which BCM5325x version we have */
1341 if (is5325(dev)) {
1342 u8 vc4;
1343
1344 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1345
1346 /* check reserved bits */
1347 switch (vc4 & 3) {
1348 case 1:
1349 /* BCM5325E */
1350 break;
1351 case 3:
1352 /* BCM5325F - do not use port 4 */
1353 dev->enabled_ports &= ~BIT(4);
1354 break;
1355 default:
1356 /* On the BCM47XX SoCs this is the supported internal switch.*/
1357 #ifndef CONFIG_BCM47XX
1358 /* BCM5325M */
1359 return -EINVAL;
1360 #else
1361 break;
1362 #endif
1363 }
1364 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1365 u64 strap_value;
1366
1367 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1368 /* use second IMP port if GMII is enabled */
1369 if (strap_value & SV_GMII_CTRL_115)
1370 sw_dev->cpu_port = 5;
1371 }
1372
1373 /* cpu port is always last */
1374 sw_dev->ports = sw_dev->cpu_port + 1;
1375 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1376
1377 dev->ports = devm_kzalloc(dev->dev,
1378 sizeof(struct b53_port) * sw_dev->ports,
1379 GFP_KERNEL);
1380 if (!dev->ports)
1381 return -ENOMEM;
1382
1383 dev->vlans = devm_kzalloc(dev->dev,
1384 sizeof(struct b53_vlan) * sw_dev->vlans,
1385 GFP_KERNEL);
1386 if (!dev->vlans)
1387 return -ENOMEM;
1388
1389 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1390 if (!dev->buf)
1391 return -ENOMEM;
1392
1393 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1394 if (dev->reset_gpio >= 0) {
1395 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1396 GPIOF_OUT_INIT_HIGH, "robo_reset");
1397 if (ret)
1398 return ret;
1399 }
1400
1401 return b53_switch_reset(dev);
1402 }
1403
1404 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1405 void *priv)
1406 {
1407 struct b53_device *dev;
1408
1409 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1410 if (!dev)
1411 return NULL;
1412
1413 dev->dev = base;
1414 dev->ops = ops;
1415 dev->priv = priv;
1416 mutex_init(&dev->reg_mutex);
1417
1418 return dev;
1419 }
1420 EXPORT_SYMBOL(b53_switch_alloc);
1421
1422 int b53_switch_detect(struct b53_device *dev)
1423 {
1424 u32 id32;
1425 u16 tmp;
1426 u8 id8;
1427 int ret;
1428
1429 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1430 if (ret)
1431 return ret;
1432
1433 switch (id8) {
1434 case 0:
1435 /*
1436 * BCM5325 and BCM5365 do not have this register so reads
1437 * return 0. But the read operation did succeed, so assume
1438 * this is one of them.
1439 *
1440 * Next check if we can write to the 5325's VTA register; for
1441 * 5365 it is read only.
1442 */
1443
1444 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1445 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1446
1447 if (tmp == 0xf)
1448 dev->chip_id = BCM5325_DEVICE_ID;
1449 else
1450 dev->chip_id = BCM5365_DEVICE_ID;
1451 break;
1452 case BCM5395_DEVICE_ID:
1453 case BCM5397_DEVICE_ID:
1454 case BCM5398_DEVICE_ID:
1455 dev->chip_id = id8;
1456 break;
1457 default:
1458 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1459 if (ret)
1460 return ret;
1461
1462 switch (id32) {
1463 case BCM53115_DEVICE_ID:
1464 case BCM53125_DEVICE_ID:
1465 case BCM53128_DEVICE_ID:
1466 case BCM53010_DEVICE_ID:
1467 case BCM53011_DEVICE_ID:
1468 case BCM53012_DEVICE_ID:
1469 case BCM53018_DEVICE_ID:
1470 case BCM53019_DEVICE_ID:
1471 dev->chip_id = id32;
1472 break;
1473 default:
1474 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1475 id8, id32);
1476 return -ENODEV;
1477 }
1478 }
1479
1480 if (dev->chip_id == BCM5325_DEVICE_ID)
1481 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1482 &dev->core_rev);
1483 else
1484 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1485 &dev->core_rev);
1486 }
1487 EXPORT_SYMBOL(b53_switch_detect);
1488
1489 int b53_switch_register(struct b53_device *dev)
1490 {
1491 int ret;
1492
1493 if (dev->pdata) {
1494 dev->chip_id = dev->pdata->chip_id;
1495 dev->enabled_ports = dev->pdata->enabled_ports;
1496 dev->sw_dev.alias = dev->pdata->alias;
1497 }
1498
1499 if (!dev->chip_id && b53_switch_detect(dev))
1500 return -EINVAL;
1501
1502 ret = b53_switch_init(dev);
1503 if (ret)
1504 return ret;
1505
1506 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1507
1508 return register_switch(&dev->sw_dev, NULL);
1509 }
1510 EXPORT_SYMBOL(b53_switch_register);
1511
1512 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1513 MODULE_DESCRIPTION("B53 switch library");
1514 MODULE_LICENSE("Dual BSD/GPL");
OpenWrt Source Repository