target/linux/generic/files/drivers/net/phy/b53/b53_regs.h

   1 /*
   2  * B53 register definitions
   3  *
   4  * Copyright (C) 2004 Broadcom Corporation
   5  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #ifndef __B53_REGS_H
  21 #define __B53_REGS_H
  22
  23 /* Management Port (SMP) Page offsets */
  24 #define B53_CTRL_PAGE                   0x00 /* Control */
  25 #define B53_STAT_PAGE                   0x01 /* Status */
  26 #define B53_MGMT_PAGE                   0x02 /* Management Mode */
  27 #define B53_MIB_AC_PAGE                 0x03 /* MIB Autocast */
  28 #define B53_ARLCTRL_PAGE                0x04 /* ARL Control */
  29 #define B53_ARLIO_PAGE                  0x05 /* ARL Access */
  30 #define B53_FRAMEBUF_PAGE               0x06 /* Management frame access */
  31 #define B53_MEM_ACCESS_PAGE             0x08 /* Memory access */
  32
  33 /* PHY Registers */
  34 #define B53_PORT_MII_PAGE(i)            (0x10 + (i)) /* Port i MII Registers */
  35 #define B53_IM_PORT_PAGE                0x18 /* Inverse MII Port (to EMAC) */
  36 #define B53_ALL_PORT_PAGE               0x19 /* All ports MII (broadcast) */
  37
  38 /* MIB registers */
  39 #define B53_MIB_PAGE(i)                 (0x20 + (i))
  40
  41 /* Quality of Service (QoS) Registers */
  42 #define B53_QOS_PAGE                    0x30
  43
  44 /* Port VLAN Page */
  45 #define B53_PVLAN_PAGE                  0x31
  46
  47 /* VLAN Registers */
  48 #define B53_VLAN_PAGE                   0x34
  49
  50 /* Jumbo Frame Registers */
  51 #define B53_JUMBO_PAGE                  0x40
  52
  53 /* CFP Configuration Registers Page */
  54 #define B53_CFP_PAGE                    0xa1
  55
  56 /*************************************************************************
  57  * Control Page registers
  58  *************************************************************************/
  59
  60 /* Port Control Register (8 bit) */
  61 #define B53_PORT_CTRL(i)                (0x00 + (i))
  62 #define   PORT_CTRL_RX_DISABLE          BIT(0)
  63 #define   PORT_CTRL_TX_DISABLE          BIT(1)
  64 #define   PORT_CTRL_RX_BCST_EN          BIT(2) /* Broadcast RX (P8 only) */
  65 #define   PORT_CTRL_RX_MCST_EN          BIT(3) /* Multicast RX (P8 only) */
  66 #define   PORT_CTRL_RX_UCST_EN          BIT(4) /* Unicast RX (P8 only) */
  67 #define   PORT_CTRL_STP_STATE_S         5
  68 #define   PORT_CTRL_STP_STATE_MASK      (0x7 << PORT_CTRL_STP_STATE_S)
  69
  70 /* SMP Control Register (8 bit) */
  71 #define B53_SMP_CTRL                    0x0a
  72
  73 /* Switch Mode Control Register (8 bit) */
  74 #define B53_SWITCH_MODE                 0x0b
  75 #define   SM_SW_FWD_MODE                BIT(0)  /* 1 = Managed Mode */
  76 #define   SM_SW_FWD_EN                  BIT(1)  /* Forwarding Enable */
  77
  78 /* IMP Port state override register (8 bit) */
  79 #define B53_PORT_OVERRIDE_CTRL          0x0e
  80 #define   PORT_OVERRIDE_LINK            BIT(0)
  81 #define   PORT_OVERRIDE_FULL_DUPLEX     BIT(1) /* 0 = Half Duplex */
  82 #define   PORT_OVERRIDE_SPEED_S         2
  83 #define   PORT_OVERRIDE_SPEED_10M       (0 << PORT_OVERRIDE_SPEED_S)
  84 #define   PORT_OVERRIDE_SPEED_100M      (1 << PORT_OVERRIDE_SPEED_S)
  85 #define   PORT_OVERRIDE_SPEED_1000M     (2 << PORT_OVERRIDE_SPEED_S)
  86 #define   PORT_OVERRIDE_RV_MII_25       BIT(4) /* BCM5325 only */
  87 #define   PORT_OVERRIDE_RX_FLOW         BIT(4)
  88 #define   PORT_OVERRIDE_TX_FLOW         BIT(5)
  89 #define   PORT_OVERRIDE_SPEED_2000M     BIT(6) /* BCM5301X only, requires setting 1000M */
  90 #define   PORT_OVERRIDE_EN              BIT(7) /* Use the register contents */
  91
  92 /* Power-down mode control */
  93 #define B53_PD_MODE_CTRL_25             0x0f
  94
  95 /* IP Multicast control (8 bit) */
  96 #define B53_IP_MULTICAST_CTRL           0x21
  97 #define  B53_IPMC_FWD_EN                BIT(1)
  98 #define  B53_UC_FWD_EN                  BIT(6)
  99 #define  B53_MC_FWD_EN                  BIT(7)
 100
 101 /* (16 bit) */
 102 #define B53_UC_FLOOD_MASK               0x32
 103 #define B53_MC_FLOOD_MASK               0x34
 104 #define B53_IPMC_FLOOD_MASK             0x36
 105
 106 /*
 107  * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
 108  *
 109  * For port 8 still use B53_PORT_OVERRIDE_CTRL
 110  * Please note that not all ports are available on every hardware, e.g. BCM5301X
 111  * don't include overriding port 6, BCM63xx also have some limitations.
 112  */
 113 #define B53_GMII_PORT_OVERRIDE_CTRL(i)  (0x58 + (i))
 114 #define   GMII_PO_LINK                  BIT(0)
 115 #define   GMII_PO_FULL_DUPLEX           BIT(1) /* 0 = Half Duplex */
 116 #define   GMII_PO_SPEED_S               2
 117 #define   GMII_PO_SPEED_10M             (0 << GMII_PO_SPEED_S)
 118 #define   GMII_PO_SPEED_100M            (1 << GMII_PO_SPEED_S)
 119 #define   GMII_PO_SPEED_1000M           (2 << GMII_PO_SPEED_S)
 120 #define   GMII_PO_RX_FLOW               BIT(4)
 121 #define   GMII_PO_TX_FLOW               BIT(5)
 122 #define   GMII_PO_EN                    BIT(6) /* Use the register contents */
 123 #define   GMII_PO_SPEED_2000M           BIT(7) /* BCM5301X only, requires setting 1000M */
 124
 125 /* Software reset register (8 bit) */
 126 #define B53_SOFTRESET                   0x79
 127
 128 /* Fast Aging Control register (8 bit) */
 129 #define B53_FAST_AGE_CTRL               0x88
 130 #define   FAST_AGE_STATIC               BIT(0)
 131 #define   FAST_AGE_DYNAMIC              BIT(1)
 132 #define   FAST_AGE_PORT                 BIT(2)
 133 #define   FAST_AGE_VLAN                 BIT(3)
 134 #define   FAST_AGE_STP                  BIT(4)
 135 #define   FAST_AGE_MC                   BIT(5)
 136 #define   FAST_AGE_DONE                 BIT(7)
 137
 138 /*************************************************************************
 139  * Status Page registers
 140  *************************************************************************/
 141
 142 /* Link Status Summary Register (16bit) */
 143 #define B53_LINK_STAT                   0x00
 144
 145 /* Link Status Change Register (16 bit) */
 146 #define B53_LINK_STAT_CHANGE            0x02
 147
 148 /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
 149 #define B53_SPEED_STAT                  0x04
 150 #define  SPEED_PORT_FE(reg, port)       (((reg) >> (port)) & 1)
 151 #define  SPEED_PORT_GE(reg, port)       (((reg) >> 2 * (port)) & 3)
 152 #define  SPEED_STAT_10M                 0
 153 #define  SPEED_STAT_100M                1
 154 #define  SPEED_STAT_1000M               2
 155
 156 /* Duplex Status Summary (16 bit) */
 157 #define B53_DUPLEX_STAT_FE              0x06
 158 #define B53_DUPLEX_STAT_GE              0x08
 159 #define B53_DUPLEX_STAT_63XX            0x0c
 160
 161 /* Revision ID register for BCM5325 */
 162 #define B53_REV_ID_25                   0x50
 163
 164 /* Strap Value (48 bit) */
 165 #define B53_STRAP_VALUE                 0x70
 166 #define   SV_GMII_CTRL_115              BIT(27)
 167
 168 /*************************************************************************
 169  * Management Mode Page Registers
 170  *************************************************************************/
 171
 172 /* Global Management Config Register (8 bit) */
 173 #define B53_GLOBAL_CONFIG               0x00
 174 #define   GC_RESET_MIB                  0x01
 175 #define   GC_RX_BPDU_EN                 0x02
 176 #define   GC_MIB_AC_HDR_EN              0x10
 177 #define   GC_MIB_AC_EN                  0x20
 178 #define   GC_FRM_MGMT_PORT_M            0xC0
 179 #define   GC_FRM_MGMT_PORT_04           0x00
 180 #define   GC_FRM_MGMT_PORT_MII          0x80
 181
 182 /* Broadcom Header control register (8 bit) */
 183 #define B53_BRCM_HDR                    0x03
 184 #define   BRCM_HDR_EN                   BIT(0) /* Enable tagging on IMP port */
 185
 186 /* Device ID register (8 or 32 bit) */
 187 #define B53_DEVICE_ID                   0x30
 188
 189 /* Revision ID register (8 bit) */
 190 #define B53_REV_ID                      0x40
 191
 192 /*************************************************************************
 193  * ARL Access Page Registers
 194  *************************************************************************/
 195
 196 /* VLAN Table Access Register (8 bit) */
 197 #define B53_VT_ACCESS                   0x80
 198 #define B53_VT_ACCESS_9798              0x60 /* for BCM5397/BCM5398 */
 199 #define B53_VT_ACCESS_63XX              0x60 /* for BCM6328/62/68 */
 200 #define   VTA_CMD_WRITE                 0
 201 #define   VTA_CMD_READ                  1
 202 #define   VTA_CMD_CLEAR                 2
 203 #define   VTA_START_CMD                 BIT(7)
 204
 205 /* VLAN Table Index Register (16 bit) */
 206 #define B53_VT_INDEX                    0x81
 207 #define B53_VT_INDEX_9798               0x61
 208 #define B53_VT_INDEX_63XX               0x62
 209
 210 /* VLAN Table Entry Register (32 bit) */
 211 #define B53_VT_ENTRY                    0x83
 212 #define B53_VT_ENTRY_9798               0x63
 213 #define B53_VT_ENTRY_63XX               0x64
 214 #define   VTE_MEMBERS                   0x1ff
 215 #define   VTE_UNTAG_S                   9
 216 #define   VTE_UNTAG                     (0x1ff << 9)
 217
 218 /*************************************************************************
 219  * Port VLAN Registers
 220  *************************************************************************/
 221
 222 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
 223 #define B53_PVLAN_PORT_MASK(i)          ((i) * 2)
 224
 225 /*************************************************************************
 226  * 802.1Q Page Registers
 227  *************************************************************************/
 228
 229 /* Global QoS Control (8 bit) */
 230 #define B53_QOS_GLOBAL_CTL              0x00
 231
 232 /* Enable 802.1Q for individual Ports (16 bit) */
 233 #define B53_802_1P_EN                   0x04
 234
 235 /*************************************************************************
 236  * VLAN Page Registers
 237  *************************************************************************/
 238
 239 /* VLAN Control 0 (8 bit) */
 240 #define B53_VLAN_CTRL0                  0x00
 241 #define   VC0_8021PF_CTRL_MASK          0x3
 242 #define   VC0_8021PF_CTRL_NONE          0x0
 243 #define   VC0_8021PF_CTRL_CHANGE_PRI    0x1
 244 #define   VC0_8021PF_CTRL_CHANGE_VID    0x2
 245 #define   VC0_8021PF_CTRL_CHANGE_BOTH   0x3
 246 #define   VC0_8021QF_CTRL_MASK          0xc
 247 #define   VC0_8021QF_CTRL_CHANGE_PRI    0x1
 248 #define   VC0_8021QF_CTRL_CHANGE_VID    0x2
 249 #define   VC0_8021QF_CTRL_CHANGE_BOTH   0x3
 250 #define   VC0_RESERVED_1                BIT(1)
 251 #define   VC0_DROP_VID_MISS             BIT(4)
 252 #define   VC0_VID_HASH_VID              BIT(5)
 253 #define   VC0_VID_CHK_EN                BIT(6)  /* Use VID,DA or VID,SA */
 254 #define   VC0_VLAN_EN                   BIT(7)  /* 802.1Q VLAN Enabled */
 255
 256 /* VLAN Control 1 (8 bit) */
 257 #define B53_VLAN_CTRL1                  0x01
 258 #define   VC1_RX_MCST_TAG_EN            BIT(1)
 259 #define   VC1_RX_MCST_FWD_EN            BIT(2)
 260 #define   VC1_RX_MCST_UNTAG_EN          BIT(3)
 261
 262 /* VLAN Control 2 (8 bit) */
 263 #define B53_VLAN_CTRL2                  0x02
 264
 265 /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
 266 #define B53_VLAN_CTRL3                  0x03
 267 #define B53_VLAN_CTRL3_63XX             0x04
 268 #define   VC3_MAXSIZE_1532              BIT(6) /* 5325 only */
 269 #define   VC3_HIGH_8BIT_EN              BIT(7) /* 5325 only */
 270
 271 /* VLAN Control 4 (8 bit) */
 272 #define B53_VLAN_CTRL4                  0x05
 273 #define B53_VLAN_CTRL4_25               0x04
 274 #define B53_VLAN_CTRL4_63XX             0x06
 275 #define   VC4_ING_VID_CHECK_S           6
 276 #define   VC4_ING_VID_CHECK_MASK        (0x3 << VC4_ING_VID_CHECK_S)
 277 #define   VC4_ING_VID_VIO_FWD           0 /* forward, but do not learn */
 278 #define   VC4_ING_VID_VIO_DROP          1 /* drop VID violations */
 279 #define   VC4_NO_ING_VID_CHK            2 /* do not check */
 280 #define   VC4_ING_VID_VIO_TO_IMP        3 /* redirect to MII port */
 281
 282 /* VLAN Control 5 (8 bit) */
 283 #define B53_VLAN_CTRL5                  0x06
 284 #define B53_VLAN_CTRL5_25               0x05
 285 #define B53_VLAN_CTRL5_63XX             0x07
 286 #define   VC5_VID_FFF_EN                BIT(2)
 287 #define   VC5_DROP_VTABLE_MISS          BIT(3)
 288
 289 /* VLAN Control 6 (8 bit) */
 290 #define B53_VLAN_CTRL6                  0x07
 291 #define B53_VLAN_CTRL6_63XX             0x08
 292
 293 /* VLAN Table Access Register (16 bit) */
 294 #define B53_VLAN_TABLE_ACCESS_25        0x06    /* BCM5325E/5350 */
 295 #define B53_VLAN_TABLE_ACCESS_65        0x08    /* BCM5365 */
 296 #define   VTA_VID_LOW_MASK_25           0xf
 297 #define   VTA_VID_LOW_MASK_65           0xff
 298 #define   VTA_VID_HIGH_S_25             4
 299 #define   VTA_VID_HIGH_S_65             8
 300 #define   VTA_VID_HIGH_MASK_25          (0xff << VTA_VID_HIGH_S_25E)
 301 #define   VTA_VID_HIGH_MASK_65          (0xf << VTA_VID_HIGH_S_65)
 302 #define   VTA_RW_STATE                  BIT(12)
 303 #define   VTA_RW_STATE_RD               0
 304 #define   VTA_RW_STATE_WR               BIT(12)
 305 #define   VTA_RW_OP_EN                  BIT(13)
 306
 307 /* VLAN Read/Write Registers for (16/32 bit) */
 308 #define B53_VLAN_WRITE_25               0x08
 309 #define B53_VLAN_WRITE_65               0x0a
 310 #define B53_VLAN_READ                   0x0c
 311 #define   VA_MEMBER_MASK                0x3f
 312 #define   VA_UNTAG_S_25                 6
 313 #define   VA_UNTAG_MASK_25              0x3f
 314 #define   VA_UNTAG_S_65                 7
 315 #define   VA_UNTAG_MASK_65              0x1f
 316 #define   VA_VID_HIGH_S                 12
 317 #define   VA_VID_HIGH_MASK              (0xffff << VA_VID_HIGH_S)
 318 #define   VA_VALID_25                   BIT(20)
 319 #define   VA_VALID_25_R4                BIT(24)
 320 #define   VA_VALID_65                   BIT(14)
 321
 322 /* VLAN Port Default Tag (16 bit) */
 323 #define B53_VLAN_PORT_DEF_TAG(i)        (0x10 + 2 * (i))
 324
 325 /*************************************************************************
 326  * Jumbo Frame Page Registers
 327  *************************************************************************/
 328
 329 /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
 330 #define B53_JUMBO_PORT_MASK             0x01
 331 #define B53_JUMBO_PORT_MASK_63XX        0x04
 332 #define   JPM_10_100_JUMBO_EN           BIT(24) /* GigE always enabled */
 333
 334 /* Good Frame Max Size without 802.1Q TAG (16 bit) */
 335 #define B53_JUMBO_MAX_SIZE              0x05
 336 #define B53_JUMBO_MAX_SIZE_63XX         0x08
 337 #define   JMS_MIN_SIZE                  1518
 338 #define   JMS_MAX_SIZE                  9724
 339
 340 /*************************************************************************
 341  * CFP Configuration Page Registers
 342  *************************************************************************/
 343
 344 /* CFP Control Register with ports map (8 bit) */
 345 #define B53_CFP_CTRL                    0x00
 346
 347 #endif /* !__B53_REGS_H */