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[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / mvsw61xx.c
1 /*
2 * Marvell 88E61xx switch driver
3 *
4 * Copyright (c) 2014 Claudio Leite <leitec@staticky.com>
5 * Copyright (c) 2014 Nikita Nazarenko <nnazarenko@radiofid.com>
6 *
7 * Based on code (c) 2008 Felix Fietkau <nbd@nbd.name>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License v2 as published by the
11 * Free Software Foundation
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/list.h>
18 #include <linux/mii.h>
19 #include <linux/phy.h>
20 #include <linux/of.h>
21 #include <linux/of_mdio.h>
22 #include <linux/delay.h>
23 #include <linux/switch.h>
24 #include <linux/device.h>
25 #include <linux/platform_device.h>
26
27 #include "mvsw61xx.h"
28
29 MODULE_DESCRIPTION("Marvell 88E61xx Switch driver");
30 MODULE_AUTHOR("Claudio Leite <leitec@staticky.com>");
31 MODULE_AUTHOR("Nikita Nazarenko <nnazarenko@radiofid.com>");
32 MODULE_LICENSE("GPL v2");
33 MODULE_ALIAS("platform:mvsw61xx");
34
35 /*
36 * Register access is done through direct or indirect addressing,
37 * depending on how the switch is physically connected.
38 *
39 * Direct addressing: all port and global registers directly
40 * accessible via an address/register pair
41 *
42 * Indirect addressing: switch is mapped at a single address,
43 * port and global registers accessible via a single command/data
44 * register pair
45 */
46
47 static int
48 mvsw61xx_wait_mask_raw(struct mii_bus *bus, int addr,
49 int reg, u16 mask, u16 val)
50 {
51 int i = 100;
52 u16 r;
53
54 do {
55 r = bus->read(bus, addr, reg);
56 if ((r & mask) == val)
57 return 0;
58 } while (--i > 0);
59
60 return -ETIMEDOUT;
61 }
62
63 static u16
64 r16(struct mii_bus *bus, bool indirect, int base_addr, int addr, int reg)
65 {
66 u16 ind_addr;
67
68 if (!indirect)
69 return bus->read(bus, addr, reg);
70
71 /* Indirect read: First, make sure switch is free */
72 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
73 MV_INDIRECT_INPROGRESS, 0);
74
75 /* Load address and request read */
76 ind_addr = MV_INDIRECT_READ | (addr << MV_INDIRECT_ADDR_S) | reg;
77 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
78 ind_addr);
79
80 /* Wait until it's ready */
81 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
82 MV_INDIRECT_INPROGRESS, 0);
83
84 /* Read the requested data */
85 return bus->read(bus, base_addr, MV_INDIRECT_REG_DATA);
86 }
87
88 static void
89 w16(struct mii_bus *bus, bool indirect, int base_addr, int addr,
90 int reg, u16 val)
91 {
92 u16 ind_addr;
93
94 if (!indirect) {
95 bus->write(bus, addr, reg, val);
96 return;
97 }
98
99 /* Indirect write: First, make sure switch is free */
100 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
101 MV_INDIRECT_INPROGRESS, 0);
102
103 /* Load the data to be written */
104 bus->write(bus, base_addr, MV_INDIRECT_REG_DATA, val);
105
106 /* Wait again for switch to be free */
107 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
108 MV_INDIRECT_INPROGRESS, 0);
109
110 /* Load address, and issue write command */
111 ind_addr = MV_INDIRECT_WRITE | (addr << MV_INDIRECT_ADDR_S) | reg;
112 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
113 ind_addr);
114 }
115
116 /* swconfig support */
117
118 static inline u16
119 sr16(struct switch_dev *dev, int addr, int reg)
120 {
121 struct mvsw61xx_state *state = get_state(dev);
122
123 return r16(state->bus, state->is_indirect, state->base_addr, addr, reg);
124 }
125
126 static inline void
127 sw16(struct switch_dev *dev, int addr, int reg, u16 val)
128 {
129 struct mvsw61xx_state *state = get_state(dev);
130
131 w16(state->bus, state->is_indirect, state->base_addr, addr, reg, val);
132 }
133
134 static int
135 mvsw61xx_wait_mask_s(struct switch_dev *dev, int addr,
136 int reg, u16 mask, u16 val)
137 {
138 int i = 100;
139 u16 r;
140
141 do {
142 r = sr16(dev, addr, reg) & mask;
143 if (r == val)
144 return 0;
145 } while (--i > 0);
146
147 return -ETIMEDOUT;
148 }
149
150 static int
151 mvsw61xx_get_port_mask(struct switch_dev *dev,
152 const struct switch_attr *attr, struct switch_val *val)
153 {
154 struct mvsw61xx_state *state = get_state(dev);
155 char *buf = state->buf;
156 int port, len, i;
157 u16 reg;
158
159 port = val->port_vlan;
160 reg = sr16(dev, MV_PORTREG(VLANMAP, port)) & MV_PORTS_MASK;
161
162 len = sprintf(buf, "0x%04x: ", reg);
163
164 for (i = 0; i < MV_PORTS; i++) {
165 if (reg & (1 << i))
166 len += sprintf(buf + len, "%d ", i);
167 else if (i == port)
168 len += sprintf(buf + len, "(%d) ", i);
169 }
170
171 val->value.s = buf;
172
173 return 0;
174 }
175
176 static int
177 mvsw61xx_get_port_qmode(struct switch_dev *dev,
178 const struct switch_attr *attr, struct switch_val *val)
179 {
180 struct mvsw61xx_state *state = get_state(dev);
181
182 val->value.i = state->ports[val->port_vlan].qmode;
183
184 return 0;
185 }
186
187 static int
188 mvsw61xx_set_port_qmode(struct switch_dev *dev,
189 const struct switch_attr *attr, struct switch_val *val)
190 {
191 struct mvsw61xx_state *state = get_state(dev);
192
193 state->ports[val->port_vlan].qmode = val->value.i;
194
195 return 0;
196 }
197
198 static int
199 mvsw61xx_get_port_pvid(struct switch_dev *dev, int port, int *val)
200 {
201 struct mvsw61xx_state *state = get_state(dev);
202
203 *val = state->ports[port].pvid;
204
205 return 0;
206 }
207
208 static int
209 mvsw61xx_set_port_pvid(struct switch_dev *dev, int port, int val)
210 {
211 struct mvsw61xx_state *state = get_state(dev);
212
213 if (val < 0 || val >= MV_VLANS)
214 return -EINVAL;
215
216 state->ports[port].pvid = (u16)val;
217
218 return 0;
219 }
220
221 static int
222 mvsw61xx_get_port_link(struct switch_dev *dev, int port,
223 struct switch_port_link *link)
224 {
225 u16 status, speed;
226
227 status = sr16(dev, MV_PORTREG(STATUS, port));
228
229 link->link = status & MV_PORT_STATUS_LINK;
230 if (!link->link)
231 return 0;
232
233 link->duplex = status & MV_PORT_STATUS_FDX;
234
235 speed = (status & MV_PORT_STATUS_SPEED_MASK) >>
236 MV_PORT_STATUS_SPEED_SHIFT;
237
238 switch (speed) {
239 case MV_PORT_STATUS_SPEED_10:
240 link->speed = SWITCH_PORT_SPEED_10;
241 break;
242 case MV_PORT_STATUS_SPEED_100:
243 link->speed = SWITCH_PORT_SPEED_100;
244 break;
245 case MV_PORT_STATUS_SPEED_1000:
246 link->speed = SWITCH_PORT_SPEED_1000;
247 break;
248 }
249
250 return 0;
251 }
252
253 static int mvsw61xx_get_vlan_ports(struct switch_dev *dev,
254 struct switch_val *val)
255 {
256 struct mvsw61xx_state *state = get_state(dev);
257 int i, j, mode, vno;
258
259 vno = val->port_vlan;
260
261 if (vno <= 0 || vno >= dev->vlans)
262 return -EINVAL;
263
264 for (i = 0, j = 0; i < dev->ports; i++) {
265 if (state->vlans[vno].mask & (1 << i)) {
266 val->value.ports[j].id = i;
267
268 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
269 if (mode == MV_VTUCTL_EGRESS_TAGGED)
270 val->value.ports[j].flags =
271 (1 << SWITCH_PORT_FLAG_TAGGED);
272 else
273 val->value.ports[j].flags = 0;
274
275 j++;
276 }
277 }
278
279 val->len = j;
280
281 return 0;
282 }
283
284 static int mvsw61xx_set_vlan_ports(struct switch_dev *dev,
285 struct switch_val *val)
286 {
287 struct mvsw61xx_state *state = get_state(dev);
288 int i, mode, pno, vno;
289
290 vno = val->port_vlan;
291
292 if (vno <= 0 || vno >= dev->vlans)
293 return -EINVAL;
294
295 state->vlans[vno].mask = 0;
296 state->vlans[vno].port_mode = 0;
297 state->vlans[vno].port_sstate = 0;
298
299 if(state->vlans[vno].vid == 0)
300 state->vlans[vno].vid = vno;
301
302 for (i = 0; i < val->len; i++) {
303 pno = val->value.ports[i].id;
304
305 state->vlans[vno].mask |= (1 << pno);
306 if (val->value.ports[i].flags &
307 (1 << SWITCH_PORT_FLAG_TAGGED))
308 mode = MV_VTUCTL_EGRESS_TAGGED;
309 else
310 mode = MV_VTUCTL_EGRESS_UNTAGGED;
311
312 state->vlans[vno].port_mode |= mode << (pno * 4);
313 state->vlans[vno].port_sstate |=
314 MV_STUCTL_STATE_FORWARDING << (pno * 4 + 2);
315 }
316
317 /*
318 * DISCARD is nonzero, so it must be explicitly
319 * set on ports not in the VLAN.
320 */
321 for (i = 0; i < dev->ports; i++)
322 if (!(state->vlans[vno].mask & (1 << i)))
323 state->vlans[vno].port_mode |=
324 MV_VTUCTL_DISCARD << (i * 4);
325
326 return 0;
327 }
328
329 static int mvsw61xx_get_vlan_port_based(struct switch_dev *dev,
330 const struct switch_attr *attr, struct switch_val *val)
331 {
332 struct mvsw61xx_state *state = get_state(dev);
333 int vno = val->port_vlan;
334
335 if (vno <= 0 || vno >= dev->vlans)
336 return -EINVAL;
337
338 if (state->vlans[vno].port_based)
339 val->value.i = 1;
340 else
341 val->value.i = 0;
342
343 return 0;
344 }
345
346 static int mvsw61xx_set_vlan_port_based(struct switch_dev *dev,
347 const struct switch_attr *attr, struct switch_val *val)
348 {
349 struct mvsw61xx_state *state = get_state(dev);
350 int vno = val->port_vlan;
351
352 if (vno <= 0 || vno >= dev->vlans)
353 return -EINVAL;
354
355 if (val->value.i == 1)
356 state->vlans[vno].port_based = true;
357 else
358 state->vlans[vno].port_based = false;
359
360 return 0;
361 }
362
363 static int mvsw61xx_get_vid(struct switch_dev *dev,
364 const struct switch_attr *attr, struct switch_val *val)
365 {
366 struct mvsw61xx_state *state = get_state(dev);
367 int vno = val->port_vlan;
368
369 if (vno <= 0 || vno >= dev->vlans)
370 return -EINVAL;
371
372 val->value.i = state->vlans[vno].vid;
373
374 return 0;
375 }
376
377 static int mvsw61xx_set_vid(struct switch_dev *dev,
378 const struct switch_attr *attr, struct switch_val *val)
379 {
380 struct mvsw61xx_state *state = get_state(dev);
381 int vno = val->port_vlan;
382
383 if (vno <= 0 || vno >= dev->vlans)
384 return -EINVAL;
385
386 state->vlans[vno].vid = val->value.i;
387
388 return 0;
389 }
390
391 static int mvsw61xx_get_enable_vlan(struct switch_dev *dev,
392 const struct switch_attr *attr, struct switch_val *val)
393 {
394 struct mvsw61xx_state *state = get_state(dev);
395
396 val->value.i = state->vlan_enabled;
397
398 return 0;
399 }
400
401 static int mvsw61xx_set_enable_vlan(struct switch_dev *dev,
402 const struct switch_attr *attr, struct switch_val *val)
403 {
404 struct mvsw61xx_state *state = get_state(dev);
405
406 state->vlan_enabled = val->value.i;
407
408 return 0;
409 }
410
411 static int mvsw61xx_vtu_program(struct switch_dev *dev)
412 {
413 struct mvsw61xx_state *state = get_state(dev);
414 u16 v1, v2, s1, s2;
415 int i;
416
417 /* Flush */
418 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
419 MV_VTUOP_INPROGRESS, 0);
420 sw16(dev, MV_GLOBALREG(VTU_OP),
421 MV_VTUOP_INPROGRESS | MV_VTUOP_PURGE);
422
423 /* Write VLAN table */
424 for (i = 1; i < dev->vlans; i++) {
425 if (state->vlans[i].mask == 0 ||
426 state->vlans[i].vid == 0 ||
427 state->vlans[i].port_based == true)
428 continue;
429
430 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
431 MV_VTUOP_INPROGRESS, 0);
432
433 /* Write per-VLAN port state into STU */
434 s1 = (u16) (state->vlans[i].port_sstate & 0xffff);
435 s2 = (u16) ((state->vlans[i].port_sstate >> 16) & 0xffff);
436
437 sw16(dev, MV_GLOBALREG(VTU_VID), MV_VTU_VID_VALID);
438 sw16(dev, MV_GLOBALREG(VTU_SID), i);
439 sw16(dev, MV_GLOBALREG(VTU_DATA1), s1);
440 sw16(dev, MV_GLOBALREG(VTU_DATA2), s2);
441 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
442
443 sw16(dev, MV_GLOBALREG(VTU_OP),
444 MV_VTUOP_INPROGRESS | MV_VTUOP_STULOAD);
445 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
446 MV_VTUOP_INPROGRESS, 0);
447
448 /* Write VLAN information into VTU */
449 v1 = (u16) (state->vlans[i].port_mode & 0xffff);
450 v2 = (u16) ((state->vlans[i].port_mode >> 16) & 0xffff);
451
452 sw16(dev, MV_GLOBALREG(VTU_VID),
453 MV_VTU_VID_VALID | state->vlans[i].vid);
454 sw16(dev, MV_GLOBALREG(VTU_SID), i);
455 sw16(dev, MV_GLOBALREG(VTU_FID), i);
456 sw16(dev, MV_GLOBALREG(VTU_DATA1), v1);
457 sw16(dev, MV_GLOBALREG(VTU_DATA2), v2);
458 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
459
460 sw16(dev, MV_GLOBALREG(VTU_OP),
461 MV_VTUOP_INPROGRESS | MV_VTUOP_LOAD);
462 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
463 MV_VTUOP_INPROGRESS, 0);
464 }
465
466 return 0;
467 }
468
469 static void mvsw61xx_vlan_port_config(struct switch_dev *dev, int vno)
470 {
471 struct mvsw61xx_state *state = get_state(dev);
472 int i, mode;
473
474 for (i = 0; i < dev->ports; i++) {
475 if (!(state->vlans[vno].mask & (1 << i)))
476 continue;
477
478 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
479
480 if(mode != MV_VTUCTL_EGRESS_TAGGED)
481 state->ports[i].pvid = state->vlans[vno].vid;
482
483 if (state->vlans[vno].port_based) {
484 state->ports[i].mask |= state->vlans[vno].mask;
485 state->ports[i].fdb = vno;
486 }
487 else
488 state->ports[i].qmode = MV_8021Q_MODE_SECURE;
489 }
490 }
491
492 static int mvsw61xx_update_state(struct switch_dev *dev)
493 {
494 struct mvsw61xx_state *state = get_state(dev);
495 int i;
496 u16 reg;
497
498 if (!state->registered)
499 return -EINVAL;
500
501 /*
502 * Set 802.1q-only mode if vlan_enabled is true.
503 *
504 * Without this, even if 802.1q is enabled for
505 * a port/VLAN, it still depends on the port-based
506 * VLAN mask being set.
507 *
508 * With this setting, port-based VLANs are still
509 * functional, provided the VID is not in the VTU.
510 */
511 reg = sr16(dev, MV_GLOBAL2REG(SDET_POLARITY));
512
513 if (state->vlan_enabled)
514 reg |= MV_8021Q_VLAN_ONLY;
515 else
516 reg &= ~MV_8021Q_VLAN_ONLY;
517
518 sw16(dev, MV_GLOBAL2REG(SDET_POLARITY), reg);
519
520 /*
521 * Set port-based VLAN masks on each port
522 * based only on VLAN definitions known to
523 * the driver (i.e. in state).
524 *
525 * This means any pre-existing port mapping is
526 * wiped out once our driver is initialized.
527 */
528 for (i = 0; i < dev->ports; i++) {
529 state->ports[i].mask = 0;
530 state->ports[i].qmode = MV_8021Q_MODE_DISABLE;
531 }
532
533 for (i = 0; i < dev->vlans; i++)
534 mvsw61xx_vlan_port_config(dev, i);
535
536 for (i = 0; i < dev->ports; i++) {
537 reg = sr16(dev, MV_PORTREG(VLANID, i)) & ~MV_PVID_MASK;
538 reg |= state->ports[i].pvid;
539 sw16(dev, MV_PORTREG(VLANID, i), reg);
540
541 state->ports[i].mask &= ~(1 << i);
542
543 /* set default forwarding DB number and port mask */
544 reg = sr16(dev, MV_PORTREG(CONTROL1, i)) & ~MV_FDB_HI_MASK;
545 reg |= (state->ports[i].fdb >> MV_FDB_HI_SHIFT) &
546 MV_FDB_HI_MASK;
547 sw16(dev, MV_PORTREG(CONTROL1, i), reg);
548
549 reg = ((state->ports[i].fdb & 0xf) << MV_FDB_LO_SHIFT) |
550 state->ports[i].mask;
551 sw16(dev, MV_PORTREG(VLANMAP, i), reg);
552
553 reg = sr16(dev, MV_PORTREG(CONTROL2, i)) &
554 ~MV_8021Q_MODE_MASK;
555 reg |= state->ports[i].qmode << MV_8021Q_MODE_SHIFT;
556 sw16(dev, MV_PORTREG(CONTROL2, i), reg);
557 }
558
559 mvsw61xx_vtu_program(dev);
560
561 return 0;
562 }
563
564 static int mvsw61xx_apply(struct switch_dev *dev)
565 {
566 return mvsw61xx_update_state(dev);
567 }
568
569 static int mvsw61xx_reset(struct switch_dev *dev)
570 {
571 struct mvsw61xx_state *state = get_state(dev);
572 int i;
573 u16 reg;
574
575 /* Disable all ports before reset */
576 for (i = 0; i < dev->ports; i++) {
577 reg = sr16(dev, MV_PORTREG(CONTROL, i)) &
578 ~MV_PORTCTRL_FORWARDING;
579 sw16(dev, MV_PORTREG(CONTROL, i), reg);
580 }
581
582 reg = sr16(dev, MV_GLOBALREG(CONTROL)) | MV_CONTROL_RESET;
583
584 sw16(dev, MV_GLOBALREG(CONTROL), reg);
585 if (mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(CONTROL),
586 MV_CONTROL_RESET, 0) < 0)
587 return -ETIMEDOUT;
588
589 for (i = 0; i < dev->ports; i++) {
590 state->ports[i].fdb = 0;
591 state->ports[i].qmode = 0;
592 state->ports[i].mask = 0;
593 state->ports[i].pvid = 0;
594
595 /* Force flow control off */
596 reg = sr16(dev, MV_PORTREG(PHYCTL, i)) & ~MV_PHYCTL_FC_MASK;
597 reg |= MV_PHYCTL_FC_DISABLE;
598 sw16(dev, MV_PORTREG(PHYCTL, i), reg);
599
600 /* Set port association vector */
601 sw16(dev, MV_PORTREG(ASSOC, i), (1 << i));
602 }
603
604 for (i = 0; i < dev->vlans; i++) {
605 state->vlans[i].port_based = false;
606 state->vlans[i].mask = 0;
607 state->vlans[i].vid = 0;
608 state->vlans[i].port_mode = 0;
609 state->vlans[i].port_sstate = 0;
610 }
611
612 state->vlan_enabled = 0;
613
614 mvsw61xx_update_state(dev);
615
616 /* Re-enable ports */
617 for (i = 0; i < dev->ports; i++) {
618 reg = sr16(dev, MV_PORTREG(CONTROL, i)) |
619 MV_PORTCTRL_FORWARDING;
620 sw16(dev, MV_PORTREG(CONTROL, i), reg);
621 }
622
623 return 0;
624 }
625
626 enum {
627 MVSW61XX_ENABLE_VLAN,
628 };
629
630 enum {
631 MVSW61XX_VLAN_PORT_BASED,
632 MVSW61XX_VLAN_ID,
633 };
634
635 enum {
636 MVSW61XX_PORT_MASK,
637 MVSW61XX_PORT_QMODE,
638 };
639
640 static const struct switch_attr mvsw61xx_global[] = {
641 [MVSW61XX_ENABLE_VLAN] = {
642 .id = MVSW61XX_ENABLE_VLAN,
643 .type = SWITCH_TYPE_INT,
644 .name = "enable_vlan",
645 .description = "Enable 802.1q VLAN support",
646 .get = mvsw61xx_get_enable_vlan,
647 .set = mvsw61xx_set_enable_vlan,
648 },
649 };
650
651 static const struct switch_attr mvsw61xx_vlan[] = {
652 [MVSW61XX_VLAN_PORT_BASED] = {
653 .id = MVSW61XX_VLAN_PORT_BASED,
654 .type = SWITCH_TYPE_INT,
655 .name = "port_based",
656 .description = "Use port-based (non-802.1q) VLAN only",
657 .get = mvsw61xx_get_vlan_port_based,
658 .set = mvsw61xx_set_vlan_port_based,
659 },
660 [MVSW61XX_VLAN_ID] = {
661 .id = MVSW61XX_VLAN_ID,
662 .type = SWITCH_TYPE_INT,
663 .name = "vid",
664 .description = "Get/set VLAN ID",
665 .get = mvsw61xx_get_vid,
666 .set = mvsw61xx_set_vid,
667 },
668 };
669
670 static const struct switch_attr mvsw61xx_port[] = {
671 [MVSW61XX_PORT_MASK] = {
672 .id = MVSW61XX_PORT_MASK,
673 .type = SWITCH_TYPE_STRING,
674 .description = "Port-based VLAN mask",
675 .name = "mask",
676 .get = mvsw61xx_get_port_mask,
677 .set = NULL,
678 },
679 [MVSW61XX_PORT_QMODE] = {
680 .id = MVSW61XX_PORT_QMODE,
681 .type = SWITCH_TYPE_INT,
682 .description = "802.1q mode: 0=off/1=fallback/2=check/3=secure",
683 .name = "qmode",
684 .get = mvsw61xx_get_port_qmode,
685 .set = mvsw61xx_set_port_qmode,
686 },
687 };
688
689 static const struct switch_dev_ops mvsw61xx_ops = {
690 .attr_global = {
691 .attr = mvsw61xx_global,
692 .n_attr = ARRAY_SIZE(mvsw61xx_global),
693 },
694 .attr_vlan = {
695 .attr = mvsw61xx_vlan,
696 .n_attr = ARRAY_SIZE(mvsw61xx_vlan),
697 },
698 .attr_port = {
699 .attr = mvsw61xx_port,
700 .n_attr = ARRAY_SIZE(mvsw61xx_port),
701 },
702 .get_port_link = mvsw61xx_get_port_link,
703 .get_port_pvid = mvsw61xx_get_port_pvid,
704 .set_port_pvid = mvsw61xx_set_port_pvid,
705 .get_vlan_ports = mvsw61xx_get_vlan_ports,
706 .set_vlan_ports = mvsw61xx_set_vlan_ports,
707 .apply_config = mvsw61xx_apply,
708 .reset_switch = mvsw61xx_reset,
709 };
710
711 /* end swconfig stuff */
712
713 static int mvsw61xx_probe(struct platform_device *pdev)
714 {
715 struct mvsw61xx_state *state;
716 struct device_node *np = pdev->dev.of_node;
717 struct device_node *mdio;
718 char *model_str;
719 u32 val;
720 int err;
721
722 state = kzalloc(sizeof(*state), GFP_KERNEL);
723 if (!state)
724 return -ENOMEM;
725
726 mdio = of_parse_phandle(np, "mii-bus", 0);
727 if (!mdio) {
728 dev_err(&pdev->dev, "Couldn't get MII bus handle\n");
729 err = -ENODEV;
730 goto out_err;
731 }
732
733 state->bus = of_mdio_find_bus(mdio);
734 if (!state->bus) {
735 dev_err(&pdev->dev, "Couldn't find MII bus from handle\n");
736 err = -ENODEV;
737 goto out_err;
738 }
739
740 state->is_indirect = of_property_read_bool(np, "is-indirect");
741
742 if (state->is_indirect) {
743 if (of_property_read_u32(np, "reg", &val)) {
744 dev_err(&pdev->dev, "Switch address not specified\n");
745 err = -ENODEV;
746 goto out_err;
747 }
748
749 state->base_addr = val;
750 } else {
751 state->base_addr = MV_BASE;
752 }
753
754 state->model = r16(state->bus, state->is_indirect, state->base_addr,
755 MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK;
756
757 switch(state->model) {
758 case MV_IDENT_VALUE_6171:
759 model_str = MV_IDENT_STR_6171;
760 break;
761 case MV_IDENT_VALUE_6172:
762 model_str = MV_IDENT_STR_6172;
763 break;
764 case MV_IDENT_VALUE_6176:
765 model_str = MV_IDENT_STR_6176;
766 break;
767 default:
768 dev_err(&pdev->dev, "No compatible switch found at 0x%02x\n",
769 state->base_addr);
770 err = -ENODEV;
771 goto out_err;
772 }
773
774 platform_set_drvdata(pdev, state);
775 dev_info(&pdev->dev, "Found %s at %s:%02x\n", model_str,
776 state->bus->id, state->base_addr);
777
778 dev_info(&pdev->dev, "Using %sdirect addressing\n",
779 (state->is_indirect ? "in" : ""));
780
781 if (of_property_read_u32(np, "cpu-port-0", &val)) {
782 dev_err(&pdev->dev, "CPU port not set\n");
783 err = -ENODEV;
784 goto out_err;
785 }
786
787 state->cpu_port0 = val;
788
789 if (!of_property_read_u32(np, "cpu-port-1", &val))
790 state->cpu_port1 = val;
791 else
792 state->cpu_port1 = -1;
793
794 state->dev.vlans = MV_VLANS;
795 state->dev.cpu_port = state->cpu_port0;
796 state->dev.ports = MV_PORTS;
797 state->dev.name = model_str;
798 state->dev.ops = &mvsw61xx_ops;
799 state->dev.alias = dev_name(&pdev->dev);
800
801 err = register_switch(&state->dev, NULL);
802 if (err < 0)
803 goto out_err;
804
805 state->registered = true;
806
807 return 0;
808 out_err:
809 kfree(state);
810 return err;
811 }
812
813 static int
814 mvsw61xx_remove(struct platform_device *pdev)
815 {
816 struct mvsw61xx_state *state = platform_get_drvdata(pdev);
817
818 if (state->registered)
819 unregister_switch(&state->dev);
820
821 kfree(state);
822
823 return 0;
824 }
825
826 static const struct of_device_id mvsw61xx_match[] = {
827 { .compatible = "marvell,88e6171" },
828 { .compatible = "marvell,88e6172" },
829 { .compatible = "marvell,88e6176" },
830 { }
831 };
832 MODULE_DEVICE_TABLE(of, mvsw61xx_match);
833
834 static struct platform_driver mvsw61xx_driver = {
835 .probe = mvsw61xx_probe,
836 .remove = mvsw61xx_remove,
837 .driver = {
838 .name = "mvsw61xx",
839 .of_match_table = of_match_ptr(mvsw61xx_match),
840 .owner = THIS_MODULE,
841 },
842 };
843
844 static int __init mvsw61xx_module_init(void)
845 {
846 return platform_driver_register(&mvsw61xx_driver);
847 }
848 late_initcall(mvsw61xx_module_init);
849
850 static void __exit mvsw61xx_module_exit(void)
851 {
852 platform_driver_unregister(&mvsw61xx_driver);
853 }
854 module_exit(mvsw61xx_module_exit);
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