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generic: rtl8366rb: fix compatible string
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366RB ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
7 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/of.h>
19 #include <linux/of_platform.h>
20 #include <linux/delay.h>
21 #include <linux/skbuff.h>
22 #include <linux/rtl8366.h>
23
24 #include "rtl8366_smi.h"
25
26 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
27 #define RTL8366RB_DRIVER_VER "0.2.4"
28
29 #define RTL8366RB_PHY_NO_MAX 4
30 #define RTL8366RB_PHY_PAGE_MAX 7
31 #define RTL8366RB_PHY_ADDR_MAX 31
32
33 /* Switch Global Configuration register */
34 #define RTL8366RB_SGCR 0x0000
35 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
36 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
37 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
39 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
40 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
41 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
42 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
43 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
44
45 /* Port Enable Control register */
46 #define RTL8366RB_PECR 0x0001
47
48 /* Port Mirror Control Register */
49 #define RTL8366RB_PMCR 0x0007
50 #define RTL8366RB_PMCR_SOURCE_PORT(_x) (_x)
51 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
52 #define RTL8366RB_PMCR_MONITOR_PORT(_x) ((_x) << 4)
53 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
54 #define RTL8366RB_PMCR_MIRROR_RX BIT(8)
55 #define RTL8366RB_PMCR_MIRROR_TX BIT(9)
56 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
57 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
58
59 /* Switch Security Control registers */
60 #define RTL8366RB_SSCR0 0x0002
61 #define RTL8366RB_SSCR1 0x0003
62 #define RTL8366RB_SSCR2 0x0004
63 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
64
65 #define RTL8366RB_RESET_CTRL_REG 0x0100
66 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
67 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
68
69 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
70 #define RTL8366RB_CHIP_VERSION_MASK 0xf
71 #define RTL8366RB_CHIP_ID_REG 0x0509
72 #define RTL8366RB_CHIP_ID_8366 0x5937
73
74 /* PHY registers control */
75 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
76 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
77
78 #define RTL8366RB_PHY_CTRL_READ 1
79 #define RTL8366RB_PHY_CTRL_WRITE 0
80
81 #define RTL8366RB_PHY_REG_MASK 0x1f
82 #define RTL8366RB_PHY_PAGE_OFFSET 5
83 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
84 #define RTL8366RB_PHY_NO_OFFSET 9
85 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
86
87 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
88
89 /* LED control registers */
90 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
91 #define RTL8366RB_LED_BLINKRATE_BIT 0
92 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
93
94 #define RTL8366RB_LED_CTRL_REG 0x0431
95 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
96 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
97
98 #define RTL8366RB_MIB_COUNT 33
99 #define RTL8366RB_GLOBAL_MIB_COUNT 1
100 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
101 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
102 #define RTL8366RB_MIB_CTRL_REG 0x13F0
103 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
104 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
105 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
106 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
107 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
108
109 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
110 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
111 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
112 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
113 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
114
115
116 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
117 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
118
119
120 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
121 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
122 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
123
124 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
125
126
127 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
128 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
129 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
130 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
131 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
132 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
133 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
134
135
136 #define RTL8366RB_PORT_NUM_CPU 5
137 #define RTL8366RB_NUM_PORTS 6
138 #define RTL8366RB_NUM_VLANS 16
139 #define RTL8366RB_NUM_LEDGROUPS 4
140 #define RTL8366RB_NUM_VIDS 4096
141 #define RTL8366RB_PRIORITYMAX 7
142 #define RTL8366RB_FIDMAX 7
143
144
145 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
146 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
147 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
148 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
149 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
150
151 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
152
153 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
154 RTL8366RB_PORT_2 | \
155 RTL8366RB_PORT_3 | \
156 RTL8366RB_PORT_4 | \
157 RTL8366RB_PORT_5 | \
158 RTL8366RB_PORT_CPU)
159
160 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
161 RTL8366RB_PORT_2 | \
162 RTL8366RB_PORT_3 | \
163 RTL8366RB_PORT_4 | \
164 RTL8366RB_PORT_5)
165
166 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
167 RTL8366RB_PORT_2 | \
168 RTL8366RB_PORT_3 | \
169 RTL8366RB_PORT_4)
170
171 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
172
173 #define RTL8366RB_VLAN_VID_MASK 0xfff
174 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
175 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
176 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
177 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
178 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
179 #define RTL8366RB_VLAN_FID_MASK 0x7
180
181
182 /* Port ingress bandwidth control */
183 #define RTL8366RB_IB_BASE 0x0200
184 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
185 #define RTL8366RB_IB_BDTH_MASK 0x3fff
186 #define RTL8366RB_IB_PREIFG_OFFSET 14
187 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
188
189 /* Port egress bandwidth control */
190 #define RTL8366RB_EB_BASE 0x02d1
191 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
192 #define RTL8366RB_EB_BDTH_MASK 0x3fff
193 #define RTL8366RB_EB_PREIFG_REG 0x02f8
194 #define RTL8366RB_EB_PREIFG_OFFSET 9
195 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
196
197 #define RTL8366RB_BDTH_SW_MAX 1048512
198 #define RTL8366RB_BDTH_UNIT 64
199 #define RTL8366RB_BDTH_REG_DEFAULT 16383
200
201 /* QOS */
202 #define RTL8366RB_QOS_BIT 15
203 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
204 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
205 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
206
207
208 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
209 { 0, 0, 4, "IfInOctets" },
210 { 0, 4, 4, "EtherStatsOctets" },
211 { 0, 8, 2, "EtherStatsUnderSizePkts" },
212 { 0, 10, 2, "EtherFragments" },
213 { 0, 12, 2, "EtherStatsPkts64Octets" },
214 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
215 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
216 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
217 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
218 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
219 { 0, 24, 2, "EtherOversizeStats" },
220 { 0, 26, 2, "EtherStatsJabbers" },
221 { 0, 28, 2, "IfInUcastPkts" },
222 { 0, 30, 2, "EtherStatsMulticastPkts" },
223 { 0, 32, 2, "EtherStatsBroadcastPkts" },
224 { 0, 34, 2, "EtherStatsDropEvents" },
225 { 0, 36, 2, "Dot3StatsFCSErrors" },
226 { 0, 38, 2, "Dot3StatsSymbolErrors" },
227 { 0, 40, 2, "Dot3InPauseFrames" },
228 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
229 { 0, 44, 4, "IfOutOctets" },
230 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
231 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
232 { 0, 52, 2, "Dot3sDeferredTransmissions" },
233 { 0, 54, 2, "Dot3StatsLateCollisions" },
234 { 0, 56, 2, "EtherStatsCollisions" },
235 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
236 { 0, 60, 2, "Dot3OutPauseFrames" },
237 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
238 { 0, 64, 2, "Dot1dTpPortInDiscards" },
239 { 0, 66, 2, "IfOutUcastPkts" },
240 { 0, 68, 2, "IfOutMulticastPkts" },
241 { 0, 70, 2, "IfOutBroadcastPkts" },
242 };
243
244 #define REG_WR(_smi, _reg, _val) \
245 do { \
246 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
247 if (err) \
248 return err; \
249 } while (0)
250
251 #define REG_RMW(_smi, _reg, _mask, _val) \
252 do { \
253 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
254 if (err) \
255 return err; \
256 } while (0)
257
258 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
259 {
260 int timeout = 10;
261 u32 data;
262
263 rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
264 RTL8366RB_CHIP_CTRL_RESET_HW);
265 do {
266 msleep(1);
267 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
268 return -EIO;
269
270 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
271 break;
272 } while (--timeout);
273
274 if (!timeout) {
275 printk("Timeout waiting for the switch to reset\n");
276 return -EIO;
277 }
278
279 return 0;
280 }
281
282 static int rtl8366rb_setup(struct rtl8366_smi *smi)
283 {
284 int err;
285
286 /* set maximum packet length to 1536 bytes */
287 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
288 RTL8366RB_SGCR_MAX_LENGTH_1536);
289
290 /* enable learning for all ports */
291 REG_WR(smi, RTL8366RB_SSCR0, 0);
292
293 /* enable auto ageing for all ports */
294 REG_WR(smi, RTL8366RB_SSCR1, 0);
295
296 /*
297 * discard VLAN tagged packets if the port is not a member of
298 * the VLAN with which the packets is associated.
299 */
300 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
301
302 /* don't drop packets whose DA has not been learned */
303 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
304
305 return 0;
306 }
307
308 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
309 u32 phy_no, u32 page, u32 addr, u32 *data)
310 {
311 u32 reg;
312 int ret;
313
314 if (phy_no > RTL8366RB_PHY_NO_MAX)
315 return -EINVAL;
316
317 if (page > RTL8366RB_PHY_PAGE_MAX)
318 return -EINVAL;
319
320 if (addr > RTL8366RB_PHY_ADDR_MAX)
321 return -EINVAL;
322
323 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
324 RTL8366RB_PHY_CTRL_READ);
325 if (ret)
326 return ret;
327
328 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
329 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
330 (addr & RTL8366RB_PHY_REG_MASK);
331
332 ret = rtl8366_smi_write_reg(smi, reg, 0);
333 if (ret)
334 return ret;
335
336 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
337 if (ret)
338 return ret;
339
340 return 0;
341 }
342
343 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
344 u32 phy_no, u32 page, u32 addr, u32 data)
345 {
346 u32 reg;
347 int ret;
348
349 if (phy_no > RTL8366RB_PHY_NO_MAX)
350 return -EINVAL;
351
352 if (page > RTL8366RB_PHY_PAGE_MAX)
353 return -EINVAL;
354
355 if (addr > RTL8366RB_PHY_ADDR_MAX)
356 return -EINVAL;
357
358 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
359 RTL8366RB_PHY_CTRL_WRITE);
360 if (ret)
361 return ret;
362
363 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
364 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
365 (addr & RTL8366RB_PHY_REG_MASK);
366
367 ret = rtl8366_smi_write_reg(smi, reg, data);
368 if (ret)
369 return ret;
370
371 return 0;
372 }
373
374 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
375 int port, unsigned long long *val)
376 {
377 int i;
378 int err;
379 u32 addr, data;
380 u64 mibvalue;
381
382 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
383 return -EINVAL;
384
385 addr = RTL8366RB_MIB_COUNTER_BASE +
386 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
387 rtl8366rb_mib_counters[counter].offset;
388
389 /*
390 * Writing access counter address first
391 * then ASIC will prepare 64bits counter wait for being retrived
392 */
393 data = 0; /* writing data will be discard by ASIC */
394 err = rtl8366_smi_write_reg(smi, addr, data);
395 if (err)
396 return err;
397
398 /* read MIB control register */
399 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
400 if (err)
401 return err;
402
403 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
404 return -EBUSY;
405
406 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
407 return -EIO;
408
409 mibvalue = 0;
410 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
411 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
412 if (err)
413 return err;
414
415 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
416 }
417
418 *val = mibvalue;
419 return 0;
420 }
421
422 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
423 struct rtl8366_vlan_4k *vlan4k)
424 {
425 u32 data[3];
426 int err;
427 int i;
428
429 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
430
431 if (vid >= RTL8366RB_NUM_VIDS)
432 return -EINVAL;
433
434 /* write VID */
435 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
436 vid & RTL8366RB_VLAN_VID_MASK);
437 if (err)
438 return err;
439
440 /* write table access control word */
441 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
442 RTL8366RB_TABLE_VLAN_READ_CTRL);
443 if (err)
444 return err;
445
446 for (i = 0; i < 3; i++) {
447 err = rtl8366_smi_read_reg(smi,
448 RTL8366RB_VLAN_TABLE_READ_BASE + i,
449 &data[i]);
450 if (err)
451 return err;
452 }
453
454 vlan4k->vid = vid;
455 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
456 RTL8366RB_VLAN_UNTAG_MASK;
457 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
458 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
459
460 return 0;
461 }
462
463 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
464 const struct rtl8366_vlan_4k *vlan4k)
465 {
466 u32 data[3];
467 int err;
468 int i;
469
470 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
471 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
472 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
473 vlan4k->fid > RTL8366RB_FIDMAX)
474 return -EINVAL;
475
476 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
477 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
478 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
479 RTL8366RB_VLAN_UNTAG_SHIFT);
480 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
481
482 for (i = 0; i < 3; i++) {
483 err = rtl8366_smi_write_reg(smi,
484 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
485 data[i]);
486 if (err)
487 return err;
488 }
489
490 /* write table access control word */
491 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
492 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
493
494 return err;
495 }
496
497 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
498 struct rtl8366_vlan_mc *vlanmc)
499 {
500 u32 data[3];
501 int err;
502 int i;
503
504 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
505
506 if (index >= RTL8366RB_NUM_VLANS)
507 return -EINVAL;
508
509 for (i = 0; i < 3; i++) {
510 err = rtl8366_smi_read_reg(smi,
511 RTL8366RB_VLAN_MC_BASE(index) + i,
512 &data[i]);
513 if (err)
514 return err;
515 }
516
517 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
518 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
519 RTL8366RB_VLAN_PRIORITY_MASK;
520 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
521 RTL8366RB_VLAN_UNTAG_MASK;
522 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
523 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
524
525 return 0;
526 }
527
528 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
529 const struct rtl8366_vlan_mc *vlanmc)
530 {
531 u32 data[3];
532 int err;
533 int i;
534
535 if (index >= RTL8366RB_NUM_VLANS ||
536 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
537 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
538 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
539 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
540 vlanmc->fid > RTL8366RB_FIDMAX)
541 return -EINVAL;
542
543 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
544 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
545 RTL8366RB_VLAN_PRIORITY_SHIFT);
546 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
547 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
548 RTL8366RB_VLAN_UNTAG_SHIFT);
549 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
550
551 for (i = 0; i < 3; i++) {
552 err = rtl8366_smi_write_reg(smi,
553 RTL8366RB_VLAN_MC_BASE(index) + i,
554 data[i]);
555 if (err)
556 return err;
557 }
558
559 return 0;
560 }
561
562 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
563 {
564 u32 data;
565 int err;
566
567 if (port >= RTL8366RB_NUM_PORTS)
568 return -EINVAL;
569
570 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
571 &data);
572 if (err)
573 return err;
574
575 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
576 RTL8366RB_PORT_VLAN_CTRL_MASK;
577
578 return 0;
579
580 }
581
582 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
583 {
584 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
585 return -EINVAL;
586
587 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
588 RTL8366RB_PORT_VLAN_CTRL_MASK <<
589 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
590 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
591 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
592 }
593
594 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
595 {
596 unsigned max = RTL8366RB_NUM_VLANS;
597
598 if (smi->vlan4k_enabled)
599 max = RTL8366RB_NUM_VIDS - 1;
600
601 if (vlan == 0 || vlan >= max)
602 return 0;
603
604 return 1;
605 }
606
607 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
608 {
609 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
610 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
611 }
612
613 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
614 {
615 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
616 RTL8366RB_SGCR_EN_VLAN_4KTB,
617 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
618 }
619
620 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
621 {
622 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
623 (enable) ? 0 : (1 << port));
624 }
625
626 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
627 const struct switch_attr *attr,
628 struct switch_val *val)
629 {
630 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
631
632 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
633 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
634 }
635
636 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
637 const struct switch_attr *attr,
638 struct switch_val *val)
639 {
640 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
641 u32 data;
642
643 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
644
645 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
646
647 return 0;
648 }
649
650 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
651 const struct switch_attr *attr,
652 struct switch_val *val)
653 {
654 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
655
656 if (val->value.i >= 6)
657 return -EINVAL;
658
659 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
660 RTL8366RB_LED_BLINKRATE_MASK,
661 val->value.i);
662 }
663
664 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
665 const struct switch_attr *attr,
666 struct switch_val *val)
667 {
668 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
669 u32 data;
670
671 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
672 val->value.i = !data;
673
674 return 0;
675 }
676
677
678 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
679 const struct switch_attr *attr,
680 struct switch_val *val)
681 {
682 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
683 u32 portmask = 0;
684 int err = 0;
685
686 if (!val->value.i)
687 portmask = RTL8366RB_PORT_ALL;
688
689 /* set learning for all ports */
690 REG_WR(smi, RTL8366RB_SSCR0, portmask);
691
692 /* set auto ageing for all ports */
693 REG_WR(smi, RTL8366RB_SSCR1, portmask);
694
695 return 0;
696 }
697
698 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
699 int port,
700 struct switch_port_link *link)
701 {
702 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
703 u32 data = 0;
704 u32 speed;
705
706 if (port >= RTL8366RB_NUM_PORTS)
707 return -EINVAL;
708
709 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
710 &data);
711
712 if (port % 2)
713 data = data >> 8;
714
715 link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
716 if (!link->link)
717 return 0;
718
719 link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
720 link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
721 link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
722 link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
723
724 speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
725 switch (speed) {
726 case 0:
727 link->speed = SWITCH_PORT_SPEED_10;
728 break;
729 case 1:
730 link->speed = SWITCH_PORT_SPEED_100;
731 break;
732 case 2:
733 link->speed = SWITCH_PORT_SPEED_1000;
734 break;
735 default:
736 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
737 break;
738 }
739
740 return 0;
741 }
742
743 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
744 const struct switch_attr *attr,
745 struct switch_val *val)
746 {
747 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
748 u32 data;
749 u32 mask;
750 u32 reg;
751
752 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
753 return -EINVAL;
754
755 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
756 reg = RTL8366RB_LED_BLINKRATE_REG;
757 mask = 0xF << 4;
758 data = val->value.i << 4;
759 } else {
760 reg = RTL8366RB_LED_CTRL_REG;
761 mask = 0xF << (val->port_vlan * 4),
762 data = val->value.i << (val->port_vlan * 4);
763 }
764
765 return rtl8366_smi_rmwr(smi, reg, mask, data);
766 }
767
768 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
769 const struct switch_attr *attr,
770 struct switch_val *val)
771 {
772 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
773 u32 data = 0;
774
775 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
776 return -EINVAL;
777
778 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
779 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
780
781 return 0;
782 }
783
784 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
785 const struct switch_attr *attr,
786 struct switch_val *val)
787 {
788 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
789 u32 mask, data;
790
791 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
792 return -EINVAL;
793
794 mask = 1 << val->port_vlan ;
795 if (val->value.i)
796 data = mask;
797 else
798 data = 0;
799
800 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
801 }
802
803 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
804 const struct switch_attr *attr,
805 struct switch_val *val)
806 {
807 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
808 u32 data;
809
810 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
811 return -EINVAL;
812
813 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
814 if (data & (1 << val->port_vlan))
815 val->value.i = 1;
816 else
817 val->value.i = 0;
818
819 return 0;
820 }
821
822 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
823 const struct switch_attr *attr,
824 struct switch_val *val)
825 {
826 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
827
828 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
829 return -EINVAL;
830
831 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
832 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
833 else
834 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
835
836 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
837 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
838 val->value.i |
839 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
840
841 }
842
843 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
844 const struct switch_attr *attr,
845 struct switch_val *val)
846 {
847 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
848 u32 data;
849
850 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
851 return -EINVAL;
852
853 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
854 data &= RTL8366RB_IB_BDTH_MASK;
855 if (data < RTL8366RB_IB_BDTH_MASK)
856 data += 1;
857
858 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
859
860 return 0;
861 }
862
863 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
864 const struct switch_attr *attr,
865 struct switch_val *val)
866 {
867 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
868
869 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
870 return -EINVAL;
871
872 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
873 RTL8366RB_EB_PREIFG_MASK,
874 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
875
876 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
877 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
878 else
879 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
880
881 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
882 RTL8366RB_EB_BDTH_MASK, val->value.i );
883
884 }
885
886 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
887 const struct switch_attr *attr,
888 struct switch_val *val)
889 {
890 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
891 u32 data;
892
893 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
894 return -EINVAL;
895
896 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
897 data &= RTL8366RB_EB_BDTH_MASK;
898 if (data < RTL8366RB_EB_BDTH_MASK)
899 data += 1;
900
901 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
902
903 return 0;
904 }
905
906 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
907 const struct switch_attr *attr,
908 struct switch_val *val)
909 {
910 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
911 u32 data;
912
913 if (val->value.i)
914 data = RTL8366RB_QOS_MASK;
915 else
916 data = 0;
917
918 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
919 }
920
921 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
922 const struct switch_attr *attr,
923 struct switch_val *val)
924 {
925 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
926 u32 data;
927
928 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
929 if (data & RTL8366RB_QOS_MASK)
930 val->value.i = 1;
931 else
932 val->value.i = 0;
933
934 return 0;
935 }
936
937 static int rtl8366rb_sw_set_mirror_rx_enable(struct switch_dev *dev,
938 const struct switch_attr *attr,
939 struct switch_val *val)
940 {
941 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
942 u32 data;
943
944 if (val->value.i)
945 data = RTL8366RB_PMCR_MIRROR_RX;
946 else
947 data = 0;
948
949 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_RX, data);
950 }
951
952 static int rtl8366rb_sw_get_mirror_rx_enable(struct switch_dev *dev,
953 const struct switch_attr *attr,
954 struct switch_val *val)
955 {
956 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
957 u32 data;
958
959 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
960 if (data & RTL8366RB_PMCR_MIRROR_RX)
961 val->value.i = 1;
962 else
963 val->value.i = 0;
964
965 return 0;
966 }
967
968 static int rtl8366rb_sw_set_mirror_tx_enable(struct switch_dev *dev,
969 const struct switch_attr *attr,
970 struct switch_val *val)
971 {
972 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
973 u32 data;
974
975 if (val->value.i)
976 data = RTL8366RB_PMCR_MIRROR_TX;
977 else
978 data = 0;
979
980 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_TX, data);
981 }
982
983 static int rtl8366rb_sw_get_mirror_tx_enable(struct switch_dev *dev,
984 const struct switch_attr *attr,
985 struct switch_val *val)
986 {
987 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
988 u32 data;
989
990 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
991 if (data & RTL8366RB_PMCR_MIRROR_TX)
992 val->value.i = 1;
993 else
994 val->value.i = 0;
995
996 return 0;
997 }
998
999 static int rtl8366rb_sw_set_monitor_isolation_enable(struct switch_dev *dev,
1000 const struct switch_attr *attr,
1001 struct switch_val *val)
1002 {
1003 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1004 u32 data;
1005
1006 if (val->value.i)
1007 data = RTL8366RB_PMCR_MIRROR_ISO;
1008 else
1009 data = 0;
1010
1011 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_ISO, data);
1012 }
1013
1014 static int rtl8366rb_sw_get_monitor_isolation_enable(struct switch_dev *dev,
1015 const struct switch_attr *attr,
1016 struct switch_val *val)
1017 {
1018 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1019 u32 data;
1020
1021 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1022 if (data & RTL8366RB_PMCR_MIRROR_ISO)
1023 val->value.i = 1;
1024 else
1025 val->value.i = 0;
1026
1027 return 0;
1028 }
1029
1030 static int rtl8366rb_sw_set_mirror_pause_frames_enable(struct switch_dev *dev,
1031 const struct switch_attr *attr,
1032 struct switch_val *val)
1033 {
1034 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1035 u32 data;
1036
1037 if (val->value.i)
1038 data = RTL8366RB_PMCR_MIRROR_SPC;
1039 else
1040 data = 0;
1041
1042 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_SPC, data);
1043 }
1044
1045 static int rtl8366rb_sw_get_mirror_pause_frames_enable(struct switch_dev *dev,
1046 const struct switch_attr *attr,
1047 struct switch_val *val)
1048 {
1049 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1050 u32 data;
1051
1052 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1053 if (data & RTL8366RB_PMCR_MIRROR_SPC)
1054 val->value.i = 1;
1055 else
1056 val->value.i = 0;
1057
1058 return 0;
1059 }
1060
1061 static int rtl8366rb_sw_set_mirror_monitor_port(struct switch_dev *dev,
1062 const struct switch_attr *attr,
1063 struct switch_val *val)
1064 {
1065 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1066 u32 data;
1067
1068 data = RTL8366RB_PMCR_MONITOR_PORT(val->value.i);
1069
1070 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MONITOR_PORT_MASK, data);
1071 }
1072
1073 static int rtl8366rb_sw_get_mirror_monitor_port(struct switch_dev *dev,
1074 const struct switch_attr *attr,
1075 struct switch_val *val)
1076 {
1077 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1078 u32 data;
1079
1080 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1081 val->value.i = (data & RTL8366RB_PMCR_MONITOR_PORT_MASK) >> 4;
1082
1083 return 0;
1084 }
1085
1086 static int rtl8366rb_sw_set_mirror_source_port(struct switch_dev *dev,
1087 const struct switch_attr *attr,
1088 struct switch_val *val)
1089 {
1090 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1091 u32 data;
1092
1093 data = RTL8366RB_PMCR_SOURCE_PORT(val->value.i);
1094
1095 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_SOURCE_PORT_MASK, data);
1096 }
1097
1098 static int rtl8366rb_sw_get_mirror_source_port(struct switch_dev *dev,
1099 const struct switch_attr *attr,
1100 struct switch_val *val)
1101 {
1102 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1103 u32 data;
1104
1105 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1106 val->value.i = data & RTL8366RB_PMCR_SOURCE_PORT_MASK;
1107
1108 return 0;
1109 }
1110
1111 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1112 const struct switch_attr *attr,
1113 struct switch_val *val)
1114 {
1115 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1116
1117 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1118 return -EINVAL;
1119
1120 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
1121 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
1122 }
1123
1124 static struct switch_attr rtl8366rb_globals[] = {
1125 {
1126 .type = SWITCH_TYPE_INT,
1127 .name = "enable_learning",
1128 .description = "Enable learning, enable aging",
1129 .set = rtl8366rb_sw_set_learning_enable,
1130 .get = rtl8366rb_sw_get_learning_enable,
1131 .max = 1
1132 }, {
1133 .type = SWITCH_TYPE_INT,
1134 .name = "enable_vlan",
1135 .description = "Enable VLAN mode",
1136 .set = rtl8366_sw_set_vlan_enable,
1137 .get = rtl8366_sw_get_vlan_enable,
1138 .max = 1,
1139 .ofs = 1
1140 }, {
1141 .type = SWITCH_TYPE_INT,
1142 .name = "enable_vlan4k",
1143 .description = "Enable VLAN 4K mode",
1144 .set = rtl8366_sw_set_vlan_enable,
1145 .get = rtl8366_sw_get_vlan_enable,
1146 .max = 1,
1147 .ofs = 2
1148 }, {
1149 .type = SWITCH_TYPE_NOVAL,
1150 .name = "reset_mibs",
1151 .description = "Reset all MIB counters",
1152 .set = rtl8366rb_sw_reset_mibs,
1153 }, {
1154 .type = SWITCH_TYPE_INT,
1155 .name = "blinkrate",
1156 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1157 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1158 .set = rtl8366rb_sw_set_blinkrate,
1159 .get = rtl8366rb_sw_get_blinkrate,
1160 .max = 5
1161 }, {
1162 .type = SWITCH_TYPE_INT,
1163 .name = "enable_qos",
1164 .description = "Enable QOS",
1165 .set = rtl8366rb_sw_set_qos_enable,
1166 .get = rtl8366rb_sw_get_qos_enable,
1167 .max = 1
1168 }, {
1169 .type = SWITCH_TYPE_INT,
1170 .name = "enable_mirror_rx",
1171 .description = "Enable mirroring of RX packets",
1172 .set = rtl8366rb_sw_set_mirror_rx_enable,
1173 .get = rtl8366rb_sw_get_mirror_rx_enable,
1174 .max = 1
1175 }, {
1176 .type = SWITCH_TYPE_INT,
1177 .name = "enable_mirror_tx",
1178 .description = "Enable mirroring of TX packets",
1179 .set = rtl8366rb_sw_set_mirror_tx_enable,
1180 .get = rtl8366rb_sw_get_mirror_tx_enable,
1181 .max = 1
1182 }, {
1183 .type = SWITCH_TYPE_INT,
1184 .name = "enable_monitor_isolation",
1185 .description = "Enable isolation of monitor port (TX packets will be dropped)",
1186 .set = rtl8366rb_sw_set_monitor_isolation_enable,
1187 .get = rtl8366rb_sw_get_monitor_isolation_enable,
1188 .max = 1
1189 }, {
1190 .type = SWITCH_TYPE_INT,
1191 .name = "enable_mirror_pause_frames",
1192 .description = "Enable mirroring of RX pause frames",
1193 .set = rtl8366rb_sw_set_mirror_pause_frames_enable,
1194 .get = rtl8366rb_sw_get_mirror_pause_frames_enable,
1195 .max = 1
1196 }, {
1197 .type = SWITCH_TYPE_INT,
1198 .name = "mirror_monitor_port",
1199 .description = "Mirror monitor port",
1200 .set = rtl8366rb_sw_set_mirror_monitor_port,
1201 .get = rtl8366rb_sw_get_mirror_monitor_port,
1202 .max = 5
1203 }, {
1204 .type = SWITCH_TYPE_INT,
1205 .name = "mirror_source_port",
1206 .description = "Mirror source port",
1207 .set = rtl8366rb_sw_set_mirror_source_port,
1208 .get = rtl8366rb_sw_get_mirror_source_port,
1209 .max = 5
1210 },
1211 };
1212
1213 static struct switch_attr rtl8366rb_port[] = {
1214 {
1215 .type = SWITCH_TYPE_NOVAL,
1216 .name = "reset_mib",
1217 .description = "Reset single port MIB counters",
1218 .set = rtl8366rb_sw_reset_port_mibs,
1219 }, {
1220 .type = SWITCH_TYPE_STRING,
1221 .name = "mib",
1222 .description = "Get MIB counters for port",
1223 .max = 33,
1224 .set = NULL,
1225 .get = rtl8366_sw_get_port_mib,
1226 }, {
1227 .type = SWITCH_TYPE_INT,
1228 .name = "led",
1229 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1230 .max = 15,
1231 .set = rtl8366rb_sw_set_port_led,
1232 .get = rtl8366rb_sw_get_port_led,
1233 }, {
1234 .type = SWITCH_TYPE_INT,
1235 .name = "disable",
1236 .description = "Get/Set port state (enabled or disabled)",
1237 .max = 1,
1238 .set = rtl8366rb_sw_set_port_disable,
1239 .get = rtl8366rb_sw_get_port_disable,
1240 }, {
1241 .type = SWITCH_TYPE_INT,
1242 .name = "rate_in",
1243 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1244 .max = RTL8366RB_BDTH_SW_MAX,
1245 .set = rtl8366rb_sw_set_port_rate_in,
1246 .get = rtl8366rb_sw_get_port_rate_in,
1247 }, {
1248 .type = SWITCH_TYPE_INT,
1249 .name = "rate_out",
1250 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1251 .max = RTL8366RB_BDTH_SW_MAX,
1252 .set = rtl8366rb_sw_set_port_rate_out,
1253 .get = rtl8366rb_sw_get_port_rate_out,
1254 },
1255 };
1256
1257 static struct switch_attr rtl8366rb_vlan[] = {
1258 {
1259 .type = SWITCH_TYPE_STRING,
1260 .name = "info",
1261 .description = "Get vlan information",
1262 .max = 1,
1263 .set = NULL,
1264 .get = rtl8366_sw_get_vlan_info,
1265 }, {
1266 .type = SWITCH_TYPE_INT,
1267 .name = "fid",
1268 .description = "Get/Set vlan FID",
1269 .max = RTL8366RB_FIDMAX,
1270 .set = rtl8366_sw_set_vlan_fid,
1271 .get = rtl8366_sw_get_vlan_fid,
1272 },
1273 };
1274
1275 static const struct switch_dev_ops rtl8366_ops = {
1276 .attr_global = {
1277 .attr = rtl8366rb_globals,
1278 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1279 },
1280 .attr_port = {
1281 .attr = rtl8366rb_port,
1282 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1283 },
1284 .attr_vlan = {
1285 .attr = rtl8366rb_vlan,
1286 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1287 },
1288
1289 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1290 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1291 .get_port_pvid = rtl8366_sw_get_port_pvid,
1292 .set_port_pvid = rtl8366_sw_set_port_pvid,
1293 .reset_switch = rtl8366_sw_reset_switch,
1294 .get_port_link = rtl8366rb_sw_get_port_link,
1295 };
1296
1297 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1298 {
1299 struct switch_dev *dev = &smi->sw_dev;
1300 int err;
1301
1302 dev->name = "RTL8366RB";
1303 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1304 dev->ports = RTL8366RB_NUM_PORTS;
1305 dev->vlans = RTL8366RB_NUM_VIDS;
1306 dev->ops = &rtl8366_ops;
1307 dev->alias = dev_name(smi->parent);
1308
1309 err = register_switch(dev, NULL);
1310 if (err)
1311 dev_err(smi->parent, "switch registration failed\n");
1312
1313 return err;
1314 }
1315
1316 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1317 {
1318 unregister_switch(&smi->sw_dev);
1319 }
1320
1321 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1322 {
1323 struct rtl8366_smi *smi = bus->priv;
1324 u32 val = 0;
1325 int err;
1326
1327 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1328 if (err)
1329 return 0xffff;
1330
1331 return val;
1332 }
1333
1334 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1335 {
1336 struct rtl8366_smi *smi = bus->priv;
1337 u32 t;
1338 int err;
1339
1340 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1341 /* flush write */
1342 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1343
1344 return err;
1345 }
1346
1347 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1348 {
1349 u32 chip_id = 0;
1350 u32 chip_ver = 0;
1351 int ret;
1352
1353 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1354 if (ret) {
1355 dev_err(smi->parent, "unable to read chip id\n");
1356 return ret;
1357 }
1358
1359 switch (chip_id) {
1360 case RTL8366RB_CHIP_ID_8366:
1361 break;
1362 default:
1363 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1364 return -ENODEV;
1365 }
1366
1367 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1368 &chip_ver);
1369 if (ret) {
1370 dev_err(smi->parent, "unable to read chip version\n");
1371 return ret;
1372 }
1373
1374 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1375 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1376
1377 return 0;
1378 }
1379
1380 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1381 .detect = rtl8366rb_detect,
1382 .reset_chip = rtl8366rb_reset_chip,
1383 .setup = rtl8366rb_setup,
1384
1385 .mii_read = rtl8366rb_mii_read,
1386 .mii_write = rtl8366rb_mii_write,
1387
1388 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1389 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1390 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1391 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1392 .get_mc_index = rtl8366rb_get_mc_index,
1393 .set_mc_index = rtl8366rb_set_mc_index,
1394 .get_mib_counter = rtl8366rb_get_mib_counter,
1395 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1396 .enable_vlan = rtl8366rb_enable_vlan,
1397 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1398 .enable_port = rtl8366rb_enable_port,
1399 };
1400
1401 static int rtl8366rb_probe(struct platform_device *pdev)
1402 {
1403 static int rtl8366_smi_version_printed;
1404 struct rtl8366_smi *smi;
1405 int err;
1406
1407 if (!rtl8366_smi_version_printed++)
1408 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1409 " version " RTL8366RB_DRIVER_VER"\n");
1410
1411 smi = rtl8366_smi_probe(pdev);
1412 if (!smi)
1413 return -ENODEV;
1414
1415 smi->clk_delay = 10;
1416 smi->cmd_read = 0xa9;
1417 smi->cmd_write = 0xa8;
1418 smi->ops = &rtl8366rb_smi_ops;
1419 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1420 smi->num_ports = RTL8366RB_NUM_PORTS;
1421 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1422 smi->mib_counters = rtl8366rb_mib_counters;
1423 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1424
1425 err = rtl8366_smi_init(smi);
1426 if (err)
1427 goto err_free_smi;
1428
1429 platform_set_drvdata(pdev, smi);
1430
1431 err = rtl8366rb_switch_init(smi);
1432 if (err)
1433 goto err_clear_drvdata;
1434
1435 return 0;
1436
1437 err_clear_drvdata:
1438 platform_set_drvdata(pdev, NULL);
1439 rtl8366_smi_cleanup(smi);
1440 err_free_smi:
1441 kfree(smi);
1442 return err;
1443 }
1444
1445 static int rtl8366rb_remove(struct platform_device *pdev)
1446 {
1447 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1448
1449 if (smi) {
1450 rtl8366rb_switch_cleanup(smi);
1451 platform_set_drvdata(pdev, NULL);
1452 rtl8366_smi_cleanup(smi);
1453 kfree(smi);
1454 }
1455
1456 return 0;
1457 }
1458
1459 #ifdef CONFIG_OF
1460 static const struct of_device_id rtl8366rb_match[] = {
1461 { .compatible = "realtek,rtl8366rb" },
1462 {},
1463 };
1464 MODULE_DEVICE_TABLE(of, rtl8366rb_match);
1465 #endif
1466
1467 static struct platform_driver rtl8366rb_driver = {
1468 .driver = {
1469 .name = RTL8366RB_DRIVER_NAME,
1470 .owner = THIS_MODULE,
1471 .of_match_table = of_match_ptr(rtl8366rb_match),
1472 },
1473 .probe = rtl8366rb_probe,
1474 .remove = rtl8366rb_remove,
1475 };
1476
1477 static int __init rtl8366rb_module_init(void)
1478 {
1479 return platform_driver_register(&rtl8366rb_driver);
1480 }
1481 module_init(rtl8366rb_module_init);
1482
1483 static void __exit rtl8366rb_module_exit(void)
1484 {
1485 platform_driver_unregister(&rtl8366rb_driver);
1486 }
1487 module_exit(rtl8366rb_module_exit);
1488
1489 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1490 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1491 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1492 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1493 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1494 MODULE_AUTHOR("Colin Leitner <colin.leitner@googlemail.com>");
1495 MODULE_LICENSE("GPL v2");
1496 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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