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[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.2"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29 #define RTL8366RB_PHY_WAN 4
30
31 /* Switch Global Configuration register */
32 #define RTL8366RB_SGCR 0x0000
33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
34 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
39 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
40 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
41 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
42
43 /* Port Enable Control register */
44 #define RTL8366RB_PECR 0x0001
45
46 /* Switch Security Control registers */
47 #define RTL8366RB_SSCR0 0x0002
48 #define RTL8366RB_SSCR1 0x0003
49 #define RTL8366RB_SSCR2 0x0004
50 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
51
52 #define RTL8366RB_RESET_CTRL_REG 0x0100
53 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
54 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
55
56 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
57 #define RTL8366RB_CHIP_VERSION_MASK 0xf
58 #define RTL8366RB_CHIP_ID_REG 0x0509
59 #define RTL8366RB_CHIP_ID_8366 0x5937
60
61 /* PHY registers control */
62 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
63 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
64
65 #define RTL8366RB_PHY_CTRL_READ 1
66 #define RTL8366RB_PHY_CTRL_WRITE 0
67
68 #define RTL8366RB_PHY_REG_MASK 0x1f
69 #define RTL8366RB_PHY_PAGE_OFFSET 5
70 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
71 #define RTL8366RB_PHY_NO_OFFSET 9
72 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
73
74 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
75
76 /* LED control registers */
77 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
78 #define RTL8366RB_LED_BLINKRATE_BIT 0
79 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
80
81 #define RTL8366RB_LED_CTRL_REG 0x0431
82 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
83 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
84
85 #define RTL8366RB_MIB_COUNT 33
86 #define RTL8366RB_GLOBAL_MIB_COUNT 1
87 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
88 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
89 #define RTL8366RB_MIB_CTRL_REG 0x13F0
90 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
91 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
92 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
93 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
94 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
95
96 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
97 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
98 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
99 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
100 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
101
102
103 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
104 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
105
106
107 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
108 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
109 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
110
111 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
112
113
114 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
115 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
116 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
117 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
118 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
119 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
120 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
121
122
123 #define RTL8366RB_PORT_NUM_CPU 5
124 #define RTL8366RB_NUM_PORTS 6
125 #define RTL8366RB_NUM_VLANS 16
126 #define RTL8366RB_NUM_LEDGROUPS 4
127 #define RTL8366RB_NUM_VIDS 4096
128 #define RTL8366RB_PRIORITYMAX 7
129 #define RTL8366RB_FIDMAX 7
130
131
132 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
133 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
134 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
135 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
136 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
137
138 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
139
140 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
141 RTL8366RB_PORT_2 | \
142 RTL8366RB_PORT_3 | \
143 RTL8366RB_PORT_4 | \
144 RTL8366RB_PORT_5 | \
145 RTL8366RB_PORT_CPU)
146
147 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
148 RTL8366RB_PORT_2 | \
149 RTL8366RB_PORT_3 | \
150 RTL8366RB_PORT_4 | \
151 RTL8366RB_PORT_5)
152
153 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
154 RTL8366RB_PORT_2 | \
155 RTL8366RB_PORT_3 | \
156 RTL8366RB_PORT_4)
157
158 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
159
160 #define RTL8366RB_VLAN_VID_MASK 0xfff
161 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
162 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
163 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
164 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
165 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
166 #define RTL8366RB_VLAN_FID_MASK 0x7
167
168
169 /* Port ingress bandwidth control */
170 #define RTL8366RB_IB_BASE 0x0200
171 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
172 #define RTL8366RB_IB_BDTH_MASK 0x3fff
173 #define RTL8366RB_IB_PREIFG_OFFSET 14
174 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
175
176 /* Port egress bandwidth control */
177 #define RTL8366RB_EB_BASE 0x02d1
178 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
179 #define RTL8366RB_EB_BDTH_MASK 0x3fff
180 #define RTL8366RB_EB_PREIFG_REG 0x02f8
181 #define RTL8366RB_EB_PREIFG_OFFSET 9
182 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
183
184 #define RTL8366RB_BDTH_SW_MAX 1048512
185 #define RTL8366RB_BDTH_BASE 64
186 #define RTL8366RB_BDTH_REG_DEFAULT 16383
187
188 /* QOS */
189 #define RTL8366RB_QOS_BIT 15
190 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
191 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
192 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
193
194
195 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
196 { 0, 0, 4, "IfInOctets" },
197 { 0, 4, 4, "EtherStatsOctets" },
198 { 0, 8, 2, "EtherStatsUnderSizePkts" },
199 { 0, 10, 2, "EtherFragments" },
200 { 0, 12, 2, "EtherStatsPkts64Octets" },
201 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
202 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
203 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
204 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
205 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
206 { 0, 24, 2, "EtherOversizeStats" },
207 { 0, 26, 2, "EtherStatsJabbers" },
208 { 0, 28, 2, "IfInUcastPkts" },
209 { 0, 30, 2, "EtherStatsMulticastPkts" },
210 { 0, 32, 2, "EtherStatsBroadcastPkts" },
211 { 0, 34, 2, "EtherStatsDropEvents" },
212 { 0, 36, 2, "Dot3StatsFCSErrors" },
213 { 0, 38, 2, "Dot3StatsSymbolErrors" },
214 { 0, 40, 2, "Dot3InPauseFrames" },
215 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
216 { 0, 44, 4, "IfOutOctets" },
217 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
218 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
219 { 0, 52, 2, "Dot3sDeferredTransmissions" },
220 { 0, 54, 2, "Dot3StatsLateCollisions" },
221 { 0, 56, 2, "EtherStatsCollisions" },
222 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
223 { 0, 60, 2, "Dot3OutPauseFrames" },
224 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
225 { 0, 64, 2, "Dot1dTpPortInDiscards" },
226 { 0, 66, 2, "IfOutUcastPkts" },
227 { 0, 68, 2, "IfOutMulticastPkts" },
228 { 0, 70, 2, "IfOutBroadcastPkts" },
229 };
230
231 #define REG_WR(_smi, _reg, _val) \
232 do { \
233 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
234 if (err) \
235 return err; \
236 } while (0)
237
238 #define REG_RMW(_smi, _reg, _mask, _val) \
239 do { \
240 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
241 if (err) \
242 return err; \
243 } while (0)
244
245 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
246 {
247 int timeout = 10;
248 u32 data;
249
250 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
251 RTL8366RB_CHIP_CTRL_RESET_HW);
252 do {
253 msleep(1);
254 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
255 return -EIO;
256
257 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
258 break;
259 } while (--timeout);
260
261 if (!timeout) {
262 printk("Timeout waiting for the switch to reset\n");
263 return -EIO;
264 }
265
266 return 0;
267 }
268
269 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
270 {
271 int err;
272
273 /* set maximum packet length to 1536 bytes */
274 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
275 RTL8366RB_SGCR_MAX_LENGTH_1536);
276
277 /* enable all ports */
278 REG_WR(smi, RTL8366RB_PECR, 0);
279
280 /* enable learning for all ports */
281 REG_WR(smi, RTL8366RB_SSCR0, 0);
282
283 /* enable auto ageing for all ports */
284 REG_WR(smi, RTL8366RB_SSCR1, 0);
285
286 /*
287 * discard VLAN tagged packets if the port is not a member of
288 * the VLAN with which the packets is associated.
289 */
290 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
291
292 /* don't drop packets whose DA has not been learned */
293 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
294
295 return 0;
296 }
297
298 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
299 u32 phy_no, u32 page, u32 addr, u32 *data)
300 {
301 u32 reg;
302 int ret;
303
304 if (phy_no > RTL8366RB_PHY_NO_MAX)
305 return -EINVAL;
306
307 if (page > RTL8366RB_PHY_PAGE_MAX)
308 return -EINVAL;
309
310 if (addr > RTL8366RB_PHY_ADDR_MAX)
311 return -EINVAL;
312
313 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
314 RTL8366RB_PHY_CTRL_READ);
315 if (ret)
316 return ret;
317
318 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
319 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
320 (addr & RTL8366RB_PHY_REG_MASK);
321
322 ret = rtl8366_smi_write_reg(smi, reg, 0);
323 if (ret)
324 return ret;
325
326 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
327 if (ret)
328 return ret;
329
330 return 0;
331 }
332
333 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
334 u32 phy_no, u32 page, u32 addr, u32 data)
335 {
336 u32 reg;
337 int ret;
338
339 if (phy_no > RTL8366RB_PHY_NO_MAX)
340 return -EINVAL;
341
342 if (page > RTL8366RB_PHY_PAGE_MAX)
343 return -EINVAL;
344
345 if (addr > RTL8366RB_PHY_ADDR_MAX)
346 return -EINVAL;
347
348 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
349 RTL8366RB_PHY_CTRL_WRITE);
350 if (ret)
351 return ret;
352
353 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
354 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
355 (addr & RTL8366RB_PHY_REG_MASK);
356
357 ret = rtl8366_smi_write_reg(smi, reg, data);
358 if (ret)
359 return ret;
360
361 return 0;
362 }
363
364 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
365 int port, unsigned long long *val)
366 {
367 int i;
368 int err;
369 u32 addr, data;
370 u64 mibvalue;
371
372 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
373 return -EINVAL;
374
375 addr = RTL8366RB_MIB_COUNTER_BASE +
376 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
377 rtl8366rb_mib_counters[counter].offset;
378
379 /*
380 * Writing access counter address first
381 * then ASIC will prepare 64bits counter wait for being retrived
382 */
383 data = 0; /* writing data will be discard by ASIC */
384 err = rtl8366_smi_write_reg(smi, addr, data);
385 if (err)
386 return err;
387
388 /* read MIB control register */
389 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
390 if (err)
391 return err;
392
393 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
394 return -EBUSY;
395
396 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
397 return -EIO;
398
399 mibvalue = 0;
400 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
401 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
402 if (err)
403 return err;
404
405 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
406 }
407
408 *val = mibvalue;
409 return 0;
410 }
411
412 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
413 struct rtl8366_vlan_4k *vlan4k)
414 {
415 u32 data[3];
416 int err;
417 int i;
418
419 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
420
421 if (vid >= RTL8366RB_NUM_VIDS)
422 return -EINVAL;
423
424 /* write VID */
425 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
426 vid & RTL8366RB_VLAN_VID_MASK);
427 if (err)
428 return err;
429
430 /* write table access control word */
431 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
432 RTL8366RB_TABLE_VLAN_READ_CTRL);
433 if (err)
434 return err;
435
436 for (i = 0; i < 3; i++) {
437 err = rtl8366_smi_read_reg(smi,
438 RTL8366RB_VLAN_TABLE_READ_BASE + i,
439 &data[i]);
440 if (err)
441 return err;
442 }
443
444 vlan4k->vid = vid;
445 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
446 RTL8366RB_VLAN_UNTAG_MASK;
447 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
448 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
449
450 return 0;
451 }
452
453 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
454 const struct rtl8366_vlan_4k *vlan4k)
455 {
456 u32 data[3];
457 int err;
458 int i;
459
460 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
461 vlan4k->member > RTL8366RB_PORT_ALL ||
462 vlan4k->untag > RTL8366RB_PORT_ALL ||
463 vlan4k->fid > RTL8366RB_FIDMAX)
464 return -EINVAL;
465
466 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
467 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
468 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
469 RTL8366RB_VLAN_UNTAG_SHIFT);
470 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
471
472 for (i = 0; i < 3; i++) {
473 err = rtl8366_smi_write_reg(smi,
474 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
475 data[i]);
476 if (err)
477 return err;
478 }
479
480 /* write table access control word */
481 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
482 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
483
484 return err;
485 }
486
487 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
488 struct rtl8366_vlan_mc *vlanmc)
489 {
490 u32 data[3];
491 int err;
492 int i;
493
494 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
495
496 if (index >= RTL8366RB_NUM_VLANS)
497 return -EINVAL;
498
499 for (i = 0; i < 3; i++) {
500 err = rtl8366_smi_read_reg(smi,
501 RTL8366RB_VLAN_MC_BASE(index) + i,
502 &data[i]);
503 if (err)
504 return err;
505 }
506
507 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
508 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
509 RTL8366RB_VLAN_PRIORITY_MASK;
510 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
511 RTL8366RB_VLAN_UNTAG_MASK;
512 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
513 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
514
515 return 0;
516 }
517
518 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
519 const struct rtl8366_vlan_mc *vlanmc)
520 {
521 u32 data[3];
522 int err;
523 int i;
524
525 if (index >= RTL8366RB_NUM_VLANS ||
526 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
527 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
528 vlanmc->member > RTL8366RB_PORT_ALL ||
529 vlanmc->untag > RTL8366RB_PORT_ALL ||
530 vlanmc->fid > RTL8366RB_FIDMAX)
531 return -EINVAL;
532
533 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
534 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
535 RTL8366RB_VLAN_PRIORITY_SHIFT);
536 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
537 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
538 RTL8366RB_VLAN_UNTAG_SHIFT);
539 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
540
541 for (i = 0; i < 3; i++) {
542 err = rtl8366_smi_write_reg(smi,
543 RTL8366RB_VLAN_MC_BASE(index) + i,
544 data[i]);
545 if (err)
546 return err;
547 }
548
549 return 0;
550 }
551
552 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
553 {
554 u32 data;
555 int err;
556
557 if (port >= RTL8366RB_NUM_PORTS)
558 return -EINVAL;
559
560 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
561 &data);
562 if (err)
563 return err;
564
565 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
566 RTL8366RB_PORT_VLAN_CTRL_MASK;
567
568 return 0;
569
570 }
571
572 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
573 {
574 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
575 return -EINVAL;
576
577 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
578 RTL8366RB_PORT_VLAN_CTRL_MASK <<
579 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
580 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
581 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
582 }
583
584 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
585 {
586 unsigned max = RTL8366RB_NUM_VLANS;
587
588 if (smi->vlan4k_enabled)
589 max = RTL8366RB_NUM_VIDS - 1;
590
591 if (vlan == 0 || vlan >= max)
592 return 0;
593
594 return 1;
595 }
596
597 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
598 {
599 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
600 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
601 }
602
603 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
604 {
605 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
606 RTL8366RB_SGCR_EN_VLAN_4KTB,
607 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
608 }
609
610 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
611 const struct switch_attr *attr,
612 struct switch_val *val)
613 {
614 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
615
616 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
617 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
618 }
619
620 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
621 const struct switch_attr *attr,
622 struct switch_val *val)
623 {
624 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
625 u32 data;
626
627 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
628
629 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
630
631 return 0;
632 }
633
634 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
635 const struct switch_attr *attr,
636 struct switch_val *val)
637 {
638 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
639
640 if (val->value.i >= 6)
641 return -EINVAL;
642
643 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
644 RTL8366RB_LED_BLINKRATE_MASK,
645 val->value.i);
646 }
647
648 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
649 const struct switch_attr *attr,
650 struct switch_val *val)
651 {
652 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
653 u32 data;
654
655 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
656 val->value.i = !data;
657
658 return 0;
659 }
660
661
662 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
663 const struct switch_attr *attr,
664 struct switch_val *val)
665 {
666 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
667 u32 portmask = 0;
668 int err = 0;
669
670 if (!val->value.i)
671 portmask = RTL8366RB_PORT_ALL;
672
673 /* set learning for all ports */
674 REG_WR(smi, RTL8366RB_SSCR0, portmask);
675
676 /* set auto ageing for all ports */
677 REG_WR(smi, RTL8366RB_SSCR1, portmask);
678
679 return 0;
680 }
681
682
683 static const char *rtl8366rb_speed_str(unsigned speed)
684 {
685 switch (speed) {
686 case 0:
687 return "10baseT";
688 case 1:
689 return "100baseT";
690 case 2:
691 return "1000baseT";
692 }
693
694 return "unknown";
695 }
696
697 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
698 const struct switch_attr *attr,
699 struct switch_val *val)
700 {
701 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
702 u32 len = 0, data = 0;
703
704 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
705 return -EINVAL;
706
707 memset(smi->buf, '\0', sizeof(smi->buf));
708 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
709 (val->port_vlan / 2), &data);
710
711 if (val->port_vlan % 2)
712 data = data >> 8;
713
714 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
715 len = snprintf(smi->buf, sizeof(smi->buf),
716 "port:%d link:up speed:%s %s-duplex %s%s%s",
717 val->port_vlan,
718 rtl8366rb_speed_str(data &
719 RTL8366RB_PORT_STATUS_SPEED_MASK),
720 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
721 "full" : "half",
722 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
723 "tx-pause ": "",
724 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
725 "rx-pause " : "",
726 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
727 "nway ": "");
728 } else {
729 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
730 val->port_vlan);
731 }
732
733 val->value.s = smi->buf;
734 val->len = len;
735
736 return 0;
737 }
738
739 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
740 const struct switch_attr *attr,
741 struct switch_val *val)
742 {
743 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
744 u32 data;
745 u32 mask;
746 u32 reg;
747
748 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
749 return -EINVAL;
750
751 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
752 reg = RTL8366RB_LED_BLINKRATE_REG;
753 mask = 0xF << 4;
754 data = val->value.i << 4;
755 } else {
756 reg = RTL8366RB_LED_CTRL_REG;
757 mask = 0xF << (val->port_vlan * 4),
758 data = val->value.i << (val->port_vlan * 4);
759 }
760
761 return rtl8366_smi_rmwr(smi, reg, mask, data);
762 }
763
764 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
765 const struct switch_attr *attr,
766 struct switch_val *val)
767 {
768 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
769 u32 data = 0;
770
771 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
772 return -EINVAL;
773
774 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
775 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
776
777 return 0;
778 }
779
780 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
781 const struct switch_attr *attr,
782 struct switch_val *val)
783 {
784 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
785 u32 mask, data;
786
787 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
788 return -EINVAL;
789
790 mask = 1 << val->port_vlan ;
791 if (val->value.i)
792 data = mask;
793 else
794 data = 0;
795
796 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
797 }
798
799 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
800 const struct switch_attr *attr,
801 struct switch_val *val)
802 {
803 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
804 u32 data;
805
806 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
807 return -EINVAL;
808
809 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
810 if (data & (1 << val->port_vlan))
811 val->value.i = 1;
812 else
813 val->value.i = 0;
814
815 return 0;
816 }
817
818 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
819 const struct switch_attr *attr,
820 struct switch_val *val)
821 {
822 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
823
824 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
825 return -EINVAL;
826
827 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
828 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_BASE;
829 else
830 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
831
832 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
833 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
834 val->value.i |
835 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
836
837 }
838
839 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
840 const struct switch_attr *attr,
841 struct switch_val *val)
842 {
843 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
844 u32 data;
845
846 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
847 return -EINVAL;
848
849 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
850 data &= RTL8366RB_IB_BDTH_MASK;
851 if (data < RTL8366RB_IB_BDTH_MASK)
852 data += 1;
853
854 val->value.i = (int)data * RTL8366RB_BDTH_BASE;
855
856 return 0;
857 }
858
859 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
860 const struct switch_attr *attr,
861 struct switch_val *val)
862 {
863 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
864
865 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
866 return -EINVAL;
867
868 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
869 RTL8366RB_EB_PREIFG_MASK,
870 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
871
872 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
873 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_BASE;
874 else
875 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
876
877 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
878 RTL8366RB_EB_BDTH_MASK, val->value.i );
879
880 }
881
882 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
883 const struct switch_attr *attr,
884 struct switch_val *val)
885 {
886 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
887 u32 data;
888
889 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
890 return -EINVAL;
891
892 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
893 data &= RTL8366RB_EB_BDTH_MASK;
894 if (data < RTL8366RB_EB_BDTH_MASK)
895 data += 1;
896
897 val->value.i = (int)data * RTL8366RB_BDTH_BASE;
898
899 return 0;
900 }
901
902 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
903 const struct switch_attr *attr,
904 struct switch_val *val)
905 {
906 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
907 u32 data;
908
909 if (val->value.i)
910 data = RTL8366RB_QOS_MASK;
911 else
912 data = 0;
913
914 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
915 }
916
917 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
918 const struct switch_attr *attr,
919 struct switch_val *val)
920 {
921 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
922 u32 data;
923
924 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
925 if (data & RTL8366RB_QOS_MASK)
926 val->value.i = 1;
927 else
928 val->value.i = 0;
929
930 return 0;
931 }
932
933 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
934 const struct switch_attr *attr,
935 struct switch_val *val)
936 {
937 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
938
939 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
940 return -EINVAL;
941
942 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
943 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
944 }
945
946 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
947 {
948 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
949 int err;
950
951 err = rtl8366rb_reset_chip(smi);
952 if (err)
953 return err;
954
955 err = rtl8366rb_hw_init(smi);
956 if (err)
957 return err;
958
959 return rtl8366_reset_vlan(smi);
960 }
961
962 static struct switch_attr rtl8366rb_globals[] = {
963 {
964 .type = SWITCH_TYPE_INT,
965 .name = "enable_learning",
966 .description = "Enable learning, enable aging",
967 .set = rtl8366rb_sw_set_learning_enable,
968 .get = rtl8366rb_sw_get_learning_enable,
969 .max = 1
970 }, {
971 .type = SWITCH_TYPE_INT,
972 .name = "enable_vlan",
973 .description = "Enable VLAN mode",
974 .set = rtl8366_sw_set_vlan_enable,
975 .get = rtl8366_sw_get_vlan_enable,
976 .max = 1,
977 .ofs = 1
978 }, {
979 .type = SWITCH_TYPE_INT,
980 .name = "enable_vlan4k",
981 .description = "Enable VLAN 4K mode",
982 .set = rtl8366_sw_set_vlan_enable,
983 .get = rtl8366_sw_get_vlan_enable,
984 .max = 1,
985 .ofs = 2
986 }, {
987 .type = SWITCH_TYPE_NOVAL,
988 .name = "reset_mibs",
989 .description = "Reset all MIB counters",
990 .set = rtl8366rb_sw_reset_mibs,
991 }, {
992 .type = SWITCH_TYPE_INT,
993 .name = "blinkrate",
994 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
995 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
996 .set = rtl8366rb_sw_set_blinkrate,
997 .get = rtl8366rb_sw_get_blinkrate,
998 .max = 5
999 }, {
1000 .type = SWITCH_TYPE_INT,
1001 .name = "enable_qos",
1002 .description = "Enable QOS",
1003 .set = rtl8366rb_sw_set_qos_enable,
1004 .get = rtl8366rb_sw_get_qos_enable,
1005 .max = 1
1006 },
1007 };
1008
1009 static struct switch_attr rtl8366rb_port[] = {
1010 {
1011 .type = SWITCH_TYPE_STRING,
1012 .name = "link",
1013 .description = "Get port link information",
1014 .max = 1,
1015 .set = NULL,
1016 .get = rtl8366rb_sw_get_port_link,
1017 }, {
1018 .type = SWITCH_TYPE_NOVAL,
1019 .name = "reset_mib",
1020 .description = "Reset single port MIB counters",
1021 .set = rtl8366rb_sw_reset_port_mibs,
1022 }, {
1023 .type = SWITCH_TYPE_STRING,
1024 .name = "mib",
1025 .description = "Get MIB counters for port",
1026 .max = 33,
1027 .set = NULL,
1028 .get = rtl8366_sw_get_port_mib,
1029 }, {
1030 .type = SWITCH_TYPE_INT,
1031 .name = "led",
1032 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1033 .max = 15,
1034 .set = rtl8366rb_sw_set_port_led,
1035 .get = rtl8366rb_sw_get_port_led,
1036 }, {
1037 .type = SWITCH_TYPE_INT,
1038 .name = "disable",
1039 .description = "Get/Set port state (enabled or disabled)",
1040 .max = 1,
1041 .set = rtl8366rb_sw_set_port_disable,
1042 .get = rtl8366rb_sw_get_port_disable,
1043 }, {
1044 .type = SWITCH_TYPE_INT,
1045 .name = "rate_in",
1046 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1047 .max = RTL8366RB_BDTH_SW_MAX,
1048 .set = rtl8366rb_sw_set_port_rate_in,
1049 .get = rtl8366rb_sw_get_port_rate_in,
1050 }, {
1051 .type = SWITCH_TYPE_INT,
1052 .name = "rate_out",
1053 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1054 .max = RTL8366RB_BDTH_SW_MAX,
1055 .set = rtl8366rb_sw_set_port_rate_out,
1056 .get = rtl8366rb_sw_get_port_rate_out,
1057 },
1058 };
1059
1060 static struct switch_attr rtl8366rb_vlan[] = {
1061 {
1062 .type = SWITCH_TYPE_STRING,
1063 .name = "info",
1064 .description = "Get vlan information",
1065 .max = 1,
1066 .set = NULL,
1067 .get = rtl8366_sw_get_vlan_info,
1068 },
1069 };
1070
1071 static const struct switch_dev_ops rtl8366_ops = {
1072 .attr_global = {
1073 .attr = rtl8366rb_globals,
1074 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1075 },
1076 .attr_port = {
1077 .attr = rtl8366rb_port,
1078 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1079 },
1080 .attr_vlan = {
1081 .attr = rtl8366rb_vlan,
1082 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1083 },
1084
1085 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1086 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1087 .get_port_pvid = rtl8366_sw_get_port_pvid,
1088 .set_port_pvid = rtl8366_sw_set_port_pvid,
1089 .reset_switch = rtl8366rb_sw_reset_switch,
1090 };
1091
1092 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1093 {
1094 struct switch_dev *dev = &smi->sw_dev;
1095 int err;
1096
1097 dev->name = "RTL8366RB";
1098 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1099 dev->ports = RTL8366RB_NUM_PORTS;
1100 dev->vlans = RTL8366RB_NUM_VIDS;
1101 dev->ops = &rtl8366_ops;
1102 dev->devname = dev_name(smi->parent);
1103
1104 err = register_switch(dev, NULL);
1105 if (err)
1106 dev_err(smi->parent, "switch registration failed\n");
1107
1108 return err;
1109 }
1110
1111 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1112 {
1113 unregister_switch(&smi->sw_dev);
1114 }
1115
1116 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1117 {
1118 struct rtl8366_smi *smi = bus->priv;
1119 u32 val = 0;
1120 int err;
1121
1122 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1123 if (err)
1124 return 0xffff;
1125
1126 return val;
1127 }
1128
1129 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1130 {
1131 struct rtl8366_smi *smi = bus->priv;
1132 u32 t;
1133 int err;
1134
1135 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1136 /* flush write */
1137 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1138
1139 return err;
1140 }
1141
1142 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1143 {
1144 return (bus->read == rtl8366rb_mii_read &&
1145 bus->write == rtl8366rb_mii_write);
1146 }
1147
1148 static int rtl8366rb_setup(struct rtl8366_smi *smi)
1149 {
1150 int ret;
1151
1152 ret = rtl8366rb_reset_chip(smi);
1153 if (ret)
1154 return ret;
1155
1156 ret = rtl8366rb_hw_init(smi);
1157 return ret;
1158 }
1159
1160 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1161 {
1162 u32 chip_id = 0;
1163 u32 chip_ver = 0;
1164 int ret;
1165
1166 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1167 if (ret) {
1168 dev_err(smi->parent, "unable to read chip id\n");
1169 return ret;
1170 }
1171
1172 switch (chip_id) {
1173 case RTL8366RB_CHIP_ID_8366:
1174 break;
1175 default:
1176 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1177 return -ENODEV;
1178 }
1179
1180 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1181 &chip_ver);
1182 if (ret) {
1183 dev_err(smi->parent, "unable to read chip version\n");
1184 return ret;
1185 }
1186
1187 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1188 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1189
1190 return 0;
1191 }
1192
1193 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1194 .detect = rtl8366rb_detect,
1195 .setup = rtl8366rb_setup,
1196
1197 .mii_read = rtl8366rb_mii_read,
1198 .mii_write = rtl8366rb_mii_write,
1199
1200 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1201 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1202 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1203 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1204 .get_mc_index = rtl8366rb_get_mc_index,
1205 .set_mc_index = rtl8366rb_set_mc_index,
1206 .get_mib_counter = rtl8366rb_get_mib_counter,
1207 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1208 .enable_vlan = rtl8366rb_enable_vlan,
1209 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1210 };
1211
1212 static int __init rtl8366rb_probe(struct platform_device *pdev)
1213 {
1214 static int rtl8366_smi_version_printed;
1215 struct rtl8366rb_platform_data *pdata;
1216 struct rtl8366_smi *smi;
1217 int err;
1218
1219 if (!rtl8366_smi_version_printed++)
1220 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1221 " version " RTL8366RB_DRIVER_VER"\n");
1222
1223 pdata = pdev->dev.platform_data;
1224 if (!pdata) {
1225 dev_err(&pdev->dev, "no platform data specified\n");
1226 err = -EINVAL;
1227 goto err_out;
1228 }
1229
1230 smi = rtl8366_smi_alloc(&pdev->dev);
1231 if (!smi) {
1232 err = -ENOMEM;
1233 goto err_out;
1234 }
1235
1236 smi->gpio_sda = pdata->gpio_sda;
1237 smi->gpio_sck = pdata->gpio_sck;
1238 smi->ops = &rtl8366rb_smi_ops;
1239 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1240 smi->num_ports = RTL8366RB_NUM_PORTS;
1241 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1242 smi->mib_counters = rtl8366rb_mib_counters;
1243 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1244
1245 err = rtl8366_smi_init(smi);
1246 if (err)
1247 goto err_free_smi;
1248
1249 platform_set_drvdata(pdev, smi);
1250
1251 err = rtl8366rb_switch_init(smi);
1252 if (err)
1253 goto err_clear_drvdata;
1254
1255 return 0;
1256
1257 err_clear_drvdata:
1258 platform_set_drvdata(pdev, NULL);
1259 rtl8366_smi_cleanup(smi);
1260 err_free_smi:
1261 kfree(smi);
1262 err_out:
1263 return err;
1264 }
1265
1266 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1267 {
1268 if (!rtl8366rb_mii_bus_match(phydev->bus))
1269 return -EINVAL;
1270
1271 return 0;
1272 }
1273
1274 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1275 {
1276 /* phy 4 might be connected to a second mac, allow aneg config */
1277 if (phydev->addr == RTL8366RB_PHY_WAN)
1278 return genphy_config_aneg(phydev);
1279
1280 return 0;
1281 }
1282
1283 static struct phy_driver rtl8366rb_phy_driver = {
1284 .phy_id = 0x001cc960,
1285 .name = "Realtek RTL8366RB",
1286 .phy_id_mask = 0x1ffffff0,
1287 .features = PHY_GBIT_FEATURES,
1288 .config_aneg = rtl8366rb_phy_config_aneg,
1289 .config_init = rtl8366rb_phy_config_init,
1290 .read_status = genphy_read_status,
1291 .driver = {
1292 .owner = THIS_MODULE,
1293 },
1294 };
1295
1296 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1297 {
1298 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1299
1300 if (smi) {
1301 rtl8366rb_switch_cleanup(smi);
1302 platform_set_drvdata(pdev, NULL);
1303 rtl8366_smi_cleanup(smi);
1304 kfree(smi);
1305 }
1306
1307 return 0;
1308 }
1309
1310 static struct platform_driver rtl8366rb_driver = {
1311 .driver = {
1312 .name = RTL8366RB_DRIVER_NAME,
1313 .owner = THIS_MODULE,
1314 },
1315 .probe = rtl8366rb_probe,
1316 .remove = __devexit_p(rtl8366rb_remove),
1317 };
1318
1319 static int __init rtl8366rb_module_init(void)
1320 {
1321 int ret;
1322 ret = platform_driver_register(&rtl8366rb_driver);
1323 if (ret)
1324 return ret;
1325
1326 ret = phy_driver_register(&rtl8366rb_phy_driver);
1327 if (ret)
1328 goto err_platform_unregister;
1329
1330 return 0;
1331
1332 err_platform_unregister:
1333 platform_driver_unregister(&rtl8366rb_driver);
1334 return ret;
1335 }
1336 module_init(rtl8366rb_module_init);
1337
1338 static void __exit rtl8366rb_module_exit(void)
1339 {
1340 phy_driver_unregister(&rtl8366rb_phy_driver);
1341 platform_driver_unregister(&rtl8366rb_driver);
1342 }
1343 module_exit(rtl8366rb_module_exit);
1344
1345 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1346 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1347 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1348 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1349 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1350 MODULE_LICENSE("GPL v2");
1351 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
OpenWrt Source Repository