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kernel: rtl8367(b): fix build error
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8367b.c
1 /*
2 * Platform driver for the Realtek RTL8367R-VB ethernet switches
3 *
4 * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8367.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8367B_RESET_DELAY 1000 /* msecs*/
24
25 #define RTL8367B_PHY_ADDR_MAX 8
26 #define RTL8367B_PHY_REG_MAX 31
27
28 #define RTL8367B_VID_MASK 0x3fff
29 #define RTL8367B_FID_MASK 0xf
30 #define RTL8367B_UNTAG_MASK 0xff
31 #define RTL8367B_MEMBER_MASK 0xff
32
33 #define RTL8367B_PORT_MISC_CFG_REG(_p) (0x000e + 0x20 * (_p))
34 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT 4
35 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK 0x3
36 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL 0
37 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP 1
38 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI 2
39 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL 3
40
41 #define RTL8367B_BYPASS_LINE_RATE_REG 0x03f7
42
43 #define RTL8367B_TA_CTRL_REG 0x0500 /*GOOD*/
44 #define RTL8367B_TA_CTRL_SPA_SHIFT 8
45 #define RTL8367B_TA_CTRL_SPA_MASK 0x7
46 #define RTL8367B_TA_CTRL_METHOD BIT(4)/*GOOD*/
47 #define RTL8367B_TA_CTRL_CMD_SHIFT 3
48 #define RTL8367B_TA_CTRL_CMD_READ 0
49 #define RTL8367B_TA_CTRL_CMD_WRITE 1
50 #define RTL8367B_TA_CTRL_TABLE_SHIFT 0 /*GOOD*/
51 #define RTL8367B_TA_CTRL_TABLE_ACLRULE 1
52 #define RTL8367B_TA_CTRL_TABLE_ACLACT 2
53 #define RTL8367B_TA_CTRL_TABLE_CVLAN 3
54 #define RTL8367B_TA_CTRL_TABLE_L2 4
55 #define RTL8367B_TA_CTRL_CVLAN_READ \
56 ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \
57 RTL8367B_TA_CTRL_TABLE_CVLAN)
58 #define RTL8367B_TA_CTRL_CVLAN_WRITE \
59 ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \
60 RTL8367B_TA_CTRL_TABLE_CVLAN)
61
62 #define RTL8367B_TA_ADDR_REG 0x0501/*GOOD*/
63 #define RTL8367B_TA_ADDR_MASK 0x3fff/*GOOD*/
64
65 #define RTL8367B_TA_LUT_REG 0x0502/*GOOD*/
66
67 #define RTL8367B_TA_WRDATA_REG(_x) (0x0510 + (_x))/*GOOD*/
68 #define RTL8367B_TA_VLAN_NUM_WORDS 2
69 #define RTL8367B_TA_VLAN_VID_MASK RTL8367B_VID_MASK
70 #define RTL8367B_TA_VLAN0_MEMBER_SHIFT 0
71 #define RTL8367B_TA_VLAN0_MEMBER_MASK RTL8367B_MEMBER_MASK
72 #define RTL8367B_TA_VLAN0_UNTAG_SHIFT 8
73 #define RTL8367B_TA_VLAN0_UNTAG_MASK RTL8367B_MEMBER_MASK
74 #define RTL8367B_TA_VLAN1_FID_SHIFT 0
75 #define RTL8367B_TA_VLAN1_FID_MASK RTL8367B_FID_MASK
76
77 #define RTL8367B_TA_RDDATA_REG(_x) (0x0520 + (_x))/*GOOD*/
78
79 #define RTL8367B_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) /*GOOD*/
80 #define RTL8367B_VLAN_PVID_CTRL_MASK 0x1f /*GOOD*/
81 #define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) /*GOOD*/
82
83 #define RTL8367B_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) /*GOOD*/
84 #define RTL8367B_VLAN_MC_NUM_WORDS 4 /*GOOD*/
85 #define RTL8367B_VLAN_MC0_MEMBER_SHIFT 0/*GOOD*/
86 #define RTL8367B_VLAN_MC0_MEMBER_MASK RTL8367B_MEMBER_MASK/*GOOD*/
87 #define RTL8367B_VLAN_MC1_FID_SHIFT 0/*GOOD*/
88 #define RTL8367B_VLAN_MC1_FID_MASK RTL8367B_FID_MASK/*GOOD*/
89 #define RTL8367B_VLAN_MC3_EVID_SHIFT 0/*GOOD*/
90 #define RTL8367B_VLAN_MC3_EVID_MASK RTL8367B_VID_MASK/*GOOD*/
91
92 #define RTL8367B_VLAN_CTRL_REG 0x07a8 /*GOOD*/
93 #define RTL8367B_VLAN_CTRL_ENABLE BIT(0)
94
95 #define RTL8367B_VLAN_INGRESS_REG 0x07a9 /*GOOD*/
96
97 #define RTL8367B_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) /*GOOD*/
98
99 #define RTL8367B_MIB_COUNTER_REG(_x) (0x1000 + (_x)) /*GOOD*/
100 #define RTL8367B_MIB_COUNTER_PORT_OFFSET 0x007c /*GOOD*/
101
102 #define RTL8367B_MIB_ADDRESS_REG 0x1004 /*GOOD*/
103
104 #define RTL8367B_MIB_CTRL0_REG(_x) (0x1005 + (_x)) /*GOOD*/
105 #define RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK BIT(11) /*GOOD*/
106 #define RTL8367B_MIB_CTRL0_QM_RESET_MASK BIT(10) /*GOOD*/
107 #define RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/
108 #define RTL8367B_MIB_CTRL0_RESET_MASK BIT(1) /*GOOD*/
109 #define RTL8367B_MIB_CTRL0_BUSY_MASK BIT(0) /*GOOD*/
110
111 #define RTL8367B_SWC0_REG 0x1200/*GOOD*/
112 #define RTL8367B_SWC0_MAX_LENGTH_SHIFT 13/*GOOD*/
113 #define RTL8367B_SWC0_MAX_LENGTH(_x) ((_x) << 13) /*GOOD*/
114 #define RTL8367B_SWC0_MAX_LENGTH_MASK RTL8367B_SWC0_MAX_LENGTH(0x3)
115 #define RTL8367B_SWC0_MAX_LENGTH_1522 RTL8367B_SWC0_MAX_LENGTH(0)
116 #define RTL8367B_SWC0_MAX_LENGTH_1536 RTL8367B_SWC0_MAX_LENGTH(1)
117 #define RTL8367B_SWC0_MAX_LENGTH_1552 RTL8367B_SWC0_MAX_LENGTH(2)
118 #define RTL8367B_SWC0_MAX_LENGTH_16000 RTL8367B_SWC0_MAX_LENGTH(3)
119
120 #define RTL8367B_CHIP_NUMBER_REG 0x1300/*GOOD*/
121
122 #define RTL8367B_CHIP_VER_REG 0x1301/*GOOD*/
123 #define RTL8367B_CHIP_VER_RLVID_SHIFT 12/*GOOD*/
124 #define RTL8367B_CHIP_VER_RLVID_MASK 0xf/*GOOD*/
125 #define RTL8367B_CHIP_VER_MCID_SHIFT 8/*GOOD*/
126 #define RTL8367B_CHIP_VER_MCID_MASK 0xf/*GOOD*/
127 #define RTL8367B_CHIP_VER_BOID_SHIFT 4/*GOOD*/
128 #define RTL8367B_CHIP_VER_BOID_MASK 0xf/*GOOD*/
129 #define RTL8367B_CHIP_VER_AFE_SHIFT 0/*GOOD*/
130 #define RTL8367B_CHIP_VER_AFE_MASK 0x1/*GOOD*/
131
132 #define RTL8367B_CHIP_MODE_REG 0x1302
133 #define RTL8367B_CHIP_MODE_MASK 0x7
134
135 #define RTL8367B_CHIP_DEBUG0_REG 0x1303
136 #define RTL8367B_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x))
137
138 #define RTL8367B_CHIP_DEBUG1_REG 0x1304
139
140 #define RTL8367B_DIS_REG 0x1305
141 #define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
142 #define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x))
143 #define RTL8367B_DIS_RGMII_MASK 0x7
144
145 #define RTL8367B_EXT_RGMXF_REG(_x) (0x1306 + (_x))
146 #define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5
147 #define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff
148 #define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3
149 #define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1
150 #define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7
151
152 #define RTL8367B_DI_FORCE_REG(_x) (0x1310 + (_x))
153 #define RTL8367B_DI_FORCE_MODE BIT(12)
154 #define RTL8367B_DI_FORCE_NWAY BIT(7)
155 #define RTL8367B_DI_FORCE_TXPAUSE BIT(6)
156 #define RTL8367B_DI_FORCE_RXPAUSE BIT(5)
157 #define RTL8367B_DI_FORCE_LINK BIT(4)
158 #define RTL8367B_DI_FORCE_DUPLEX BIT(2)
159 #define RTL8367B_DI_FORCE_SPEED_MASK 3
160 #define RTL8367B_DI_FORCE_SPEED_10 0
161 #define RTL8367B_DI_FORCE_SPEED_100 1
162 #define RTL8367B_DI_FORCE_SPEED_1000 2
163
164 #define RTL8367B_MAC_FORCE_REG(_x) (0x1312 + (_x))
165
166 #define RTL8367B_CHIP_RESET_REG 0x1322 /*GOOD*/
167 #define RTL8367B_CHIP_RESET_SW BIT(1) /*GOOD*/
168 #define RTL8367B_CHIP_RESET_HW BIT(0) /*GOOD*/
169
170 #define RTL8367B_PORT_STATUS_REG(_p) (0x1352 + (_p)) /*GOOD*/
171 #define RTL8367B_PORT_STATUS_EN_1000_SPI BIT(11) /*GOOD*/
172 #define RTL8367B_PORT_STATUS_EN_100_SPI BIT(10)/*GOOD*/
173 #define RTL8367B_PORT_STATUS_NWAY_FAULT BIT(9)/*GOOD*/
174 #define RTL8367B_PORT_STATUS_LINK_MASTER BIT(8)/*GOOD*/
175 #define RTL8367B_PORT_STATUS_NWAY BIT(7)/*GOOD*/
176 #define RTL8367B_PORT_STATUS_TXPAUSE BIT(6)/*GOOD*/
177 #define RTL8367B_PORT_STATUS_RXPAUSE BIT(5)/*GOOD*/
178 #define RTL8367B_PORT_STATUS_LINK BIT(4)/*GOOD*/
179 #define RTL8367B_PORT_STATUS_DUPLEX BIT(2)/*GOOD*/
180 #define RTL8367B_PORT_STATUS_SPEED_MASK 0x0003/*GOOD*/
181 #define RTL8367B_PORT_STATUS_SPEED_10 0/*GOOD*/
182 #define RTL8367B_PORT_STATUS_SPEED_100 1/*GOOD*/
183 #define RTL8367B_PORT_STATUS_SPEED_1000 2/*GOOD*/
184
185 #define RTL8367B_RTL_MAGIC_ID_REG 0x13c2
186 #define RTL8367B_RTL_MAGIC_ID_VAL 0x0249
187
188 #define RTL8367B_IA_CTRL_REG 0x1f00
189 #define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1)
190 #define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0)
191 #define RTL8367B_IA_CTRL_RW_WRITE RTL8367B_IA_CTRL_RW(1)
192 #define RTL8367B_IA_CTRL_CMD_MASK BIT(0)
193
194 #define RTL8367B_IA_STATUS_REG 0x1f01
195 #define RTL8367B_IA_STATUS_PHY_BUSY BIT(2)
196 #define RTL8367B_IA_STATUS_SDS_BUSY BIT(1)
197 #define RTL8367B_IA_STATUS_MDX_BUSY BIT(0)
198
199 #define RTL8367B_IA_ADDRESS_REG 0x1f02
200 #define RTL8367B_IA_WRITE_DATA_REG 0x1f03
201 #define RTL8367B_IA_READ_DATA_REG 0x1f04
202
203 #define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
204
205 #define RTL8367B_NUM_MIB_COUNTERS 58
206
207 #define RTL8367B_CPU_PORT_NUM 5
208 #define RTL8367B_NUM_PORTS 8
209 #define RTL8367B_NUM_VLANS 32
210 #define RTL8367B_NUM_VIDS 4096
211 #define RTL8367B_PRIORITYMAX 7
212 #define RTL8367B_FIDMAX 7
213
214 #define RTL8367B_PORT_0 BIT(0)
215 #define RTL8367B_PORT_1 BIT(1)
216 #define RTL8367B_PORT_2 BIT(2)
217 #define RTL8367B_PORT_3 BIT(3)
218 #define RTL8367B_PORT_4 BIT(4)
219 #define RTL8367B_PORT_E0 BIT(5) /* External port 0 */
220 #define RTL8367B_PORT_E1 BIT(6) /* External port 1 */
221 #define RTL8367B_PORT_E2 BIT(7) /* External port 2 */
222
223 #define RTL8367B_PORTS_ALL \
224 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
225 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
226 RTL8367B_PORT_E1 | RTL8367B_PORT_E2)
227
228 #define RTL8367B_PORTS_ALL_BUT_CPU \
229 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
230 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
231 RTL8367B_PORT_E2)
232
233 struct rtl8367b_initval {
234 u16 reg;
235 u16 val;
236 };
237
238 static struct rtl8366_mib_counter
239 rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
240 {0, 0, 4, "ifInOctets" },
241 {0, 4, 2, "dot3StatsFCSErrors" },
242 {0, 6, 2, "dot3StatsSymbolErrors" },
243 {0, 8, 2, "dot3InPauseFrames" },
244 {0, 10, 2, "dot3ControlInUnknownOpcodes" },
245 {0, 12, 2, "etherStatsFragments" },
246 {0, 14, 2, "etherStatsJabbers" },
247 {0, 16, 2, "ifInUcastPkts" },
248 {0, 18, 2, "etherStatsDropEvents" },
249 {0, 20, 2, "ifInMulticastPkts" },
250 {0, 22, 2, "ifInBroadcastPkts" },
251 {0, 24, 2, "inMldChecksumError" },
252 {0, 26, 2, "inIgmpChecksumError" },
253 {0, 28, 2, "inMldSpecificQuery" },
254 {0, 30, 2, "inMldGeneralQuery" },
255 {0, 32, 2, "inIgmpSpecificQuery" },
256 {0, 34, 2, "inIgmpGeneralQuery" },
257 {0, 36, 2, "inMldLeaves" },
258 {0, 38, 2, "inIgmpLeaves" },
259
260 {0, 40, 4, "etherStatsOctets" },
261 {0, 44, 2, "etherStatsUnderSizePkts" },
262 {0, 46, 2, "etherOversizeStats" },
263 {0, 48, 2, "etherStatsPkts64Octets" },
264 {0, 50, 2, "etherStatsPkts65to127Octets" },
265 {0, 52, 2, "etherStatsPkts128to255Octets" },
266 {0, 54, 2, "etherStatsPkts256to511Octets" },
267 {0, 56, 2, "etherStatsPkts512to1023Octets" },
268 {0, 58, 2, "etherStatsPkts1024to1518Octets" },
269
270 {0, 60, 4, "ifOutOctets" },
271 {0, 64, 2, "dot3StatsSingleCollisionFrames" },
272 {0, 66, 2, "dot3StatMultipleCollisionFrames" },
273 {0, 68, 2, "dot3sDeferredTransmissions" },
274 {0, 70, 2, "dot3StatsLateCollisions" },
275 {0, 72, 2, "etherStatsCollisions" },
276 {0, 74, 2, "dot3StatsExcessiveCollisions" },
277 {0, 76, 2, "dot3OutPauseFrames" },
278 {0, 78, 2, "ifOutDiscards" },
279 {0, 80, 2, "dot1dTpPortInDiscards" },
280 {0, 82, 2, "ifOutUcastPkts" },
281 {0, 84, 2, "ifOutMulticastPkts" },
282 {0, 86, 2, "ifOutBroadcastPkts" },
283 {0, 88, 2, "outOampduPkts" },
284 {0, 90, 2, "inOampduPkts" },
285 {0, 92, 2, "inIgmpJoinsSuccess" },
286 {0, 94, 2, "inIgmpJoinsFail" },
287 {0, 96, 2, "inMldJoinsSuccess" },
288 {0, 98, 2, "inMldJoinsFail" },
289 {0, 100, 2, "inReportSuppressionDrop" },
290 {0, 102, 2, "inLeaveSuppressionDrop" },
291 {0, 104, 2, "outIgmpReports" },
292 {0, 106, 2, "outIgmpLeaves" },
293 {0, 108, 2, "outIgmpGeneralQuery" },
294 {0, 110, 2, "outIgmpSpecificQuery" },
295 {0, 112, 2, "outMldReports" },
296 {0, 114, 2, "outMldLeaves" },
297 {0, 116, 2, "outMldGeneralQuery" },
298 {0, 118, 2, "outMldSpecificQuery" },
299 {0, 120, 2, "inKnownMulticastPkts" },
300 };
301
302 #define REG_RD(_smi, _reg, _val) \
303 do { \
304 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
305 if (err) \
306 return err; \
307 } while (0)
308
309 #define REG_WR(_smi, _reg, _val) \
310 do { \
311 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
312 if (err) \
313 return err; \
314 } while (0)
315
316 #define REG_RMW(_smi, _reg, _mask, _val) \
317 do { \
318 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
319 if (err) \
320 return err; \
321 } while (0)
322
323 static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {
324 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
325 {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
326 {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
327 {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
328 {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
329 {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
330 {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
331 {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
332 {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
333 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
334 {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
335 {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
336 {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
337 {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
338 {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
339 {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
340 {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
341 {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
342 {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
343 {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
344 {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
345 {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
346 {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
347 {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
348 {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
349 {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
350 {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
351 {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
352 {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
353 {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
354 {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
355 {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
356 {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
357 {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
358 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
359 {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
360 {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
361 {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
362 {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
363 {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
364 {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
365 {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
366 {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
367 {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
368 {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
369 {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
370 {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
371 {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
372 {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
373 {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
374 {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
375 {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
376 {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
377 {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
378 {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
379 {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
380 {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
381 {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
382 {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
383 {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
384 {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
385 {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
386 {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
387 {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
388 {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
389 {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
390 {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
391 {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
392 {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
393 {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
394 {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
395 {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
396 {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
397 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
398 {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
399 {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
400 {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
401 {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
402 {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
403 {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
404 {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
405 {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
406 {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
407 {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
408 {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
409 {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
410 {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
411 {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
412 {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
413 {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
414 {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
415 {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
416 {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
417 {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
418 {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
419 {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
420 {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
421 {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
422 {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
423 {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
424 {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
425 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
426 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
427 {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
428 {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
429 {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
430 {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
431 {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
432 {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
433 {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
434 {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
435 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
436 {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
437 {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
438 {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
439 {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
440 {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
441 {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
442 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
443 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
444 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
445 {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
446 {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
447 {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
448 {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
449 {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
450 {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
451 {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
452 {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
453 {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
454 {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
455 {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
456 {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
457 {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
458 {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
459 {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
460 {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
461 {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
462 {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
463 {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
464 {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
465 {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
466 {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
467 {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
468 {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
469 {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
470 {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
471 {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
472 {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
473 {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
474 {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
475 {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
476 {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
477 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
478 {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
479 {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
480 {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
481 {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
482 {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
483 {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
484 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
485 {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
486 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
487 {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
488 {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
489 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
490 {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
491 {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
492 {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
493 {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
494 {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
495 {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
496 {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
497 {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
498 {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
499 {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
500 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
501 {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
502 {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
503 {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
504 {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
505 {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
506 {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
507 {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
508 {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
509 {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
510 {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
511 {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
512 {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
513 {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
514 {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
515 {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
516 {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
517 {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
518 {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
519 {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
520 {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
521 {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
522 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
523 {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
524 {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
525 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
526 {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
527 {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
528 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
529 {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
530 {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
531 {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
532 {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
533 {0x13EB, 0x11BB}
534 };
535
536 static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
537 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
538 {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
539 {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
540 {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
541 {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
542 {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
543 {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
544 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
545 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
546 {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
547 {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
548 {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
549 {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
550 {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
551 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
552 {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
553 {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
554 {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
555 {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
556 {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
557 {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
558 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
559 {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
560 {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
561 {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
562 {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
563 {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
564 {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
565 {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
566 {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
567 {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
568 {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
569 {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
570 {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
571 {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
572 {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
573 {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
574 {0x133E, 0x000E}, {0x133F, 0x0010},
575 };
576
577 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
578 const struct rtl8367b_initval *initvals,
579 int count)
580 {
581 int err;
582 int i;
583
584 for (i = 0; i < count; i++)
585 REG_WR(smi, initvals[i].reg, initvals[i].val);
586
587 return 0;
588 }
589
590 static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,
591 u32 phy_addr, u32 phy_reg, u32 *val)
592 {
593 int timeout;
594 u32 data;
595 int err;
596
597 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
598 return -EINVAL;
599
600 if (phy_reg > RTL8367B_PHY_REG_MAX)
601 return -EINVAL;
602
603 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
604 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
605 return -ETIMEDOUT;
606
607 /* prepare address */
608 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
609 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
610
611 /* send read command */
612 REG_WR(smi, RTL8367B_IA_CTRL_REG,
613 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);
614
615 timeout = 5;
616 do {
617 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
618 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
619 break;
620
621 if (timeout--) {
622 dev_err(smi->parent, "phy read timed out\n");
623 return -ETIMEDOUT;
624 }
625
626 udelay(1);
627 } while (1);
628
629 /* read data */
630 REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);
631
632 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
633 phy_addr, phy_reg, *val);
634 return 0;
635 }
636
637 static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
638 u32 phy_addr, u32 phy_reg, u32 val)
639 {
640 int timeout;
641 u32 data;
642 int err;
643
644 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
645 phy_addr, phy_reg, val);
646
647 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
648 return -EINVAL;
649
650 if (phy_reg > RTL8367B_PHY_REG_MAX)
651 return -EINVAL;
652
653 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
654 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
655 return -ETIMEDOUT;
656
657 /* preapre data */
658 REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);
659
660 /* prepare address */
661 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
662 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
663
664 /* send write command */
665 REG_WR(smi, RTL8367B_IA_CTRL_REG,
666 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);
667
668 timeout = 5;
669 do {
670 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
671 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
672 break;
673
674 if (timeout--) {
675 dev_err(smi->parent, "phy write timed out\n");
676 return -ETIMEDOUT;
677 }
678
679 udelay(1);
680 } while (1);
681
682 return 0;
683 }
684
685 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
686 {
687 const struct rtl8367b_initval *initvals;
688 u32 chip_ver;
689 u32 rlvid;
690 int count;
691 int err;
692
693 REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
694 REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
695
696 rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
697 RTL8367B_CHIP_VER_RLVID_MASK;
698
699 switch (rlvid) {
700 case 0:
701 initvals = rtl8367r_vb_initvals_0;
702 count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
703 break;
704
705 case 1:
706 initvals = rtl8367r_vb_initvals_1;
707 count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
708 break;
709
710 default:
711 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
712 return -ENODEV;
713 }
714
715 /* TODO: disable RLTP */
716
717 return rtl8367b_write_initvals(smi, initvals, count);
718 }
719
720 static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
721 {
722 int timeout = 10;
723 int err;
724 u32 data;
725
726 REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);
727 msleep(RTL8367B_RESET_DELAY);
728
729 do {
730 REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);
731 if (!(data & RTL8367B_CHIP_RESET_HW))
732 break;
733
734 msleep(1);
735 } while (--timeout);
736
737 if (!timeout) {
738 dev_err(smi->parent, "chip reset timed out\n");
739 return -ETIMEDOUT;
740 }
741
742 return 0;
743 }
744
745 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
746 enum rtl8367_extif_mode mode)
747 {
748 int err;
749
750 /* set port mode */
751 switch (mode) {
752 case RTL8367_EXTIF_MODE_RGMII:
753 case RTL8367_EXTIF_MODE_RGMII_33V:
754 REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367);
755 REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777);
756 break;
757
758 case RTL8367_EXTIF_MODE_TMII_MAC:
759 case RTL8367_EXTIF_MODE_TMII_PHY:
760 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
761 BIT((id + 1) % 2), BIT((id + 1) % 2));
762 break;
763
764 case RTL8367_EXTIF_MODE_GMII:
765 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
766 RTL8367B_CHIP_DEBUG0_DUMMY0(id),
767 RTL8367B_CHIP_DEBUG0_DUMMY0(id));
768 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
769 break;
770
771 case RTL8367_EXTIF_MODE_MII_MAC:
772 case RTL8367_EXTIF_MODE_MII_PHY:
773 case RTL8367_EXTIF_MODE_DISABLED:
774 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
775 BIT((id + 1) % 2), 0);
776 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
777 break;
778
779 default:
780 dev_err(smi->parent,
781 "invalid mode for external interface %d\n", id);
782 return -EINVAL;
783 }
784
785 REG_RMW(smi, RTL8367B_DIS_REG,
786 RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
787 mode << RTL8367B_DIS_RGMII_SHIFT(id));
788
789 return 0;
790 }
791
792 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
793 struct rtl8367_port_ability *pa)
794 {
795 u32 mask;
796 u32 val;
797 int err;
798
799 mask = (RTL8367B_DI_FORCE_MODE |
800 RTL8367B_DI_FORCE_NWAY |
801 RTL8367B_DI_FORCE_TXPAUSE |
802 RTL8367B_DI_FORCE_RXPAUSE |
803 RTL8367B_DI_FORCE_LINK |
804 RTL8367B_DI_FORCE_DUPLEX |
805 RTL8367B_DI_FORCE_SPEED_MASK);
806
807 val = pa->speed;
808 val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
809 val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
810 val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
811 val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
812 val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
813 val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
814
815 REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
816
817 return 0;
818 }
819
820 static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
821 unsigned txdelay, unsigned rxdelay)
822 {
823 u32 mask;
824 u32 val;
825 int err;
826
827 mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |
828 (RTL8367B_EXT_RGMXF_TXDELAY_MASK <<
829 RTL8367B_EXT_RGMXF_TXDELAY_SHIFT));
830
831 val = rxdelay;
832 val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;
833
834 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);
835
836 return 0;
837 }
838
839 static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
840 struct rtl8367_extif_config *cfg)
841 {
842 enum rtl8367_extif_mode mode;
843 int err;
844
845 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
846
847 err = rtl8367b_extif_set_mode(smi, id, mode);
848 if (err)
849 return err;
850
851 if (mode != RTL8367_EXTIF_MODE_DISABLED) {
852 err = rtl8367b_extif_set_force(smi, id, &cfg->ability);
853 if (err)
854 return err;
855
856 err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,
857 cfg->rxdelay);
858 if (err)
859 return err;
860 }
861
862 return 0;
863 }
864
865 #ifdef CONFIG_OF
866 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
867 const char *name)
868 {
869 struct rtl8367_extif_config *cfg;
870 const __be32 *prop;
871 int size;
872 int err;
873
874 prop = of_get_property(smi->parent->of_node, name, &size);
875 if (!prop)
876 return rtl8367b_extif_init(smi, id, NULL);
877
878 if (size != (9 * sizeof(*prop))) {
879 dev_err(smi->parent, "%s property is invalid\n", name);
880 return -EINVAL;
881 }
882
883 cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);
884 if (!cfg)
885 return -ENOMEM;
886
887 cfg->txdelay = be32_to_cpup(prop++);
888 cfg->rxdelay = be32_to_cpup(prop++);
889 cfg->mode = be32_to_cpup(prop++);
890 cfg->ability.force_mode = be32_to_cpup(prop++);
891 cfg->ability.txpause = be32_to_cpup(prop++);
892 cfg->ability.rxpause = be32_to_cpup(prop++);
893 cfg->ability.link = be32_to_cpup(prop++);
894 cfg->ability.duplex = be32_to_cpup(prop++);
895 cfg->ability.speed = be32_to_cpup(prop++);
896
897 err = rtl8367b_extif_init(smi, id, cfg);
898 kfree(cfg);
899
900 return err;
901 }
902 #else
903 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
904 const char *name)
905 {
906 return -EINVAL;
907 }
908 #endif
909
910 static int rtl8367b_setup(struct rtl8366_smi *smi)
911 {
912 struct rtl8367_platform_data *pdata;
913 int err;
914 int i;
915
916 pdata = smi->parent->platform_data;
917
918 err = rtl8367b_init_regs(smi);
919 if (err)
920 return err;
921
922 /* initialize external interfaces */
923 if (smi->parent->of_node) {
924 err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
925 if (err)
926 return err;
927
928 err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
929 if (err)
930 return err;
931 } else {
932 err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
933 if (err)
934 return err;
935
936 err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
937 if (err)
938 return err;
939 }
940
941 /* set maximum packet length to 1536 bytes */
942 REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,
943 RTL8367B_SWC0_MAX_LENGTH_1536);
944
945 /*
946 * discard VLAN tagged packets if the port is not a member of
947 * the VLAN with which the packets is associated.
948 */
949 REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);
950
951 /*
952 * Setup egress tag mode for each port.
953 */
954 for (i = 0; i < RTL8367B_NUM_PORTS; i++)
955 REG_RMW(smi,
956 RTL8367B_PORT_MISC_CFG_REG(i),
957 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<
958 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,
959 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<
960 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);
961
962 return 0;
963 }
964
965 static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,
966 int port, unsigned long long *val)
967 {
968 struct rtl8366_mib_counter *mib;
969 int offset;
970 int i;
971 int err;
972 u32 addr, data;
973 u64 mibvalue;
974
975 if (port > RTL8367B_NUM_PORTS ||
976 counter >= RTL8367B_NUM_MIB_COUNTERS)
977 return -EINVAL;
978
979 mib = &rtl8367b_mib_counters[counter];
980 addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
981
982 /*
983 * Writing access counter address first
984 * then ASIC will prepare 64bits counter wait for being retrived
985 */
986 REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);
987
988 /* read MIB control register */
989 REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);
990
991 if (data & RTL8367B_MIB_CTRL0_BUSY_MASK)
992 return -EBUSY;
993
994 if (data & RTL8367B_MIB_CTRL0_RESET_MASK)
995 return -EIO;
996
997 if (mib->length == 4)
998 offset = 3;
999 else
1000 offset = (mib->offset + 1) % 4;
1001
1002 mibvalue = 0;
1003 for (i = 0; i < mib->length; i++) {
1004 REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);
1005 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1006 }
1007
1008 *val = mibvalue;
1009 return 0;
1010 }
1011
1012 static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
1013 struct rtl8366_vlan_4k *vlan4k)
1014 {
1015 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1016 int err;
1017 int i;
1018
1019 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1020
1021 if (vid >= RTL8367B_NUM_VIDS)
1022 return -EINVAL;
1023
1024 /* write VID */
1025 REG_WR(smi, RTL8367B_TA_ADDR_REG, vid);
1026
1027 /* write table access control word */
1028 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);
1029
1030 for (i = 0; i < ARRAY_SIZE(data); i++)
1031 REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);
1032
1033 vlan4k->vid = vid;
1034 vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &
1035 RTL8367B_TA_VLAN0_MEMBER_MASK;
1036 vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
1037 RTL8367B_TA_VLAN0_UNTAG_MASK;
1038 vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
1039 RTL8367B_TA_VLAN1_FID_MASK;
1040
1041 return 0;
1042 }
1043
1044 static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
1045 const struct rtl8366_vlan_4k *vlan4k)
1046 {
1047 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1048 int err;
1049 int i;
1050
1051 if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
1052 vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
1053 vlan4k->untag > RTL8367B_UNTAG_MASK ||
1054 vlan4k->fid > RTL8367B_FIDMAX)
1055 return -EINVAL;
1056
1057 memset(data, 0, sizeof(data));
1058
1059 data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<
1060 RTL8367B_TA_VLAN0_MEMBER_SHIFT;
1061 data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
1062 RTL8367B_TA_VLAN0_UNTAG_SHIFT;
1063 data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
1064 RTL8367B_TA_VLAN1_FID_SHIFT;
1065
1066 for (i = 0; i < ARRAY_SIZE(data); i++)
1067 REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
1068
1069 /* write VID */
1070 REG_WR(smi, RTL8367B_TA_ADDR_REG,
1071 vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
1072
1073 /* write table access control word */
1074 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
1075
1076 return 0;
1077 }
1078
1079 static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1080 struct rtl8366_vlan_mc *vlanmc)
1081 {
1082 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1083 int err;
1084 int i;
1085
1086 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1087
1088 if (index >= RTL8367B_NUM_VLANS)
1089 return -EINVAL;
1090
1091 for (i = 0; i < ARRAY_SIZE(data); i++)
1092 REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
1093
1094 vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &
1095 RTL8367B_VLAN_MC0_MEMBER_MASK;
1096 vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &
1097 RTL8367B_VLAN_MC1_FID_MASK;
1098 vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &
1099 RTL8367B_VLAN_MC3_EVID_MASK;
1100
1101 return 0;
1102 }
1103
1104 static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1105 const struct rtl8366_vlan_mc *vlanmc)
1106 {
1107 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1108 int err;
1109 int i;
1110
1111 if (index >= RTL8367B_NUM_VLANS ||
1112 vlanmc->vid >= RTL8367B_NUM_VIDS ||
1113 vlanmc->priority > RTL8367B_PRIORITYMAX ||
1114 vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
1115 vlanmc->untag > RTL8367B_UNTAG_MASK ||
1116 vlanmc->fid > RTL8367B_FIDMAX)
1117 return -EINVAL;
1118
1119 data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
1120 RTL8367B_VLAN_MC0_MEMBER_SHIFT;
1121 data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
1122 RTL8367B_VLAN_MC1_FID_SHIFT;
1123 data[2] = 0;
1124 data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<
1125 RTL8367B_VLAN_MC3_EVID_SHIFT;
1126
1127 for (i = 0; i < ARRAY_SIZE(data); i++)
1128 REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);
1129
1130 return 0;
1131 }
1132
1133 static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1134 {
1135 u32 data;
1136 int err;
1137
1138 if (port >= RTL8367B_NUM_PORTS)
1139 return -EINVAL;
1140
1141 REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
1142
1143 *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
1144 RTL8367B_VLAN_PVID_CTRL_MASK;
1145
1146 return 0;
1147 }
1148
1149 static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1150 {
1151 if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
1152 return -EINVAL;
1153
1154 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
1155 RTL8367B_VLAN_PVID_CTRL_MASK <<
1156 RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
1157 (index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
1158 RTL8367B_VLAN_PVID_CTRL_SHIFT(port));
1159 }
1160
1161 static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)
1162 {
1163 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,
1164 RTL8367B_VLAN_CTRL_ENABLE,
1165 (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);
1166 }
1167
1168 static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1169 {
1170 return 0;
1171 }
1172
1173 static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1174 {
1175 unsigned max = RTL8367B_NUM_VLANS;
1176
1177 if (smi->vlan4k_enabled)
1178 max = RTL8367B_NUM_VIDS - 1;
1179
1180 if (vlan == 0 || vlan >= max)
1181 return 0;
1182
1183 return 1;
1184 }
1185
1186 static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)
1187 {
1188 int err;
1189
1190 REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),
1191 (enable) ? RTL8367B_PORTS_ALL : 0);
1192
1193 return 0;
1194 }
1195
1196 static int rtl8367b_sw_reset_mibs(struct switch_dev *dev,
1197 const struct switch_attr *attr,
1198 struct switch_val *val)
1199 {
1200 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1201
1202 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,
1203 RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);
1204 }
1205
1206 static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
1207 int port,
1208 struct switch_port_link *link)
1209 {
1210 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1211 u32 data = 0;
1212 u32 speed;
1213
1214 if (port >= RTL8367B_NUM_PORTS)
1215 return -EINVAL;
1216
1217 rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
1218
1219 link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
1220 if (!link->link)
1221 return 0;
1222
1223 link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);
1224 link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);
1225 link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
1226 link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
1227
1228 speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
1229 switch (speed) {
1230 case 0:
1231 link->speed = SWITCH_PORT_SPEED_10;
1232 break;
1233 case 1:
1234 link->speed = SWITCH_PORT_SPEED_100;
1235 break;
1236 case 2:
1237 link->speed = SWITCH_PORT_SPEED_1000;
1238 break;
1239 default:
1240 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1241 break;
1242 }
1243
1244 return 0;
1245 }
1246
1247 static int rtl8367b_sw_get_max_length(struct switch_dev *dev,
1248 const struct switch_attr *attr,
1249 struct switch_val *val)
1250 {
1251 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1252 u32 data;
1253
1254 rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);
1255 val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>
1256 RTL8367B_SWC0_MAX_LENGTH_SHIFT;
1257
1258 return 0;
1259 }
1260
1261 static int rtl8367b_sw_set_max_length(struct switch_dev *dev,
1262 const struct switch_attr *attr,
1263 struct switch_val *val)
1264 {
1265 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1266 u32 max_len;
1267
1268 switch (val->value.i) {
1269 case 0:
1270 max_len = RTL8367B_SWC0_MAX_LENGTH_1522;
1271 break;
1272 case 1:
1273 max_len = RTL8367B_SWC0_MAX_LENGTH_1536;
1274 break;
1275 case 2:
1276 max_len = RTL8367B_SWC0_MAX_LENGTH_1552;
1277 break;
1278 case 3:
1279 max_len = RTL8367B_SWC0_MAX_LENGTH_16000;
1280 break;
1281 default:
1282 return -EINVAL;
1283 }
1284
1285 return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,
1286 RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
1287 }
1288
1289
1290 static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
1291 const struct switch_attr *attr,
1292 struct switch_val *val)
1293 {
1294 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1295 int port;
1296
1297 port = val->port_vlan;
1298 if (port >= RTL8367B_NUM_PORTS)
1299 return -EINVAL;
1300
1301 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,
1302 RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));
1303 }
1304
1305 static struct switch_attr rtl8367b_globals[] = {
1306 {
1307 .type = SWITCH_TYPE_INT,
1308 .name = "enable_vlan",
1309 .description = "Enable VLAN mode",
1310 .set = rtl8366_sw_set_vlan_enable,
1311 .get = rtl8366_sw_get_vlan_enable,
1312 .max = 1,
1313 .ofs = 1
1314 }, {
1315 .type = SWITCH_TYPE_INT,
1316 .name = "enable_vlan4k",
1317 .description = "Enable VLAN 4K mode",
1318 .set = rtl8366_sw_set_vlan_enable,
1319 .get = rtl8366_sw_get_vlan_enable,
1320 .max = 1,
1321 .ofs = 2
1322 }, {
1323 .type = SWITCH_TYPE_NOVAL,
1324 .name = "reset_mibs",
1325 .description = "Reset all MIB counters",
1326 .set = rtl8367b_sw_reset_mibs,
1327 }, {
1328 .type = SWITCH_TYPE_INT,
1329 .name = "max_length",
1330 .description = "Get/Set the maximum length of valid packets"
1331 "(0:1522, 1:1536, 2:1552, 3:16000)",
1332 .set = rtl8367b_sw_set_max_length,
1333 .get = rtl8367b_sw_get_max_length,
1334 .max = 3,
1335 }
1336 };
1337
1338 static struct switch_attr rtl8367b_port[] = {
1339 {
1340 .type = SWITCH_TYPE_NOVAL,
1341 .name = "reset_mib",
1342 .description = "Reset single port MIB counters",
1343 .set = rtl8367b_sw_reset_port_mibs,
1344 }, {
1345 .type = SWITCH_TYPE_STRING,
1346 .name = "mib",
1347 .description = "Get MIB counters for port",
1348 .max = 33,
1349 .set = NULL,
1350 .get = rtl8366_sw_get_port_mib,
1351 },
1352 };
1353
1354 static struct switch_attr rtl8367b_vlan[] = {
1355 {
1356 .type = SWITCH_TYPE_STRING,
1357 .name = "info",
1358 .description = "Get vlan information",
1359 .max = 1,
1360 .set = NULL,
1361 .get = rtl8366_sw_get_vlan_info,
1362 },
1363 };
1364
1365 static const struct switch_dev_ops rtl8367b_sw_ops = {
1366 .attr_global = {
1367 .attr = rtl8367b_globals,
1368 .n_attr = ARRAY_SIZE(rtl8367b_globals),
1369 },
1370 .attr_port = {
1371 .attr = rtl8367b_port,
1372 .n_attr = ARRAY_SIZE(rtl8367b_port),
1373 },
1374 .attr_vlan = {
1375 .attr = rtl8367b_vlan,
1376 .n_attr = ARRAY_SIZE(rtl8367b_vlan),
1377 },
1378
1379 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1380 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1381 .get_port_pvid = rtl8366_sw_get_port_pvid,
1382 .set_port_pvid = rtl8366_sw_set_port_pvid,
1383 .reset_switch = rtl8366_sw_reset_switch,
1384 .get_port_link = rtl8367b_sw_get_port_link,
1385 };
1386
1387 static int rtl8367b_switch_init(struct rtl8366_smi *smi)
1388 {
1389 struct switch_dev *dev = &smi->sw_dev;
1390 int err;
1391
1392 dev->name = "RTL8367B";
1393 dev->cpu_port = RTL8367B_CPU_PORT_NUM;
1394 dev->ports = RTL8367B_NUM_PORTS;
1395 dev->vlans = RTL8367B_NUM_VIDS;
1396 dev->ops = &rtl8367b_sw_ops;
1397 dev->alias = dev_name(smi->parent);
1398
1399 err = register_switch(dev, NULL);
1400 if (err)
1401 dev_err(smi->parent, "switch registration failed\n");
1402
1403 return err;
1404 }
1405
1406 static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)
1407 {
1408 unregister_switch(&smi->sw_dev);
1409 }
1410
1411 static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)
1412 {
1413 struct rtl8366_smi *smi = bus->priv;
1414 u32 val = 0;
1415 int err;
1416
1417 err = rtl8367b_read_phy_reg(smi, addr, reg, &val);
1418 if (err)
1419 return 0xffff;
1420
1421 return val;
1422 }
1423
1424 static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1425 {
1426 struct rtl8366_smi *smi = bus->priv;
1427 u32 t;
1428 int err;
1429
1430 err = rtl8367b_write_phy_reg(smi, addr, reg, val);
1431 if (err)
1432 return err;
1433
1434 /* flush write */
1435 (void) rtl8367b_read_phy_reg(smi, addr, reg, &t);
1436
1437 return err;
1438 }
1439
1440 static int rtl8367b_detect(struct rtl8366_smi *smi)
1441 {
1442 const char *chip_name;
1443 u32 chip_num;
1444 u32 chip_ver;
1445 u32 chip_mode;
1446 int ret;
1447
1448 /* TODO: improve chip detection */
1449 rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
1450 RTL8367B_RTL_MAGIC_ID_VAL);
1451
1452 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
1453 if (ret) {
1454 dev_err(smi->parent, "unable to read %s register\n",
1455 "chip number");
1456 return ret;
1457 }
1458
1459 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
1460 if (ret) {
1461 dev_err(smi->parent, "unable to read %s register\n",
1462 "chip version");
1463 return ret;
1464 }
1465
1466 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);
1467 if (ret) {
1468 dev_err(smi->parent, "unable to read %s register\n",
1469 "chip mode");
1470 return ret;
1471 }
1472
1473 switch (chip_ver) {
1474 case 0x1000:
1475 chip_name = "8367RB";
1476 break;
1477 case 0x1010:
1478 chip_name = "8367R-VB";
1479 break;
1480 default:
1481 dev_err(smi->parent,
1482 "unknown chip num:%04x ver:%04x, mode:%04x\n",
1483 chip_num, chip_ver, chip_mode);
1484 return -ENODEV;
1485 }
1486
1487 dev_info(smi->parent, "RTL%s chip found\n", chip_name);
1488
1489 return 0;
1490 }
1491
1492 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
1493 .detect = rtl8367b_detect,
1494 .reset_chip = rtl8367b_reset_chip,
1495 .setup = rtl8367b_setup,
1496
1497 .mii_read = rtl8367b_mii_read,
1498 .mii_write = rtl8367b_mii_write,
1499
1500 .get_vlan_mc = rtl8367b_get_vlan_mc,
1501 .set_vlan_mc = rtl8367b_set_vlan_mc,
1502 .get_vlan_4k = rtl8367b_get_vlan_4k,
1503 .set_vlan_4k = rtl8367b_set_vlan_4k,
1504 .get_mc_index = rtl8367b_get_mc_index,
1505 .set_mc_index = rtl8367b_set_mc_index,
1506 .get_mib_counter = rtl8367b_get_mib_counter,
1507 .is_vlan_valid = rtl8367b_is_vlan_valid,
1508 .enable_vlan = rtl8367b_enable_vlan,
1509 .enable_vlan4k = rtl8367b_enable_vlan4k,
1510 .enable_port = rtl8367b_enable_port,
1511 };
1512
1513 static int rtl8367b_probe(struct platform_device *pdev)
1514 {
1515 struct rtl8366_smi *smi;
1516 int err;
1517
1518 smi = rtl8366_smi_probe(pdev);
1519 if (!smi)
1520 return -ENODEV;
1521
1522 smi->clk_delay = 1500;
1523 smi->cmd_read = 0xb9;
1524 smi->cmd_write = 0xb8;
1525 smi->ops = &rtl8367b_smi_ops;
1526 smi->cpu_port = RTL8367B_CPU_PORT_NUM;
1527 smi->num_ports = RTL8367B_NUM_PORTS;
1528 smi->num_vlan_mc = RTL8367B_NUM_VLANS;
1529 smi->mib_counters = rtl8367b_mib_counters;
1530 smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
1531
1532 err = rtl8366_smi_init(smi);
1533 if (err)
1534 goto err_free_smi;
1535
1536 platform_set_drvdata(pdev, smi);
1537
1538 err = rtl8367b_switch_init(smi);
1539 if (err)
1540 goto err_clear_drvdata;
1541
1542 return 0;
1543
1544 err_clear_drvdata:
1545 platform_set_drvdata(pdev, NULL);
1546 rtl8366_smi_cleanup(smi);
1547 err_free_smi:
1548 kfree(smi);
1549 return err;
1550 }
1551
1552 static int rtl8367b_remove(struct platform_device *pdev)
1553 {
1554 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1555
1556 if (smi) {
1557 rtl8367b_switch_cleanup(smi);
1558 platform_set_drvdata(pdev, NULL);
1559 rtl8366_smi_cleanup(smi);
1560 kfree(smi);
1561 }
1562
1563 return 0;
1564 }
1565
1566 static void rtl8367b_shutdown(struct platform_device *pdev)
1567 {
1568 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1569
1570 if (smi)
1571 rtl8367b_reset_chip(smi);
1572 }
1573
1574 #ifdef CONFIG_OF
1575 static const struct of_device_id rtl8367b_match[] = {
1576 { .compatible = "realtek,rtl8367b" },
1577 { .compatible = "rtl8367b" },
1578 {},
1579 };
1580 MODULE_DEVICE_TABLE(of, rtl8367b_match);
1581 #endif
1582
1583 static struct platform_driver rtl8367b_driver = {
1584 .driver = {
1585 .name = RTL8367B_DRIVER_NAME,
1586 .owner = THIS_MODULE,
1587 #ifdef CONFIG_OF
1588 .of_match_table = of_match_ptr(rtl8367b_match),
1589 #endif
1590 },
1591 .probe = rtl8367b_probe,
1592 .remove = rtl8367b_remove,
1593 .shutdown = rtl8367b_shutdown,
1594 };
1595
1596 module_platform_driver(rtl8367b_driver);
1597
1598 MODULE_DESCRIPTION("Realtek RTL8367B ethernet switch driver");
1599 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1600 MODULE_LICENSE("GPL v2");
1601 MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
1602
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