e7fe79302a17d244cc868463549a3c5f0dbc8e7c
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8367b.c
1 /*
2 * Platform driver for the Realtek RTL8367R-VB ethernet switches
3 *
4 * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8367.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8367B_RESET_DELAY 1000 /* msecs*/
24
25 #define RTL8367B_PHY_ADDR_MAX 8
26 #define RTL8367B_PHY_REG_MAX 31
27
28 #define RTL8367B_VID_MASK 0x3fff
29 #define RTL8367B_FID_MASK 0xf
30 #define RTL8367B_UNTAG_MASK 0xff
31 #define RTL8367B_MEMBER_MASK 0xff
32
33 #define RTL8367B_PORT_MISC_CFG_REG(_p) (0x000e + 0x20 * (_p))
34 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT 4
35 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK 0x3
36 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL 0
37 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP 1
38 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI 2
39 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL 3
40
41 #define RTL8367B_BYPASS_LINE_RATE_REG 0x03f7
42
43 #define RTL8367B_TA_CTRL_REG 0x0500 /*GOOD*/
44 #define RTL8367B_TA_CTRL_SPA_SHIFT 8
45 #define RTL8367B_TA_CTRL_SPA_MASK 0x7
46 #define RTL8367B_TA_CTRL_METHOD BIT(4)/*GOOD*/
47 #define RTL8367B_TA_CTRL_CMD_SHIFT 3
48 #define RTL8367B_TA_CTRL_CMD_READ 0
49 #define RTL8367B_TA_CTRL_CMD_WRITE 1
50 #define RTL8367B_TA_CTRL_TABLE_SHIFT 0 /*GOOD*/
51 #define RTL8367B_TA_CTRL_TABLE_ACLRULE 1
52 #define RTL8367B_TA_CTRL_TABLE_ACLACT 2
53 #define RTL8367B_TA_CTRL_TABLE_CVLAN 3
54 #define RTL8367B_TA_CTRL_TABLE_L2 4
55 #define RTL8367B_TA_CTRL_CVLAN_READ \
56 ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \
57 RTL8367B_TA_CTRL_TABLE_CVLAN)
58 #define RTL8367B_TA_CTRL_CVLAN_WRITE \
59 ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \
60 RTL8367B_TA_CTRL_TABLE_CVLAN)
61
62 #define RTL8367B_TA_ADDR_REG 0x0501/*GOOD*/
63 #define RTL8367B_TA_ADDR_MASK 0x3fff/*GOOD*/
64
65 #define RTL8367B_TA_LUT_REG 0x0502/*GOOD*/
66
67 #define RTL8367B_TA_WRDATA_REG(_x) (0x0510 + (_x))/*GOOD*/
68 #define RTL8367B_TA_VLAN_NUM_WORDS 2
69 #define RTL8367B_TA_VLAN_VID_MASK RTL8367B_VID_MASK
70 #define RTL8367B_TA_VLAN0_MEMBER_SHIFT 0
71 #define RTL8367B_TA_VLAN0_MEMBER_MASK RTL8367B_MEMBER_MASK
72 #define RTL8367B_TA_VLAN0_UNTAG_SHIFT 8
73 #define RTL8367B_TA_VLAN0_UNTAG_MASK RTL8367B_MEMBER_MASK
74 #define RTL8367B_TA_VLAN1_FID_SHIFT 0
75 #define RTL8367B_TA_VLAN1_FID_MASK RTL8367B_FID_MASK
76
77 #define RTL8367B_TA_RDDATA_REG(_x) (0x0520 + (_x))/*GOOD*/
78
79 #define RTL8367B_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) /*GOOD*/
80 #define RTL8367B_VLAN_PVID_CTRL_MASK 0x1f /*GOOD*/
81 #define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) /*GOOD*/
82
83 #define RTL8367B_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) /*GOOD*/
84 #define RTL8367B_VLAN_MC_NUM_WORDS 4 /*GOOD*/
85 #define RTL8367B_VLAN_MC0_MEMBER_SHIFT 0/*GOOD*/
86 #define RTL8367B_VLAN_MC0_MEMBER_MASK RTL8367B_MEMBER_MASK/*GOOD*/
87 #define RTL8367B_VLAN_MC1_FID_SHIFT 0/*GOOD*/
88 #define RTL8367B_VLAN_MC1_FID_MASK RTL8367B_FID_MASK/*GOOD*/
89 #define RTL8367B_VLAN_MC3_EVID_SHIFT 0/*GOOD*/
90 #define RTL8367B_VLAN_MC3_EVID_MASK RTL8367B_VID_MASK/*GOOD*/
91
92 #define RTL8367B_VLAN_CTRL_REG 0x07a8 /*GOOD*/
93 #define RTL8367B_VLAN_CTRL_ENABLE BIT(0)
94
95 #define RTL8367B_VLAN_INGRESS_REG 0x07a9 /*GOOD*/
96
97 #define RTL8367B_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) /*GOOD*/
98
99 #define RTL8367B_MIB_COUNTER_REG(_x) (0x1000 + (_x)) /*GOOD*/
100 #define RTL8367B_MIB_COUNTER_PORT_OFFSET 0x007c /*GOOD*/
101
102 #define RTL8367B_MIB_ADDRESS_REG 0x1004 /*GOOD*/
103
104 #define RTL8367B_MIB_CTRL0_REG(_x) (0x1005 + (_x)) /*GOOD*/
105 #define RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK BIT(11) /*GOOD*/
106 #define RTL8367B_MIB_CTRL0_QM_RESET_MASK BIT(10) /*GOOD*/
107 #define RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/
108 #define RTL8367B_MIB_CTRL0_RESET_MASK BIT(1) /*GOOD*/
109 #define RTL8367B_MIB_CTRL0_BUSY_MASK BIT(0) /*GOOD*/
110
111 #define RTL8367B_SWC0_REG 0x1200/*GOOD*/
112 #define RTL8367B_SWC0_MAX_LENGTH_SHIFT 13/*GOOD*/
113 #define RTL8367B_SWC0_MAX_LENGTH(_x) ((_x) << 13) /*GOOD*/
114 #define RTL8367B_SWC0_MAX_LENGTH_MASK RTL8367B_SWC0_MAX_LENGTH(0x3)
115 #define RTL8367B_SWC0_MAX_LENGTH_1522 RTL8367B_SWC0_MAX_LENGTH(0)
116 #define RTL8367B_SWC0_MAX_LENGTH_1536 RTL8367B_SWC0_MAX_LENGTH(1)
117 #define RTL8367B_SWC0_MAX_LENGTH_1552 RTL8367B_SWC0_MAX_LENGTH(2)
118 #define RTL8367B_SWC0_MAX_LENGTH_16000 RTL8367B_SWC0_MAX_LENGTH(3)
119
120 #define RTL8367B_CHIP_NUMBER_REG 0x1300/*GOOD*/
121
122 #define RTL8367B_CHIP_VER_REG 0x1301/*GOOD*/
123 #define RTL8367B_CHIP_VER_RLVID_SHIFT 12/*GOOD*/
124 #define RTL8367B_CHIP_VER_RLVID_MASK 0xf/*GOOD*/
125 #define RTL8367B_CHIP_VER_MCID_SHIFT 8/*GOOD*/
126 #define RTL8367B_CHIP_VER_MCID_MASK 0xf/*GOOD*/
127 #define RTL8367B_CHIP_VER_BOID_SHIFT 4/*GOOD*/
128 #define RTL8367B_CHIP_VER_BOID_MASK 0xf/*GOOD*/
129 #define RTL8367B_CHIP_VER_AFE_SHIFT 0/*GOOD*/
130 #define RTL8367B_CHIP_VER_AFE_MASK 0x1/*GOOD*/
131
132 #define RTL8367B_CHIP_MODE_REG 0x1302
133 #define RTL8367B_CHIP_MODE_MASK 0x7
134
135 #define RTL8367B_CHIP_DEBUG0_REG 0x1303
136 #define RTL8367B_DEBUG0_SEL33(_x) BIT(8 + (_x))
137 #define RTL8367B_DEBUG0_DRI_OTHER BIT(7)
138 #define RTL8367B_DEBUG0_DRI_RG(_x) BIT(5 + (_x))
139 #define RTL8367B_DEBUG0_DRI(_x) BIT(3 + (_x))
140 #define RTL8367B_DEBUG0_SLR_OTHER BIT(2)
141 #define RTL8367B_DEBUG0_SLR(_x) BIT(_x)
142
143 #define RTL8367B_CHIP_DEBUG1_REG 0x1304
144 #define RTL8367B_DEBUG1_DN_MASK(_x) \
145 GENMASK(6 + (_x)*8, 4 + (_x)*8)
146 #define RTL8367B_DEBUG1_DN_SHIFT(_x) (4 + (_x) * 8)
147 #define RTL8367B_DEBUG1_DP_MASK(_x) \
148 GENMASK(2 + (_x) * 8, (_x) * 8)
149 #define RTL8367B_DEBUG1_DP_SHIFT(_x) ((_x) * 8)
150
151 #define RTL8367B_CHIP_DEBUG2_REG 0x13e2
152 #define RTL8367B_DEBUG2_RG2_DN_MASK GENMASK(8, 6)
153 #define RTL8367B_DEBUG2_RG2_DN_SHIFT 6
154 #define RTL8367B_DEBUG2_RG2_DP_MASK GENMASK(5, 3)
155 #define RTL8367B_DEBUG2_RG2_DP_SHIFT 3
156 #define RTL8367B_DEBUG2_DRI_EXT2_RG BIT(2)
157 #define RTL8367B_DEBUG2_DRI_EXT2 BIT(1)
158 #define RTL8367B_DEBUG2_SLR_EXT2 BIT(0)
159
160 #define RTL8367B_DIS_REG 0x1305
161 #define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
162 #define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x))
163 #define RTL8367B_DIS_RGMII_MASK 0x7
164
165 #define RTL8367B_DIS2_REG 0x13c3
166 #define RTL8367B_DIS2_SKIP_MII_RXER_SHIFT 4
167 #define RTL8367B_DIS2_SKIP_MII_RXER 0x10
168 #define RTL8367B_DIS2_RGMII_SHIFT 0
169 #define RTL8367B_DIS2_RGMII_MASK 0xf
170
171 #define RTL8367B_EXT_RGMXF_REG(_x) \
172 ((_x) == 2 ? 0x13c5 : 0x1306 + (_x))
173 #define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5
174 #define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff
175 #define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3
176 #define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1
177 #define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7
178
179 #define RTL8367B_DI_FORCE_REG(_x) \
180 ((_x) == 2 ? 0x13c4 : 0x1310 + (_x))
181 #define RTL8367B_DI_FORCE_MODE BIT(12)
182 #define RTL8367B_DI_FORCE_NWAY BIT(7)
183 #define RTL8367B_DI_FORCE_TXPAUSE BIT(6)
184 #define RTL8367B_DI_FORCE_RXPAUSE BIT(5)
185 #define RTL8367B_DI_FORCE_LINK BIT(4)
186 #define RTL8367B_DI_FORCE_DUPLEX BIT(2)
187 #define RTL8367B_DI_FORCE_SPEED_MASK 3
188 #define RTL8367B_DI_FORCE_SPEED_10 0
189 #define RTL8367B_DI_FORCE_SPEED_100 1
190 #define RTL8367B_DI_FORCE_SPEED_1000 2
191
192 #define RTL8367B_MAC_FORCE_REG(_x) (0x1312 + (_x))
193
194 #define RTL8367B_CHIP_RESET_REG 0x1322 /*GOOD*/
195 #define RTL8367B_CHIP_RESET_SW BIT(1) /*GOOD*/
196 #define RTL8367B_CHIP_RESET_HW BIT(0) /*GOOD*/
197
198 #define RTL8367B_PORT_STATUS_REG(_p) (0x1352 + (_p)) /*GOOD*/
199 #define RTL8367B_PORT_STATUS_EN_1000_SPI BIT(11) /*GOOD*/
200 #define RTL8367B_PORT_STATUS_EN_100_SPI BIT(10)/*GOOD*/
201 #define RTL8367B_PORT_STATUS_NWAY_FAULT BIT(9)/*GOOD*/
202 #define RTL8367B_PORT_STATUS_LINK_MASTER BIT(8)/*GOOD*/
203 #define RTL8367B_PORT_STATUS_NWAY BIT(7)/*GOOD*/
204 #define RTL8367B_PORT_STATUS_TXPAUSE BIT(6)/*GOOD*/
205 #define RTL8367B_PORT_STATUS_RXPAUSE BIT(5)/*GOOD*/
206 #define RTL8367B_PORT_STATUS_LINK BIT(4)/*GOOD*/
207 #define RTL8367B_PORT_STATUS_DUPLEX BIT(2)/*GOOD*/
208 #define RTL8367B_PORT_STATUS_SPEED_MASK 0x0003/*GOOD*/
209 #define RTL8367B_PORT_STATUS_SPEED_10 0/*GOOD*/
210 #define RTL8367B_PORT_STATUS_SPEED_100 1/*GOOD*/
211 #define RTL8367B_PORT_STATUS_SPEED_1000 2/*GOOD*/
212
213 #define RTL8367B_RTL_MAGIC_ID_REG 0x13c2
214 #define RTL8367B_RTL_MAGIC_ID_VAL 0x0249
215
216 #define RTL8367B_IA_CTRL_REG 0x1f00
217 #define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1)
218 #define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0)
219 #define RTL8367B_IA_CTRL_RW_WRITE RTL8367B_IA_CTRL_RW(1)
220 #define RTL8367B_IA_CTRL_CMD_MASK BIT(0)
221
222 #define RTL8367B_IA_STATUS_REG 0x1f01
223 #define RTL8367B_IA_STATUS_PHY_BUSY BIT(2)
224 #define RTL8367B_IA_STATUS_SDS_BUSY BIT(1)
225 #define RTL8367B_IA_STATUS_MDX_BUSY BIT(0)
226
227 #define RTL8367B_IA_ADDRESS_REG 0x1f02
228 #define RTL8367B_IA_WRITE_DATA_REG 0x1f03
229 #define RTL8367B_IA_READ_DATA_REG 0x1f04
230
231 #define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
232
233 #define RTL8367B_NUM_MIB_COUNTERS 58
234
235 #define RTL8367B_CPU_PORT_NUM 5
236 #define RTL8367B_NUM_PORTS 8
237 #define RTL8367B_NUM_VLANS 32
238 #define RTL8367B_NUM_VIDS 4096
239 #define RTL8367B_PRIORITYMAX 7
240 #define RTL8367B_FIDMAX 7
241
242 #define RTL8367B_PORT_0 BIT(0)
243 #define RTL8367B_PORT_1 BIT(1)
244 #define RTL8367B_PORT_2 BIT(2)
245 #define RTL8367B_PORT_3 BIT(3)
246 #define RTL8367B_PORT_4 BIT(4)
247 #define RTL8367B_PORT_E0 BIT(5) /* External port 0 */
248 #define RTL8367B_PORT_E1 BIT(6) /* External port 1 */
249 #define RTL8367B_PORT_E2 BIT(7) /* External port 2 */
250
251 #define RTL8367B_PORTS_ALL \
252 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
253 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
254 RTL8367B_PORT_E1 | RTL8367B_PORT_E2)
255
256 #define RTL8367B_PORTS_ALL_BUT_CPU \
257 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
258 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
259 RTL8367B_PORT_E2)
260
261 struct rtl8367b_initval {
262 u16 reg;
263 u16 val;
264 };
265
266 #define RTL8367B_MIB_RXB_ID 0 /* IfInOctets */
267 #define RTL8367B_MIB_TXB_ID 28 /* IfOutOctets */
268
269 static struct rtl8366_mib_counter
270 rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
271 {0, 0, 4, "ifInOctets" },
272 {0, 4, 2, "dot3StatsFCSErrors" },
273 {0, 6, 2, "dot3StatsSymbolErrors" },
274 {0, 8, 2, "dot3InPauseFrames" },
275 {0, 10, 2, "dot3ControlInUnknownOpcodes" },
276 {0, 12, 2, "etherStatsFragments" },
277 {0, 14, 2, "etherStatsJabbers" },
278 {0, 16, 2, "ifInUcastPkts" },
279 {0, 18, 2, "etherStatsDropEvents" },
280 {0, 20, 2, "ifInMulticastPkts" },
281 {0, 22, 2, "ifInBroadcastPkts" },
282 {0, 24, 2, "inMldChecksumError" },
283 {0, 26, 2, "inIgmpChecksumError" },
284 {0, 28, 2, "inMldSpecificQuery" },
285 {0, 30, 2, "inMldGeneralQuery" },
286 {0, 32, 2, "inIgmpSpecificQuery" },
287 {0, 34, 2, "inIgmpGeneralQuery" },
288 {0, 36, 2, "inMldLeaves" },
289 {0, 38, 2, "inIgmpLeaves" },
290
291 {0, 40, 4, "etherStatsOctets" },
292 {0, 44, 2, "etherStatsUnderSizePkts" },
293 {0, 46, 2, "etherOversizeStats" },
294 {0, 48, 2, "etherStatsPkts64Octets" },
295 {0, 50, 2, "etherStatsPkts65to127Octets" },
296 {0, 52, 2, "etherStatsPkts128to255Octets" },
297 {0, 54, 2, "etherStatsPkts256to511Octets" },
298 {0, 56, 2, "etherStatsPkts512to1023Octets" },
299 {0, 58, 2, "etherStatsPkts1024to1518Octets" },
300
301 {0, 60, 4, "ifOutOctets" },
302 {0, 64, 2, "dot3StatsSingleCollisionFrames" },
303 {0, 66, 2, "dot3StatMultipleCollisionFrames" },
304 {0, 68, 2, "dot3sDeferredTransmissions" },
305 {0, 70, 2, "dot3StatsLateCollisions" },
306 {0, 72, 2, "etherStatsCollisions" },
307 {0, 74, 2, "dot3StatsExcessiveCollisions" },
308 {0, 76, 2, "dot3OutPauseFrames" },
309 {0, 78, 2, "ifOutDiscards" },
310 {0, 80, 2, "dot1dTpPortInDiscards" },
311 {0, 82, 2, "ifOutUcastPkts" },
312 {0, 84, 2, "ifOutMulticastPkts" },
313 {0, 86, 2, "ifOutBroadcastPkts" },
314 {0, 88, 2, "outOampduPkts" },
315 {0, 90, 2, "inOampduPkts" },
316 {0, 92, 2, "inIgmpJoinsSuccess" },
317 {0, 94, 2, "inIgmpJoinsFail" },
318 {0, 96, 2, "inMldJoinsSuccess" },
319 {0, 98, 2, "inMldJoinsFail" },
320 {0, 100, 2, "inReportSuppressionDrop" },
321 {0, 102, 2, "inLeaveSuppressionDrop" },
322 {0, 104, 2, "outIgmpReports" },
323 {0, 106, 2, "outIgmpLeaves" },
324 {0, 108, 2, "outIgmpGeneralQuery" },
325 {0, 110, 2, "outIgmpSpecificQuery" },
326 {0, 112, 2, "outMldReports" },
327 {0, 114, 2, "outMldLeaves" },
328 {0, 116, 2, "outMldGeneralQuery" },
329 {0, 118, 2, "outMldSpecificQuery" },
330 {0, 120, 2, "inKnownMulticastPkts" },
331 };
332
333 #define REG_RD(_smi, _reg, _val) \
334 do { \
335 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
336 if (err) \
337 return err; \
338 } while (0)
339
340 #define REG_WR(_smi, _reg, _val) \
341 do { \
342 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
343 if (err) \
344 return err; \
345 } while (0)
346
347 #define REG_RMW(_smi, _reg, _mask, _val) \
348 do { \
349 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
350 if (err) \
351 return err; \
352 } while (0)
353
354 static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {
355 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
356 {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
357 {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
358 {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
359 {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
360 {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
361 {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
362 {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
363 {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
364 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
365 {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
366 {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
367 {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
368 {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
369 {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
370 {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
371 {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
372 {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
373 {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
374 {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
375 {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
376 {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
377 {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
378 {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
379 {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
380 {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
381 {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
382 {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
383 {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
384 {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
385 {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
386 {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
387 {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
388 {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
389 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
390 {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
391 {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
392 {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
393 {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
394 {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
395 {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
396 {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
397 {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
398 {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
399 {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
400 {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
401 {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
402 {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
403 {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
404 {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
405 {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
406 {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
407 {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
408 {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
409 {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
410 {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
411 {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
412 {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
413 {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
414 {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
415 {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
416 {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
417 {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
418 {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
419 {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
420 {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
421 {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
422 {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
423 {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
424 {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
425 {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
426 {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
427 {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
428 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
429 {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
430 {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
431 {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
432 {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
433 {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
434 {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
435 {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
436 {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
437 {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
438 {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
439 {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
440 {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
441 {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
442 {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
443 {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
444 {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
445 {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
446 {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
447 {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
448 {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
449 {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
450 {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
451 {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
452 {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
453 {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
454 {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
455 {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
456 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
457 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
458 {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
459 {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
460 {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
461 {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
462 {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
463 {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
464 {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
465 {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
466 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
467 {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
468 {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
469 {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
470 {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
471 {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
472 {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
473 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
474 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
475 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
476 {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
477 {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
478 {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
479 {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
480 {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
481 {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
482 {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
483 {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
484 {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
485 {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
486 {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
487 {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
488 {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
489 {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
490 {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
491 {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
492 {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
493 {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
494 {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
495 {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
496 {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
497 {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
498 {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
499 {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
500 {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
501 {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
502 {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
503 {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
504 {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
505 {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
506 {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
507 {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
508 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
509 {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
510 {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
511 {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
512 {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
513 {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
514 {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
515 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
516 {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
517 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
518 {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
519 {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
520 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
521 {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
522 {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
523 {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
524 {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
525 {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
526 {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
527 {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
528 {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
529 {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
530 {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
531 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
532 {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
533 {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
534 {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
535 {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
536 {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
537 {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
538 {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
539 {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
540 {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
541 {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
542 {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
543 {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
544 {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
545 {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
546 {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
547 {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
548 {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
549 {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
550 {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
551 {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
552 {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
553 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
554 {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
555 {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
556 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
557 {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
558 {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
559 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
560 {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
561 {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
562 {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
563 {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
564 {0x13EB, 0x11BB}
565 };
566
567 static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
568 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
569 {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
570 {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
571 {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
572 {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
573 {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
574 {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
575 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
576 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
577 {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
578 {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
579 {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
580 {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
581 {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
582 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
583 {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
584 {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
585 {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
586 {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
587 {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
588 {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
589 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
590 {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
591 {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
592 {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
593 {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
594 {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
595 {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
596 {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
597 {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
598 {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
599 {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
600 {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
601 {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
602 {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
603 {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
604 {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
605 {0x133E, 0x000E}, {0x133F, 0x0010},
606 };
607
608 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
609 const struct rtl8367b_initval *initvals,
610 int count)
611 {
612 int err;
613 int i;
614
615 for (i = 0; i < count; i++)
616 REG_WR(smi, initvals[i].reg, initvals[i].val);
617
618 return 0;
619 }
620
621 static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,
622 u32 phy_addr, u32 phy_reg, u32 *val)
623 {
624 int timeout;
625 u32 data;
626 int err;
627
628 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
629 return -EINVAL;
630
631 if (phy_reg > RTL8367B_PHY_REG_MAX)
632 return -EINVAL;
633
634 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
635 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
636 return -ETIMEDOUT;
637
638 /* prepare address */
639 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
640 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
641
642 /* send read command */
643 REG_WR(smi, RTL8367B_IA_CTRL_REG,
644 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);
645
646 timeout = 5;
647 do {
648 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
649 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
650 break;
651
652 if (timeout--) {
653 dev_err(smi->parent, "phy read timed out\n");
654 return -ETIMEDOUT;
655 }
656
657 udelay(1);
658 } while (1);
659
660 /* read data */
661 REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);
662
663 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
664 phy_addr, phy_reg, *val);
665 return 0;
666 }
667
668 static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
669 u32 phy_addr, u32 phy_reg, u32 val)
670 {
671 int timeout;
672 u32 data;
673 int err;
674
675 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
676 phy_addr, phy_reg, val);
677
678 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
679 return -EINVAL;
680
681 if (phy_reg > RTL8367B_PHY_REG_MAX)
682 return -EINVAL;
683
684 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
685 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
686 return -ETIMEDOUT;
687
688 /* preapre data */
689 REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);
690
691 /* prepare address */
692 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
693 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
694
695 /* send write command */
696 REG_WR(smi, RTL8367B_IA_CTRL_REG,
697 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);
698
699 timeout = 5;
700 do {
701 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
702 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
703 break;
704
705 if (timeout--) {
706 dev_err(smi->parent, "phy write timed out\n");
707 return -ETIMEDOUT;
708 }
709
710 udelay(1);
711 } while (1);
712
713 return 0;
714 }
715
716 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
717 {
718 const struct rtl8367b_initval *initvals;
719 u32 chip_ver;
720 u32 rlvid;
721 int count;
722 int err;
723
724 REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
725 REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
726
727 rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
728 RTL8367B_CHIP_VER_RLVID_MASK;
729
730 switch (rlvid) {
731 case 0:
732 initvals = rtl8367r_vb_initvals_0;
733 count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
734 break;
735
736 case 1:
737 initvals = rtl8367r_vb_initvals_1;
738 count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
739 break;
740
741 default:
742 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
743 return -ENODEV;
744 }
745
746 /* TODO: disable RLTP */
747
748 return rtl8367b_write_initvals(smi, initvals, count);
749 }
750
751 static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
752 {
753 int timeout = 10;
754 int err;
755 u32 data;
756
757 REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);
758 msleep(RTL8367B_RESET_DELAY);
759
760 do {
761 REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);
762 if (!(data & RTL8367B_CHIP_RESET_HW))
763 break;
764
765 msleep(1);
766 } while (--timeout);
767
768 if (!timeout) {
769 dev_err(smi->parent, "chip reset timed out\n");
770 return -ETIMEDOUT;
771 }
772
773 return 0;
774 }
775
776 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
777 enum rtl8367_extif_mode mode)
778 {
779 int err;
780
781 /* set port mode */
782 switch (mode) {
783 case RTL8367_EXTIF_MODE_RGMII:
784 case RTL8367_EXTIF_MODE_RGMII_33V:
785 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
786 RTL8367B_DEBUG0_SEL33(id),
787 RTL8367B_DEBUG0_SEL33(id));
788 if (id <= 1) {
789 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
790 RTL8367B_DEBUG0_DRI(id) |
791 RTL8367B_DEBUG0_DRI_RG(id) |
792 RTL8367B_DEBUG0_SLR(id),
793 RTL8367B_DEBUG0_DRI_RG(id) |
794 RTL8367B_DEBUG0_SLR(id));
795 REG_RMW(smi, RTL8367B_CHIP_DEBUG1_REG,
796 RTL8367B_DEBUG1_DN_MASK(id) |
797 RTL8367B_DEBUG1_DP_MASK(id),
798 (7 << RTL8367B_DEBUG1_DN_SHIFT(id)) |
799 (7 << RTL8367B_DEBUG1_DP_SHIFT(id)));
800 } else {
801 REG_RMW(smi, RTL8367B_CHIP_DEBUG1_REG,
802 RTL8367B_DEBUG2_DRI_EXT2 |
803 RTL8367B_DEBUG2_DRI_EXT2_RG |
804 RTL8367B_DEBUG2_SLR_EXT2 |
805 RTL8367B_DEBUG2_RG2_DN_MASK |
806 RTL8367B_DEBUG2_RG2_DP_MASK,
807 RTL8367B_DEBUG2_DRI_EXT2_RG |
808 RTL8367B_DEBUG2_SLR_EXT2 |
809 (7 << RTL8367B_DEBUG2_RG2_DN_SHIFT) |
810 (7 << RTL8367B_DEBUG2_RG2_DP_SHIFT));
811 }
812 break;
813
814 case RTL8367_EXTIF_MODE_TMII_MAC:
815 case RTL8367_EXTIF_MODE_TMII_PHY:
816 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
817 BIT((id + 1) % 2), BIT((id + 1) % 2));
818 break;
819
820 case RTL8367_EXTIF_MODE_GMII:
821 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
822 RTL8367B_DEBUG0_SEL33(id),
823 RTL8367B_DEBUG0_SEL33(id));
824 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
825 break;
826
827 case RTL8367_EXTIF_MODE_MII_MAC:
828 case RTL8367_EXTIF_MODE_MII_PHY:
829 case RTL8367_EXTIF_MODE_DISABLED:
830 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
831 BIT((id + 1) % 2), 0);
832 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
833 break;
834
835 default:
836 dev_err(smi->parent,
837 "invalid mode for external interface %d\n", id);
838 return -EINVAL;
839 }
840
841 if (id <= 1)
842 REG_RMW(smi, RTL8367B_DIS_REG,
843 RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
844 mode << RTL8367B_DIS_RGMII_SHIFT(id));
845 else
846 REG_RMW(smi, RTL8367B_DIS2_REG,
847 RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,
848 mode << RTL8367B_DIS2_RGMII_SHIFT);
849
850 return 0;
851 }
852
853 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
854 struct rtl8367_port_ability *pa)
855 {
856 u32 mask;
857 u32 val;
858 int err;
859
860 mask = (RTL8367B_DI_FORCE_MODE |
861 RTL8367B_DI_FORCE_NWAY |
862 RTL8367B_DI_FORCE_TXPAUSE |
863 RTL8367B_DI_FORCE_RXPAUSE |
864 RTL8367B_DI_FORCE_LINK |
865 RTL8367B_DI_FORCE_DUPLEX |
866 RTL8367B_DI_FORCE_SPEED_MASK);
867
868 val = pa->speed;
869 val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
870 val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
871 val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
872 val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
873 val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
874 val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
875
876 REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
877
878 return 0;
879 }
880
881 static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
882 unsigned txdelay, unsigned rxdelay)
883 {
884 u32 mask;
885 u32 val;
886 int err;
887
888 mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |
889 (RTL8367B_EXT_RGMXF_TXDELAY_MASK <<
890 RTL8367B_EXT_RGMXF_TXDELAY_SHIFT));
891
892 val = rxdelay;
893 val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;
894
895 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);
896
897 return 0;
898 }
899
900 static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
901 struct rtl8367_extif_config *cfg)
902 {
903 enum rtl8367_extif_mode mode;
904 int err;
905
906 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
907
908 err = rtl8367b_extif_set_mode(smi, id, mode);
909 if (err)
910 return err;
911
912 if (mode != RTL8367_EXTIF_MODE_DISABLED) {
913 err = rtl8367b_extif_set_force(smi, id, &cfg->ability);
914 if (err)
915 return err;
916
917 err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,
918 cfg->rxdelay);
919 if (err)
920 return err;
921 }
922
923 return 0;
924 }
925
926 #ifdef CONFIG_OF
927 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
928 const char *name)
929 {
930 struct rtl8367_extif_config *cfg;
931 const __be32 *prop;
932 int size;
933 int err;
934
935 prop = of_get_property(smi->parent->of_node, name, &size);
936 if (!prop)
937 return rtl8367b_extif_init(smi, id, NULL);
938
939 if (size != (9 * sizeof(*prop))) {
940 dev_err(smi->parent, "%s property is invalid\n", name);
941 return -EINVAL;
942 }
943
944 cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);
945 if (!cfg)
946 return -ENOMEM;
947
948 cfg->txdelay = be32_to_cpup(prop++);
949 cfg->rxdelay = be32_to_cpup(prop++);
950 cfg->mode = be32_to_cpup(prop++);
951 cfg->ability.force_mode = be32_to_cpup(prop++);
952 cfg->ability.txpause = be32_to_cpup(prop++);
953 cfg->ability.rxpause = be32_to_cpup(prop++);
954 cfg->ability.link = be32_to_cpup(prop++);
955 cfg->ability.duplex = be32_to_cpup(prop++);
956 cfg->ability.speed = be32_to_cpup(prop++);
957
958 err = rtl8367b_extif_init(smi, id, cfg);
959 kfree(cfg);
960
961 return err;
962 }
963 #else
964 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
965 const char *name)
966 {
967 return -EINVAL;
968 }
969 #endif
970
971 static int rtl8367b_setup(struct rtl8366_smi *smi)
972 {
973 struct rtl8367_platform_data *pdata;
974 int err;
975 int i;
976
977 pdata = smi->parent->platform_data;
978
979 err = rtl8367b_init_regs(smi);
980 if (err)
981 return err;
982
983 /* initialize external interfaces */
984 if (smi->parent->of_node) {
985 err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
986 if (err)
987 return err;
988
989 err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
990 if (err)
991 return err;
992
993 err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2");
994 if (err)
995 return err;
996 } else {
997 err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
998 if (err)
999 return err;
1000
1001 err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
1002 if (err)
1003 return err;
1004 }
1005
1006 /* set maximum packet length to 1536 bytes */
1007 REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,
1008 RTL8367B_SWC0_MAX_LENGTH_1536);
1009
1010 /*
1011 * discard VLAN tagged packets if the port is not a member of
1012 * the VLAN with which the packets is associated.
1013 */
1014 REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);
1015
1016 /*
1017 * Setup egress tag mode for each port.
1018 */
1019 for (i = 0; i < RTL8367B_NUM_PORTS; i++)
1020 REG_RMW(smi,
1021 RTL8367B_PORT_MISC_CFG_REG(i),
1022 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<
1023 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,
1024 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<
1025 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);
1026
1027 return 0;
1028 }
1029
1030 static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,
1031 int port, unsigned long long *val)
1032 {
1033 struct rtl8366_mib_counter *mib;
1034 int offset;
1035 int i;
1036 int err;
1037 u32 addr, data;
1038 u64 mibvalue;
1039
1040 if (port > RTL8367B_NUM_PORTS ||
1041 counter >= RTL8367B_NUM_MIB_COUNTERS)
1042 return -EINVAL;
1043
1044 mib = &rtl8367b_mib_counters[counter];
1045 addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
1046
1047 /*
1048 * Writing access counter address first
1049 * then ASIC will prepare 64bits counter wait for being retrived
1050 */
1051 REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);
1052
1053 /* read MIB control register */
1054 REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);
1055
1056 if (data & RTL8367B_MIB_CTRL0_BUSY_MASK)
1057 return -EBUSY;
1058
1059 if (data & RTL8367B_MIB_CTRL0_RESET_MASK)
1060 return -EIO;
1061
1062 if (mib->length == 4)
1063 offset = 3;
1064 else
1065 offset = (mib->offset + 1) % 4;
1066
1067 mibvalue = 0;
1068 for (i = 0; i < mib->length; i++) {
1069 REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);
1070 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1071 }
1072
1073 *val = mibvalue;
1074 return 0;
1075 }
1076
1077 static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
1078 struct rtl8366_vlan_4k *vlan4k)
1079 {
1080 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1081 int err;
1082 int i;
1083
1084 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1085
1086 if (vid >= RTL8367B_NUM_VIDS)
1087 return -EINVAL;
1088
1089 /* write VID */
1090 REG_WR(smi, RTL8367B_TA_ADDR_REG, vid);
1091
1092 /* write table access control word */
1093 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);
1094
1095 for (i = 0; i < ARRAY_SIZE(data); i++)
1096 REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);
1097
1098 vlan4k->vid = vid;
1099 vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &
1100 RTL8367B_TA_VLAN0_MEMBER_MASK;
1101 vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
1102 RTL8367B_TA_VLAN0_UNTAG_MASK;
1103 vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
1104 RTL8367B_TA_VLAN1_FID_MASK;
1105
1106 return 0;
1107 }
1108
1109 static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
1110 const struct rtl8366_vlan_4k *vlan4k)
1111 {
1112 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1113 int err;
1114 int i;
1115
1116 if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
1117 vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
1118 vlan4k->untag > RTL8367B_UNTAG_MASK ||
1119 vlan4k->fid > RTL8367B_FIDMAX)
1120 return -EINVAL;
1121
1122 memset(data, 0, sizeof(data));
1123
1124 data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<
1125 RTL8367B_TA_VLAN0_MEMBER_SHIFT;
1126 data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
1127 RTL8367B_TA_VLAN0_UNTAG_SHIFT;
1128 data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
1129 RTL8367B_TA_VLAN1_FID_SHIFT;
1130
1131 for (i = 0; i < ARRAY_SIZE(data); i++)
1132 REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
1133
1134 /* write VID */
1135 REG_WR(smi, RTL8367B_TA_ADDR_REG,
1136 vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
1137
1138 /* write table access control word */
1139 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
1140
1141 return 0;
1142 }
1143
1144 static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1145 struct rtl8366_vlan_mc *vlanmc)
1146 {
1147 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1148 int err;
1149 int i;
1150
1151 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1152
1153 if (index >= RTL8367B_NUM_VLANS)
1154 return -EINVAL;
1155
1156 for (i = 0; i < ARRAY_SIZE(data); i++)
1157 REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
1158
1159 vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &
1160 RTL8367B_VLAN_MC0_MEMBER_MASK;
1161 vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &
1162 RTL8367B_VLAN_MC1_FID_MASK;
1163 vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &
1164 RTL8367B_VLAN_MC3_EVID_MASK;
1165
1166 return 0;
1167 }
1168
1169 static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1170 const struct rtl8366_vlan_mc *vlanmc)
1171 {
1172 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1173 int err;
1174 int i;
1175
1176 if (index >= RTL8367B_NUM_VLANS ||
1177 vlanmc->vid >= RTL8367B_NUM_VIDS ||
1178 vlanmc->priority > RTL8367B_PRIORITYMAX ||
1179 vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
1180 vlanmc->untag > RTL8367B_UNTAG_MASK ||
1181 vlanmc->fid > RTL8367B_FIDMAX)
1182 return -EINVAL;
1183
1184 data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
1185 RTL8367B_VLAN_MC0_MEMBER_SHIFT;
1186 data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
1187 RTL8367B_VLAN_MC1_FID_SHIFT;
1188 data[2] = 0;
1189 data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<
1190 RTL8367B_VLAN_MC3_EVID_SHIFT;
1191
1192 for (i = 0; i < ARRAY_SIZE(data); i++)
1193 REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);
1194
1195 return 0;
1196 }
1197
1198 static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1199 {
1200 u32 data;
1201 int err;
1202
1203 if (port >= RTL8367B_NUM_PORTS)
1204 return -EINVAL;
1205
1206 REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
1207
1208 *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
1209 RTL8367B_VLAN_PVID_CTRL_MASK;
1210
1211 return 0;
1212 }
1213
1214 static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1215 {
1216 if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
1217 return -EINVAL;
1218
1219 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
1220 RTL8367B_VLAN_PVID_CTRL_MASK <<
1221 RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
1222 (index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
1223 RTL8367B_VLAN_PVID_CTRL_SHIFT(port));
1224 }
1225
1226 static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)
1227 {
1228 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,
1229 RTL8367B_VLAN_CTRL_ENABLE,
1230 (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);
1231 }
1232
1233 static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1234 {
1235 return 0;
1236 }
1237
1238 static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1239 {
1240 unsigned max = RTL8367B_NUM_VLANS;
1241
1242 if (smi->vlan4k_enabled)
1243 max = RTL8367B_NUM_VIDS - 1;
1244
1245 if (vlan == 0 || vlan >= max)
1246 return 0;
1247
1248 return 1;
1249 }
1250
1251 static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)
1252 {
1253 int err;
1254
1255 REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),
1256 (enable) ? RTL8367B_PORTS_ALL : 0);
1257
1258 return 0;
1259 }
1260
1261 static int rtl8367b_sw_reset_mibs(struct switch_dev *dev,
1262 const struct switch_attr *attr,
1263 struct switch_val *val)
1264 {
1265 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1266
1267 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,
1268 RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);
1269 }
1270
1271 static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
1272 int port,
1273 struct switch_port_link *link)
1274 {
1275 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1276 u32 data = 0;
1277 u32 speed;
1278
1279 if (port >= RTL8367B_NUM_PORTS)
1280 return -EINVAL;
1281
1282 rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
1283
1284 link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
1285 if (!link->link)
1286 return 0;
1287
1288 link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);
1289 link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);
1290 link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
1291 link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
1292
1293 speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
1294 switch (speed) {
1295 case 0:
1296 link->speed = SWITCH_PORT_SPEED_10;
1297 break;
1298 case 1:
1299 link->speed = SWITCH_PORT_SPEED_100;
1300 break;
1301 case 2:
1302 link->speed = SWITCH_PORT_SPEED_1000;
1303 break;
1304 default:
1305 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1306 break;
1307 }
1308
1309 return 0;
1310 }
1311
1312 static int rtl8367b_sw_get_max_length(struct switch_dev *dev,
1313 const struct switch_attr *attr,
1314 struct switch_val *val)
1315 {
1316 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1317 u32 data;
1318
1319 rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);
1320 val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>
1321 RTL8367B_SWC0_MAX_LENGTH_SHIFT;
1322
1323 return 0;
1324 }
1325
1326 static int rtl8367b_sw_set_max_length(struct switch_dev *dev,
1327 const struct switch_attr *attr,
1328 struct switch_val *val)
1329 {
1330 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1331 u32 max_len;
1332
1333 switch (val->value.i) {
1334 case 0:
1335 max_len = RTL8367B_SWC0_MAX_LENGTH_1522;
1336 break;
1337 case 1:
1338 max_len = RTL8367B_SWC0_MAX_LENGTH_1536;
1339 break;
1340 case 2:
1341 max_len = RTL8367B_SWC0_MAX_LENGTH_1552;
1342 break;
1343 case 3:
1344 max_len = RTL8367B_SWC0_MAX_LENGTH_16000;
1345 break;
1346 default:
1347 return -EINVAL;
1348 }
1349
1350 return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,
1351 RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
1352 }
1353
1354
1355 static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
1356 const struct switch_attr *attr,
1357 struct switch_val *val)
1358 {
1359 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1360 int port;
1361
1362 port = val->port_vlan;
1363 if (port >= RTL8367B_NUM_PORTS)
1364 return -EINVAL;
1365
1366 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,
1367 RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));
1368 }
1369
1370 static int rtl8367b_sw_get_port_stats(struct switch_dev *dev, int port,
1371 struct switch_port_stats *stats)
1372 {
1373 return (rtl8366_sw_get_port_stats(dev, port, stats,
1374 RTL8367B_MIB_TXB_ID, RTL8367B_MIB_RXB_ID));
1375 }
1376
1377 static struct switch_attr rtl8367b_globals[] = {
1378 {
1379 .type = SWITCH_TYPE_INT,
1380 .name = "enable_vlan",
1381 .description = "Enable VLAN mode",
1382 .set = rtl8366_sw_set_vlan_enable,
1383 .get = rtl8366_sw_get_vlan_enable,
1384 .max = 1,
1385 .ofs = 1
1386 }, {
1387 .type = SWITCH_TYPE_INT,
1388 .name = "enable_vlan4k",
1389 .description = "Enable VLAN 4K mode",
1390 .set = rtl8366_sw_set_vlan_enable,
1391 .get = rtl8366_sw_get_vlan_enable,
1392 .max = 1,
1393 .ofs = 2
1394 }, {
1395 .type = SWITCH_TYPE_NOVAL,
1396 .name = "reset_mibs",
1397 .description = "Reset all MIB counters",
1398 .set = rtl8367b_sw_reset_mibs,
1399 }, {
1400 .type = SWITCH_TYPE_INT,
1401 .name = "max_length",
1402 .description = "Get/Set the maximum length of valid packets"
1403 "(0:1522, 1:1536, 2:1552, 3:16000)",
1404 .set = rtl8367b_sw_set_max_length,
1405 .get = rtl8367b_sw_get_max_length,
1406 .max = 3,
1407 }
1408 };
1409
1410 static struct switch_attr rtl8367b_port[] = {
1411 {
1412 .type = SWITCH_TYPE_NOVAL,
1413 .name = "reset_mib",
1414 .description = "Reset single port MIB counters",
1415 .set = rtl8367b_sw_reset_port_mibs,
1416 }, {
1417 .type = SWITCH_TYPE_STRING,
1418 .name = "mib",
1419 .description = "Get MIB counters for port",
1420 .max = 33,
1421 .set = NULL,
1422 .get = rtl8366_sw_get_port_mib,
1423 },
1424 };
1425
1426 static struct switch_attr rtl8367b_vlan[] = {
1427 {
1428 .type = SWITCH_TYPE_STRING,
1429 .name = "info",
1430 .description = "Get vlan information",
1431 .max = 1,
1432 .set = NULL,
1433 .get = rtl8366_sw_get_vlan_info,
1434 },
1435 };
1436
1437 static const struct switch_dev_ops rtl8367b_sw_ops = {
1438 .attr_global = {
1439 .attr = rtl8367b_globals,
1440 .n_attr = ARRAY_SIZE(rtl8367b_globals),
1441 },
1442 .attr_port = {
1443 .attr = rtl8367b_port,
1444 .n_attr = ARRAY_SIZE(rtl8367b_port),
1445 },
1446 .attr_vlan = {
1447 .attr = rtl8367b_vlan,
1448 .n_attr = ARRAY_SIZE(rtl8367b_vlan),
1449 },
1450
1451 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1452 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1453 .get_port_pvid = rtl8366_sw_get_port_pvid,
1454 .set_port_pvid = rtl8366_sw_set_port_pvid,
1455 .reset_switch = rtl8366_sw_reset_switch,
1456 .get_port_link = rtl8367b_sw_get_port_link,
1457 .get_port_stats = rtl8367b_sw_get_port_stats,
1458 };
1459
1460 static int rtl8367b_switch_init(struct rtl8366_smi *smi)
1461 {
1462 struct switch_dev *dev = &smi->sw_dev;
1463 int err;
1464
1465 dev->name = "RTL8367B";
1466 dev->cpu_port = smi->cpu_port;
1467 dev->ports = RTL8367B_NUM_PORTS;
1468 dev->vlans = RTL8367B_NUM_VIDS;
1469 dev->ops = &rtl8367b_sw_ops;
1470 dev->alias = dev_name(smi->parent);
1471
1472 err = register_switch(dev, NULL);
1473 if (err)
1474 dev_err(smi->parent, "switch registration failed\n");
1475
1476 return err;
1477 }
1478
1479 static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)
1480 {
1481 unregister_switch(&smi->sw_dev);
1482 }
1483
1484 static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)
1485 {
1486 struct rtl8366_smi *smi = bus->priv;
1487 u32 val = 0;
1488 int err;
1489
1490 err = rtl8367b_read_phy_reg(smi, addr, reg, &val);
1491 if (err)
1492 return 0xffff;
1493
1494 return val;
1495 }
1496
1497 static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1498 {
1499 struct rtl8366_smi *smi = bus->priv;
1500 u32 t;
1501 int err;
1502
1503 err = rtl8367b_write_phy_reg(smi, addr, reg, val);
1504 if (err)
1505 return err;
1506
1507 /* flush write */
1508 (void) rtl8367b_read_phy_reg(smi, addr, reg, &t);
1509
1510 return err;
1511 }
1512
1513 static int rtl8367b_detect(struct rtl8366_smi *smi)
1514 {
1515 const char *chip_name;
1516 u32 chip_num;
1517 u32 chip_ver;
1518 u32 chip_mode;
1519 int ret;
1520
1521 /* TODO: improve chip detection */
1522 rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
1523 RTL8367B_RTL_MAGIC_ID_VAL);
1524
1525 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
1526 if (ret) {
1527 dev_err(smi->parent, "unable to read %s register\n",
1528 "chip number");
1529 return ret;
1530 }
1531
1532 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
1533 if (ret) {
1534 dev_err(smi->parent, "unable to read %s register\n",
1535 "chip version");
1536 return ret;
1537 }
1538
1539 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);
1540 if (ret) {
1541 dev_err(smi->parent, "unable to read %s register\n",
1542 "chip mode");
1543 return ret;
1544 }
1545
1546 switch (chip_ver) {
1547 case 0x1000:
1548 chip_name = "8367RB";
1549 break;
1550 case 0x1010:
1551 chip_name = "8367R-VB";
1552 break;
1553 default:
1554 dev_err(smi->parent,
1555 "unknown chip num:%04x ver:%04x, mode:%04x\n",
1556 chip_num, chip_ver, chip_mode);
1557 return -ENODEV;
1558 }
1559
1560 dev_info(smi->parent, "RTL%s chip found\n", chip_name);
1561
1562 return 0;
1563 }
1564
1565 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
1566 .detect = rtl8367b_detect,
1567 .reset_chip = rtl8367b_reset_chip,
1568 .setup = rtl8367b_setup,
1569
1570 .mii_read = rtl8367b_mii_read,
1571 .mii_write = rtl8367b_mii_write,
1572
1573 .get_vlan_mc = rtl8367b_get_vlan_mc,
1574 .set_vlan_mc = rtl8367b_set_vlan_mc,
1575 .get_vlan_4k = rtl8367b_get_vlan_4k,
1576 .set_vlan_4k = rtl8367b_set_vlan_4k,
1577 .get_mc_index = rtl8367b_get_mc_index,
1578 .set_mc_index = rtl8367b_set_mc_index,
1579 .get_mib_counter = rtl8367b_get_mib_counter,
1580 .is_vlan_valid = rtl8367b_is_vlan_valid,
1581 .enable_vlan = rtl8367b_enable_vlan,
1582 .enable_vlan4k = rtl8367b_enable_vlan4k,
1583 .enable_port = rtl8367b_enable_port,
1584 };
1585
1586 static int rtl8367b_probe(struct platform_device *pdev)
1587 {
1588 struct rtl8366_smi *smi;
1589 int err;
1590
1591 smi = rtl8366_smi_probe(pdev);
1592 if (IS_ERR(smi))
1593 return PTR_ERR(smi);
1594
1595 smi->clk_delay = 1500;
1596 smi->cmd_read = 0xb9;
1597 smi->cmd_write = 0xb8;
1598 smi->ops = &rtl8367b_smi_ops;
1599 smi->num_ports = RTL8367B_NUM_PORTS;
1600 if (of_property_read_u32(pdev->dev.of_node, "cpu_port", &smi->cpu_port)
1601 || smi->cpu_port >= smi->num_ports)
1602 smi->cpu_port = RTL8367B_CPU_PORT_NUM;
1603 smi->num_vlan_mc = RTL8367B_NUM_VLANS;
1604 smi->mib_counters = rtl8367b_mib_counters;
1605 smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
1606
1607 err = rtl8366_smi_init(smi);
1608 if (err)
1609 goto err_free_smi;
1610
1611 platform_set_drvdata(pdev, smi);
1612
1613 err = rtl8367b_switch_init(smi);
1614 if (err)
1615 goto err_clear_drvdata;
1616
1617 return 0;
1618
1619 err_clear_drvdata:
1620 platform_set_drvdata(pdev, NULL);
1621 rtl8366_smi_cleanup(smi);
1622 err_free_smi:
1623 kfree(smi);
1624 return err;
1625 }
1626
1627 static int rtl8367b_remove(struct platform_device *pdev)
1628 {
1629 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1630
1631 if (smi) {
1632 rtl8367b_switch_cleanup(smi);
1633 platform_set_drvdata(pdev, NULL);
1634 rtl8366_smi_cleanup(smi);
1635 kfree(smi);
1636 }
1637
1638 return 0;
1639 }
1640
1641 static void rtl8367b_shutdown(struct platform_device *pdev)
1642 {
1643 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1644
1645 if (smi)
1646 rtl8367b_reset_chip(smi);
1647 }
1648
1649 #ifdef CONFIG_OF
1650 static const struct of_device_id rtl8367b_match[] = {
1651 { .compatible = "realtek,rtl8367b" },
1652 {},
1653 };
1654 MODULE_DEVICE_TABLE(of, rtl8367b_match);
1655 #endif
1656
1657 static struct platform_driver rtl8367b_driver = {
1658 .driver = {
1659 .name = RTL8367B_DRIVER_NAME,
1660 .owner = THIS_MODULE,
1661 #ifdef CONFIG_OF
1662 .of_match_table = of_match_ptr(rtl8367b_match),
1663 #endif
1664 },
1665 .probe = rtl8367b_probe,
1666 .remove = rtl8367b_remove,
1667 .shutdown = rtl8367b_shutdown,
1668 };
1669
1670 module_platform_driver(rtl8367b_driver);
1671
1672 MODULE_DESCRIPTION("Realtek RTL8367B ethernet switch driver");
1673 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1674 MODULE_LICENSE("GPL v2");
1675 MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
1676