target/linux/generic/patches-3.12/774-bgmac-add-some-workaround-for-rev-4.patch

   1 From ec12b94d22fa8715561bdffe6da0781dac08423e Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Sun, 10 Nov 2013 21:23:57 +0100
   4 Subject: [PATCH] bgmac: add some workaround for rev 4
   5
   6 ---
   7  drivers/net/ethernet/broadcom/bgmac.c |    8 ++++----
   8  drivers/net/ethernet/broadcom/bgmac.h |    4 +++-
   9  2 files changed, 7 insertions(+), 5 deletions(-)
  10
  11 --- a/drivers/net/ethernet/broadcom/bgmac.c
  12 +++ b/drivers/net/ethernet/broadcom/bgmac.c
  13 @@ -97,6 +97,16 @@ static void bgmac_dma_tx_enable(struct b
  14         u32 ctl;
  15
  16         ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
  17 +       if (bgmac->core->id.rev == 4) {
  18 +               ctl &= ~BGMAC_DMA_TX_BL_MASK;
  19 +               ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
  20 +               ctl &= ~BGMAC_DMA_TX_MR_MASK;
  21 +               ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
  22 +               ctl &= ~BGMAC_DMA_TX_PC_MASK;
  23 +               ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
  24 +               ctl &= ~BGMAC_DMA_TX_PT_MASK;
  25 +               ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
  26 +       }
  27         ctl |= BGMAC_DMA_TX_ENABLE;
  28         ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
  29         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
  30 @@ -246,6 +256,17 @@ static void bgmac_dma_rx_enable(struct b
  31         ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
  32         ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
  33         ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
  34 +
  35 +       if (bgmac->core->id.rev == 4) {
  36 +               ctl &= ~BGMAC_DMA_RX_BL_MASK;
  37 +               ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
  38 +
  39 +               ctl &= ~BGMAC_DMA_RX_PC_MASK;
  40 +               ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
  41 +
  42 +               ctl &= ~BGMAC_DMA_RX_PT_MASK;
  43 +               ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
  44 +       }
  45         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
  46  }
  47
  48 @@ -812,13 +833,13 @@ static void bgmac_cmdcfg_maskset(struct
  49         u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  50         u32 new_val = (cmdcfg & mask) | set;
  51
  52 -       bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
  53 +       bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
  54         udelay(2);
  55
  56         if (new_val != cmdcfg || force)
  57                 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
  58
  59 -       bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
  60 +       bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
  61         udelay(2);
  62  }
  63
  64 @@ -1029,7 +1050,7 @@ static void bgmac_chip_reset(struct bgma
  65                              BGMAC_CMDCFG_PROM |
  66                              BGMAC_CMDCFG_NLC |
  67                              BGMAC_CMDCFG_CFE |
  68 -                            BGMAC_CMDCFG_SR,
  69 +                            BGMAC_CMDCFG_SR(core->id.rev),
  70                              false);
  71
  72         bgmac_clear_mib(bgmac);
  73 @@ -1070,7 +1091,7 @@ static void bgmac_enable(struct bgmac *b
  74
  75         cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  76         bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
  77 -                            BGMAC_CMDCFG_SR, true);
  78 +                            BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
  79         udelay(2);
  80         cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
  81         bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
  82 --- a/drivers/net/ethernet/broadcom/bgmac.h
  83 +++ b/drivers/net/ethernet/broadcom/bgmac.h
  84 @@ -194,7 +194,9 @@
  85  #define  BGMAC_CMDCFG_TAI                      0x00000200
  86  #define  BGMAC_CMDCFG_HD                       0x00000400      /* Set if in half duplex mode */
  87  #define  BGMAC_CMDCFG_HD_SHIFT                 10
  88 -#define  BGMAC_CMDCFG_SR                       0x00000800      /* Set to reset mode */
  89 +#define  BGMAC_CMDCFG_SR_REVO                  0x00000800      /* Set to reset mode, for other revs */
  90 +#define  BGMAC_CMDCFG_SR_REV4                  0x00002000      /* Set to reset mode, only for core rev 4 */
  91 +#define  BGMAC_CMDCFG_SR(rev)  ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REVO)
  92  #define  BGMAC_CMDCFG_ML                       0x00008000      /* Set to activate mac loopback mode */
  93  #define  BGMAC_CMDCFG_AE                       0x00400000
  94  #define  BGMAC_CMDCFG_CFE                      0x00800000
  95 @@ -255,9 +257,34 @@
  96  #define  BGMAC_DMA_TX_SUSPEND                  0x00000002
  97  #define  BGMAC_DMA_TX_LOOPBACK                 0x00000004
  98  #define  BGMAC_DMA_TX_FLUSH                    0x00000010
  99 +#define  BGMAC_DMA_TX_MR_MASK                  0x000000C0      /* Multiple outstanding reads */
 100 +#define  BGMAC_DMA_TX_MR_SHIFT                 6
 101 +#define   BGMAC_DMA_TX_MR_1                    0
 102 +#define   BGMAC_DMA_TX_MR_2                    1
 103  #define  BGMAC_DMA_TX_PARITY_DISABLE           0x00000800
 104  #define  BGMAC_DMA_TX_ADDREXT_MASK             0x00030000
 105  #define  BGMAC_DMA_TX_ADDREXT_SHIFT            16
 106 +#define  BGMAC_DMA_TX_BL_MASK                  0x001C0000      /* BurstLen bits */
 107 +#define  BGMAC_DMA_TX_BL_SHIFT                 18
 108 +#define   BGMAC_DMA_TX_BL_16                   0
 109 +#define   BGMAC_DMA_TX_BL_32                   1
 110 +#define   BGMAC_DMA_TX_BL_64                   2
 111 +#define   BGMAC_DMA_TX_BL_128                  3
 112 +#define   BGMAC_DMA_TX_BL_256                  4
 113 +#define   BGMAC_DMA_TX_BL_512                  5
 114 +#define   BGMAC_DMA_TX_BL_1024                 6
 115 +#define  BGMAC_DMA_TX_PC_MASK                  0x00E00000      /* Prefetch control */
 116 +#define  BGMAC_DMA_TX_PC_SHIFT                 21
 117 +#define   BGMAC_DMA_TX_PC_0                    0
 118 +#define   BGMAC_DMA_TX_PC_4                    1
 119 +#define   BGMAC_DMA_TX_PC_8                    2
 120 +#define   BGMAC_DMA_TX_PC_16                   3
 121 +#define  BGMAC_DMA_TX_PT_MASK                  0x03000000      /* Prefetch threshold */
 122 +#define  BGMAC_DMA_TX_PT_SHIFT                 24
 123 +#define   BGMAC_DMA_TX_PT_1                    0
 124 +#define   BGMAC_DMA_TX_PT_2                    1
 125 +#define   BGMAC_DMA_TX_PT_4                    2
 126 +#define   BGMAC_DMA_TX_PT_8                    3
 127  #define BGMAC_DMA_TX_INDEX                     0x04
 128  #define BGMAC_DMA_TX_RINGLO                    0x08
 129  #define BGMAC_DMA_TX_RINGHI                    0x0C
 130 @@ -285,8 +312,33 @@
 131  #define  BGMAC_DMA_RX_DIRECT_FIFO              0x00000100
 132  #define  BGMAC_DMA_RX_OVERFLOW_CONT            0x00000400
 133  #define  BGMAC_DMA_RX_PARITY_DISABLE           0x00000800
 134 +#define  BGMAC_DMA_RX_MR_MASK                  0x000000C0      /* Multiple outstanding reads */
 135 +#define  BGMAC_DMA_RX_MR_SHIFT                 6
 136 +#define   BGMAC_DMA_TX_MR_1                    0
 137 +#define   BGMAC_DMA_TX_MR_2                    1
 138  #define  BGMAC_DMA_RX_ADDREXT_MASK             0x00030000
 139  #define  BGMAC_DMA_RX_ADDREXT_SHIFT            16
 140 +#define  BGMAC_DMA_RX_BL_MASK                  0x001C0000      /* BurstLen bits */
 141 +#define  BGMAC_DMA_RX_BL_SHIFT                 18
 142 +#define   BGMAC_DMA_RX_BL_16                   0
 143 +#define   BGMAC_DMA_RX_BL_32                   1
 144 +#define   BGMAC_DMA_RX_BL_64                   2
 145 +#define   BGMAC_DMA_RX_BL_128                  3
 146 +#define   BGMAC_DMA_RX_BL_256                  4
 147 +#define   BGMAC_DMA_RX_BL_512                  5
 148 +#define   BGMAC_DMA_RX_BL_1024                 6
 149 +#define  BGMAC_DMA_RX_PC_MASK                  0x00E00000      /* Prefetch control */
 150 +#define  BGMAC_DMA_RX_PC_SHIFT                 21
 151 +#define   BGMAC_DMA_RX_PC_0                    0
 152 +#define   BGMAC_DMA_RX_PC_4                    1
 153 +#define   BGMAC_DMA_RX_PC_8                    2
 154 +#define   BGMAC_DMA_RX_PC_16                   3
 155 +#define  BGMAC_DMA_RX_PT_MASK                  0x03000000      /* Prefetch threshold */
 156 +#define  BGMAC_DMA_RX_PT_SHIFT                 24
 157 +#define   BGMAC_DMA_RX_PT_1                    0
 158 +#define   BGMAC_DMA_RX_PT_2                    1
 159 +#define   BGMAC_DMA_RX_PT_4                    2
 160 +#define   BGMAC_DMA_RX_PT_8                    3
 161  #define BGMAC_DMA_RX_INDEX                     0x24
 162  #define BGMAC_DMA_RX_RINGLO                    0x28
 163  #define BGMAC_DMA_RX_RINGHI                    0x2C