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7ba44cb4e77986508bf1e74c9a60575488864a6a
[openwrt/openwrt.git] / target / linux / generic / patches-4.1 / 025-bcma-from-4.6.patch
1 --- a/drivers/bcma/driver_chipcommon.c
2 +++ b/drivers/bcma/driver_chipcommon.c
3 @@ -185,7 +185,7 @@ u32 bcma_chipco_watchdog_timer_set(struc
4 ticks = 2;
5 else if (ticks > maxt)
6 ticks = maxt;
7 - bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
8 + bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
9 } else {
10 struct bcma_bus *bus = cc->core->bus;
11
12 --- a/drivers/bcma/driver_chipcommon_pmu.c
13 +++ b/drivers/bcma/driver_chipcommon_pmu.c
14 @@ -15,44 +15,44 @@
15
16 u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
17 {
18 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
19 - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
20 - return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
21 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
22 + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
23 + return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
24 }
25 EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
26
27 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
28 {
29 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
30 - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
31 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
32 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
33 + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
34 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
35 }
36 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
37
38 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
39 u32 set)
40 {
41 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
42 - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
43 - bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
44 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
45 + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
46 + bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
47 }
48 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
49
50 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
51 u32 offset, u32 mask, u32 set)
52 {
53 - bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
54 - bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
55 - bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
56 + bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
57 + bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
58 + bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
59 }
60 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
61
62 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
63 u32 set)
64 {
65 - bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
66 - bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
67 - bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
68 + bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
69 + bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
70 + bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
71 }
72 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
73
74 @@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma
75 {
76 u32 ilp_ctl, alp_hz;
77
78 - if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
79 + if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
80 BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
81 return 0;
82
83 - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
84 - BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
85 + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
86 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
87 usleep_range(1000, 2000);
88
89 - ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
90 + ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
91 ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
92
93 - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
94 + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
95
96 alp_hz = ilp_ctl * 32768 / 4;
97 return (alp_hz + 50000) / 100000 * 100;
98 @@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b
99 mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
100 BCMA_RES_4314_MACPHY_CLK_AVAIL);
101
102 - bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
103 - bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
104 + bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
105 + bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
106 bcma_wait_value(cc->core, BCMA_CLKCTLST,
107 BCMA_CLKCTLST_HAVEHT, 0, 20000);
108 break;
109 @@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b
110
111 /* Flush */
112 if (cc->pmu.rev >= 2)
113 - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
114 + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
115
116 /* TODO: Do we need to update OTP? */
117 }
118 @@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru
119
120 /* Set the resource masks. */
121 if (min_msk)
122 - bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
123 + bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
124 if (max_msk)
125 - bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
126 + bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
127
128 /*
129 * Add some delay; allow resources to come up and settle.
130 @@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct
131
132 void bcma_pmu_early_init(struct bcma_drv_cc *cc)
133 {
134 + struct bcma_bus *bus = cc->core->bus;
135 u32 pmucap;
136
137 - pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
138 + if (cc->core->id.rev >= 35 &&
139 + cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
140 + cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
141 + if (!cc->pmu.core)
142 + bcma_warn(bus, "Couldn't find expected PMU core");
143 + }
144 + if (!cc->pmu.core)
145 + cc->pmu.core = cc->core;
146 +
147 + pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
148 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
149
150 - bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
151 - cc->pmu.rev, pmucap);
152 + bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
153 + pmucap);
154 }
155
156 void bcma_pmu_init(struct bcma_drv_cc *cc)
157 {
158 if (cc->pmu.rev == 1)
159 - bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
160 - ~BCMA_CC_PMU_CTL_NOILPONW);
161 + bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
162 + ~BCMA_CC_PMU_CTL_NOILPONW);
163 else
164 - bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
165 - BCMA_CC_PMU_CTL_NOILPONW);
166 + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
167 + BCMA_CC_PMU_CTL_NOILPONW);
168
169 bcma_pmu_pll_init(cc);
170 bcma_pmu_resources_init(cc);
171 @@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d
172 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
173 u32 value)
174 {
175 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
176 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
177 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
178 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
179 }
180
181 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
182 @@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct
183 bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
184
185 /* RMW only the P1 divider */
186 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
187 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
188 BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
189 - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
190 + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
191 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
192 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
193 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
194 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
195
196 /* RMW only the int feedback divider */
197 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
198 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
199 BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
200 - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
201 + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
202 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
203 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
204 - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
205 + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
206
207 tmp = BCMA_CC_PMU_CTL_PLL_UPD;
208 break;
209 @@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
210 break;
211 }
212
213 - tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
214 - bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
215 + tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
216 + bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
217 }
218 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
219 --- a/drivers/bcma/driver_chipcommon_sflash.c
220 +++ b/drivers/bcma/driver_chipcommon_sflash.c
221 @@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc
222 { "M25P32", 0x15, 0x10000, 64, },
223 { "M25P64", 0x16, 0x10000, 128, },
224 { "M25FL128", 0x17, 0x10000, 256, },
225 + { "MX25L25635F", 0x18, 0x10000, 512, },
226 { NULL },
227 };
228
229 --- a/drivers/bcma/scan.c
230 +++ b/drivers/bcma/scan.c
231 @@ -98,6 +98,9 @@ static const struct bcma_device_id_name
232 { BCMA_CORE_SHIM, "SHIM" },
233 { BCMA_CORE_PCIE2, "PCIe Gen2" },
234 { BCMA_CORE_ARM_CR4, "ARM CR4" },
235 + { BCMA_CORE_GCI, "GCI" },
236 + { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
237 + { BCMA_CORE_ARM_CA7, "ARM CA7" },
238 { BCMA_CORE_DEFAULT, "Default" },
239 };
240
241 @@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm
242 switch (core->id.id) {
243 case BCMA_CORE_4706_MAC_GBIT_COMMON:
244 case BCMA_CORE_NS_CHIPCOMMON_B:
245 + case BCMA_CORE_PMU:
246 + case BCMA_CORE_GCI:
247 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
248 break;
249 default:
250 --- a/drivers/net/wireless/b43/main.c
251 +++ b/drivers/net/wireless/b43/main.c
252 @@ -1215,10 +1215,10 @@ void b43_wireless_core_phy_pll_reset(str
253 case B43_BUS_BCMA:
254 bcma_cc = &dev->dev->bdev->bus->drv_cc;
255
256 - bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
257 - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
258 - bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
259 - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
260 + bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
261 + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
262 + bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
263 + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
264 break;
265 #endif
266 #ifdef CONFIG_B43_SSB
267 --- a/include/linux/bcma/bcma.h
268 +++ b/include/linux/bcma/bcma.h
269 @@ -151,6 +151,8 @@ struct bcma_host_ops {
270 #define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
271 #define BCMA_CORE_USB30_DEV 0x83D
272 #define BCMA_CORE_ARM_CR4 0x83E
273 +#define BCMA_CORE_GCI 0x840
274 +#define BCMA_CORE_CMEM 0x846 /* CNDS DDR2/3 memory controller */
275 #define BCMA_CORE_ARM_CA7 0x847
276 #define BCMA_CORE_SYS_MEM 0x849
277 #define BCMA_CORE_DEFAULT 0xFFF
278 --- a/include/linux/bcma/bcma_driver_chipcommon.h
279 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
280 @@ -217,6 +217,11 @@
281 #define BCMA_CC_CLKDIV_JTAG_SHIFT 8
282 #define BCMA_CC_CLKDIV_UART 0x000000FF
283 #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
284 +#define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001
285 +#define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002
286 +#define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004
287 +#define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */
288 +#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
289 #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
290 #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
291 #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
292 @@ -351,12 +356,12 @@
293 #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
294 #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
295 #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
296 -#define BCMA_CC_CHIPCTL_ADDR 0x0650
297 -#define BCMA_CC_CHIPCTL_DATA 0x0654
298 -#define BCMA_CC_REGCTL_ADDR 0x0658
299 -#define BCMA_CC_REGCTL_DATA 0x065C
300 -#define BCMA_CC_PLLCTL_ADDR 0x0660
301 -#define BCMA_CC_PLLCTL_DATA 0x0664
302 +#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
303 +#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
304 +#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
305 +#define BCMA_CC_PMU_REGCTL_DATA 0x065C
306 +#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
307 +#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
308 #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
309 #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
310 #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
311 @@ -566,6 +571,7 @@
312 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
313 */
314 struct bcma_chipcommon_pmu {
315 + struct bcma_device *core; /* Can be separated core or just ChipCommon one */
316 u8 rev; /* PMU revision */
317 u32 crystalfreq; /* The active crystal frequency (in kHz) */
318 };
319 @@ -663,6 +669,19 @@ struct bcma_drv_cc_b {
320 #define bcma_cc_maskset32(cc, offset, mask, set) \
321 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
322
323 +/* PMU registers access */
324 +#define bcma_pmu_read32(cc, offset) \
325 + bcma_read32((cc)->pmu.core, offset)
326 +#define bcma_pmu_write32(cc, offset, val) \
327 + bcma_write32((cc)->pmu.core, offset, val)
328 +
329 +#define bcma_pmu_mask32(cc, offset, mask) \
330 + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
331 +#define bcma_pmu_set32(cc, offset, set) \
332 + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
333 +#define bcma_pmu_maskset32(cc, offset, mask, set) \
334 + bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
335 +
336 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
337
338 extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
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