b64070658711433e75b98152a6622f7dc80b10f3
[openwrt/openwrt.git] / target / linux / generic / patches-4.1 / 090-m25p80_spi-nor_update_to_4.4rc1.patch
1 --- a/drivers/mtd/devices/m25p80.c
2 +++ b/drivers/mtd/devices/m25p80.c
3 @@ -31,7 +31,6 @@
4 struct m25p {
5 struct spi_device *spi;
6 struct spi_nor spi_nor;
7 - struct mtd_info mtd;
8 u8 command[MAX_CMD_SIZE];
9 };
10
11 @@ -62,8 +61,7 @@ static int m25p_cmdsz(struct spi_nor *no
12 return 1 + nor->addr_width;
13 }
14
15 -static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
16 - int wr_en)
17 +static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
18 {
19 struct m25p *flash = nor->priv;
20 struct spi_device *spi = flash->spi;
21 @@ -159,7 +157,7 @@ static int m25p80_erase(struct spi_nor *
22 struct m25p *flash = nor->priv;
23
24 dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
25 - flash->mtd.erasesize / 1024, (u32)offset);
26 + flash->spi_nor.mtd.erasesize / 1024, (u32)offset);
27
28 /* Set up command buffer. */
29 flash->command[0] = nor->erase_opcode;
30 @@ -201,11 +199,10 @@ static int m25p_probe(struct spi_device
31 nor->read_reg = m25p80_read_reg;
32
33 nor->dev = &spi->dev;
34 - nor->mtd = &flash->mtd;
35 + nor->flash_node = spi->dev.of_node;
36 nor->priv = flash;
37
38 spi_set_drvdata(spi, flash);
39 - flash->mtd.priv = nor;
40 flash->spi = spi;
41
42 if (spi->mode & SPI_RX_QUAD)
43 @@ -214,7 +211,7 @@ static int m25p_probe(struct spi_device
44 mode = SPI_NOR_DUAL;
45
46 if (data && data->name)
47 - flash->mtd.name = data->name;
48 + nor->mtd.name = data->name;
49
50 /* For some (historical?) reason many platforms provide two different
51 * names in flash_platform_data: "name" and "type". Quite often name is
52 @@ -223,8 +220,6 @@ static int m25p_probe(struct spi_device
53 */
54 if (data && data->type)
55 flash_name = data->type;
56 - else if (!strcmp(spi->modalias, "spi-nor"))
57 - flash_name = NULL; /* auto-detect */
58 else
59 flash_name = spi->modalias;
60
61 @@ -234,7 +229,7 @@ static int m25p_probe(struct spi_device
62
63 ppdata.of_node = spi->dev.of_node;
64
65 - return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
66 + return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
67 data ? data->parts : NULL,
68 data ? data->nr_parts : 0);
69 }
70 @@ -245,7 +240,7 @@ static int m25p_remove(struct spi_device
71 struct m25p *flash = spi_get_drvdata(spi);
72
73 /* Clean up MTD stuff. */
74 - return mtd_device_unregister(&flash->mtd);
75 + return mtd_device_unregister(&flash->spi_nor.mtd);
76 }
77
78 /*
79 @@ -261,59 +256,52 @@ static int m25p_remove(struct spi_device
80 * keep them available as module aliases for existing platforms.
81 */
82 static const struct spi_device_id m25p_ids[] = {
83 - {"at25fs010"}, {"at25fs040"}, {"at25df041a"}, {"at25df321a"},
84 - {"at25df641"}, {"at26f004"}, {"at26df081a"}, {"at26df161a"},
85 - {"at26df321"}, {"at45db081d"},
86 - {"en25f32"}, {"en25p32"}, {"en25q32b"}, {"en25p64"},
87 - {"en25q64"}, {"en25qh128"}, {"en25qh256"},
88 - {"f25l32pa"},
89 - {"mr25h256"}, {"mr25h10"},
90 - {"gd25q32"}, {"gd25q64"},
91 - {"160s33b"}, {"320s33b"}, {"640s33b"},
92 - {"mx25l2005a"}, {"mx25l4005a"}, {"mx25l8005"}, {"mx25l1606e"},
93 - {"mx25l3205d"}, {"mx25l3255e"}, {"mx25l6405d"}, {"mx25l12805d"},
94 - {"mx25l12855e"},{"mx25l25635e"},{"mx25l25655e"},{"mx66l51235l"},
95 - {"mx66l1g55g"},
96 - {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q256a"},
97 - {"n25q512a"}, {"n25q512ax3"}, {"n25q00"},
98 - {"pm25lv512"}, {"pm25lv010"}, {"pm25lq032"},
99 - {"s25sl032p"}, {"s25sl064p"}, {"s25fl256s0"}, {"s25fl256s1"},
100 - {"s25fl512s"}, {"s70fl01gs"}, {"s25sl12800"}, {"s25sl12801"},
101 - {"s25fl129p0"}, {"s25fl129p1"}, {"s25sl004a"}, {"s25sl008a"},
102 - {"s25sl016a"}, {"s25sl032a"}, {"s25sl064a"}, {"s25fl008k"},
103 - {"s25fl016k"}, {"s25fl064k"}, {"s25fl132k"},
104 - {"sst25vf040b"},{"sst25vf080b"},{"sst25vf016b"},{"sst25vf032b"},
105 - {"sst25vf064c"},{"sst25wf512"}, {"sst25wf010"}, {"sst25wf020"},
106 - {"sst25wf040"},
107 - {"m25p05"}, {"m25p10"}, {"m25p20"}, {"m25p40"},
108 - {"m25p80"}, {"m25p16"}, {"m25p32"}, {"m25p64"},
109 - {"m25p128"}, {"n25q032"},
110 + /*
111 + * Entries not used in DTs that should be safe to drop after replacing
112 + * them with "nor-jedec" in platform data.
113 + */
114 + {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
115 +
116 + /*
117 + * Entries that were used in DTs without "nor-jedec" fallback and should
118 + * be kept for backward compatibility.
119 + */
120 + {"at25df321a"}, {"at25df641"}, {"at26df081a"},
121 + {"mr25h256"},
122 + {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
123 + {"mx25l25635e"},{"mx66l51235l"},
124 + {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
125 + {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
126 + {"s25fl064k"},
127 + {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
128 + {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
129 + {"m25p64"}, {"m25p128"},
130 + {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
131 + {"w25q80bl"}, {"w25q128"}, {"w25q256"},
132 +
133 + /* Flashes that can't be detected using JEDEC */
134 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
135 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
136 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
137 - {"m45pe10"}, {"m45pe80"}, {"m45pe16"},
138 - {"m25pe20"}, {"m25pe80"}, {"m25pe16"},
139 - {"m25px16"}, {"m25px32"}, {"m25px32-s0"}, {"m25px32-s1"},
140 - {"m25px64"}, {"m25px80"},
141 - {"w25x10"}, {"w25x20"}, {"w25x40"}, {"w25x80"},
142 - {"w25x16"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
143 - {"w25x64"}, {"w25q64"}, {"w25q80"}, {"w25q80bl"},
144 - {"w25q128"}, {"w25q256"}, {"cat25c11"},
145 - {"cat25c03"}, {"cat25c09"}, {"cat25c17"}, {"cat25128"},
146
147 - /*
148 - * Generic support for SPI NOR that can be identified by the JEDEC READ
149 - * ID opcode (0x9F). Use this, if possible.
150 - */
151 - {"spi-nor"},
152 { },
153 };
154 MODULE_DEVICE_TABLE(spi, m25p_ids);
155
156 +static const struct of_device_id m25p_of_table[] = {
157 + /*
158 + * Generic compatibility for SPI NOR that can be identified by the
159 + * JEDEC READ ID opcode (0x9F). Use this, if possible.
160 + */
161 + { .compatible = "jedec,spi-nor" },
162 + {}
163 +};
164 +MODULE_DEVICE_TABLE(of, m25p_of_table);
165 +
166 static struct spi_driver m25p80_driver = {
167 .driver = {
168 .name = "m25p80",
169 - .owner = THIS_MODULE,
170 + .of_match_table = m25p_of_table,
171 },
172 .id_table = m25p_ids,
173 .probe = m25p_probe,
174 --- a/drivers/mtd/spi-nor/spi-nor.c
175 +++ b/drivers/mtd/spi-nor/spi-nor.c
176 @@ -16,19 +16,32 @@
177 #include <linux/device.h>
178 #include <linux/mutex.h>
179 #include <linux/math64.h>
180 +#include <linux/sizes.h>
181
182 -#include <linux/mtd/cfi.h>
183 #include <linux/mtd/mtd.h>
184 #include <linux/of_platform.h>
185 #include <linux/spi/flash.h>
186 #include <linux/mtd/spi-nor.h>
187
188 /* Define max times to check status register before we give up. */
189 -#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
190 +
191 +/*
192 + * For everything but full-chip erase; probably could be much smaller, but kept
193 + * around for safety for now
194 + */
195 +#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
196 +
197 +/*
198 + * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
199 + * for larger flash
200 + */
201 +#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
202
203 #define SPI_NOR_MAX_ID_LEN 6
204
205 struct flash_info {
206 + char *name;
207 +
208 /*
209 * This array stores the ID bytes.
210 * The first three bytes are the JEDIC ID.
211 @@ -59,7 +72,7 @@ struct flash_info {
212
213 #define JEDEC_MFR(info) ((info)->id[0])
214
215 -static const struct spi_device_id *spi_nor_match_id(const char *name);
216 +static const struct flash_info *spi_nor_match_id(const char *name);
217
218 /*
219 * Read the status register, returning its value in the location
220 @@ -143,7 +156,7 @@ static inline int spi_nor_read_dummy_cyc
221 static inline int write_sr(struct spi_nor *nor, u8 val)
222 {
223 nor->cmd_buf[0] = val;
224 - return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
225 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
226 }
227
228 /*
229 @@ -152,7 +165,7 @@ static inline int write_sr(struct spi_no
230 */
231 static inline int write_enable(struct spi_nor *nor)
232 {
233 - return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
234 + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
235 }
236
237 /*
238 @@ -160,7 +173,7 @@ static inline int write_enable(struct sp
239 */
240 static inline int write_disable(struct spi_nor *nor)
241 {
242 - return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
243 + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
244 }
245
246 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
247 @@ -169,7 +182,7 @@ static inline struct spi_nor *mtd_to_spi
248 }
249
250 /* Enable/disable 4-byte addressing mode. */
251 -static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
252 +static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
253 int enable)
254 {
255 int status;
256 @@ -177,16 +190,16 @@ static inline int set_4byte(struct spi_n
257 u8 cmd;
258
259 switch (JEDEC_MFR(info)) {
260 - case CFI_MFR_ST: /* Micron, actually */
261 + case SNOR_MFR_MICRON:
262 /* Some Micron need WREN command; all will accept it */
263 need_wren = true;
264 - case CFI_MFR_MACRONIX:
265 - case 0xEF /* winbond */:
266 + case SNOR_MFR_MACRONIX:
267 + case SNOR_MFR_WINBOND:
268 if (need_wren)
269 write_enable(nor);
270
271 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
272 - status = nor->write_reg(nor, cmd, NULL, 0, 0);
273 + status = nor->write_reg(nor, cmd, NULL, 0);
274 if (need_wren)
275 write_disable(nor);
276
277 @@ -194,7 +207,7 @@ static inline int set_4byte(struct spi_n
278 default:
279 /* Spansion style */
280 nor->cmd_buf[0] = enable << 7;
281 - return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
282 + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
283 }
284 }
285 static inline int spi_nor_sr_ready(struct spi_nor *nor)
286 @@ -231,12 +244,13 @@ static int spi_nor_ready(struct spi_nor
287 * Service routine to read status register until ready, or timeout occurs.
288 * Returns non-zero if error.
289 */
290 -static int spi_nor_wait_till_ready(struct spi_nor *nor)
291 +static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
292 + unsigned long timeout_jiffies)
293 {
294 unsigned long deadline;
295 int timeout = 0, ret;
296
297 - deadline = jiffies + MAX_READY_WAIT_JIFFIES;
298 + deadline = jiffies + timeout_jiffies;
299
300 while (!timeout) {
301 if (time_after_eq(jiffies, deadline))
302 @@ -256,6 +270,12 @@ static int spi_nor_wait_till_ready(struc
303 return -ETIMEDOUT;
304 }
305
306 +static int spi_nor_wait_till_ready(struct spi_nor *nor)
307 +{
308 + return spi_nor_wait_till_ready_with_timeout(nor,
309 + DEFAULT_READY_WAIT_JIFFIES);
310 +}
311 +
312 /*
313 * Erase the whole flash memory
314 *
315 @@ -263,9 +283,9 @@ static int spi_nor_wait_till_ready(struc
316 */
317 static int erase_chip(struct spi_nor *nor)
318 {
319 - dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
320 + dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
321
322 - return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
323 + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
324 }
325
326 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
327 @@ -319,6 +339,8 @@ static int spi_nor_erase(struct mtd_info
328
329 /* whole-chip erase? */
330 if (len == mtd->size) {
331 + unsigned long timeout;
332 +
333 write_enable(nor);
334
335 if (erase_chip(nor)) {
336 @@ -326,7 +348,16 @@ static int spi_nor_erase(struct mtd_info
337 goto erase_err;
338 }
339
340 - ret = spi_nor_wait_till_ready(nor);
341 + /*
342 + * Scale the timeout linearly with the size of the flash, with
343 + * a minimum calibrated to an old 2MB flash. We could try to
344 + * pull these from CFI/SFDP, but these values should be good
345 + * enough for now.
346 + */
347 + timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
348 + CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
349 + (unsigned long)(mtd->size / SZ_2M));
350 + ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
351 if (ret)
352 goto erase_err;
353
354 @@ -369,72 +400,171 @@ erase_err:
355 return ret;
356 }
357
358 +static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
359 + uint64_t *len)
360 +{
361 + struct mtd_info *mtd = &nor->mtd;
362 + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
363 + int shift = ffs(mask) - 1;
364 + int pow;
365 +
366 + if (!(sr & mask)) {
367 + /* No protection */
368 + *ofs = 0;
369 + *len = 0;
370 + } else {
371 + pow = ((sr & mask) ^ mask) >> shift;
372 + *len = mtd->size >> pow;
373 + *ofs = mtd->size - *len;
374 + }
375 +}
376 +
377 +/*
378 + * Return 1 if the entire region is locked, 0 otherwise
379 + */
380 +static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
381 + u8 sr)
382 +{
383 + loff_t lock_offs;
384 + uint64_t lock_len;
385 +
386 + stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
387 +
388 + return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
389 +}
390 +
391 +/*
392 + * Lock a region of the flash. Compatible with ST Micro and similar flash.
393 + * Supports only the block protection bits BP{0,1,2} in the status register
394 + * (SR). Does not support these features found in newer SR bitfields:
395 + * - TB: top/bottom protect - only handle TB=0 (top protect)
396 + * - SEC: sector/block protect - only handle SEC=0 (block protect)
397 + * - CMP: complement protect - only support CMP=0 (range is not complemented)
398 + *
399 + * Sample table portion for 8MB flash (Winbond w25q64fw):
400 + *
401 + * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
402 + * --------------------------------------------------------------------------
403 + * X | X | 0 | 0 | 0 | NONE | NONE
404 + * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
405 + * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
406 + * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
407 + * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
408 + * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
409 + * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
410 + * X | X | 1 | 1 | 1 | 8 MB | ALL
411 + *
412 + * Returns negative on errors, 0 on success.
413 + */
414 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
415 {
416 - struct mtd_info *mtd = nor->mtd;
417 - uint32_t offset = ofs;
418 - uint8_t status_old, status_new;
419 - int ret = 0;
420 + struct mtd_info *mtd = &nor->mtd;
421 + u8 status_old, status_new;
422 + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
423 + u8 shift = ffs(mask) - 1, pow, val;
424
425 status_old = read_sr(nor);
426
427 - if (offset < mtd->size - (mtd->size / 2))
428 - status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
429 - else if (offset < mtd->size - (mtd->size / 4))
430 - status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
431 - else if (offset < mtd->size - (mtd->size / 8))
432 - status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
433 - else if (offset < mtd->size - (mtd->size / 16))
434 - status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
435 - else if (offset < mtd->size - (mtd->size / 32))
436 - status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
437 - else if (offset < mtd->size - (mtd->size / 64))
438 - status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
439 - else
440 - status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
441 + /* SPI NOR always locks to the end */
442 + if (ofs + len != mtd->size) {
443 + /* Does combined region extend to end? */
444 + if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
445 + status_old))
446 + return -EINVAL;
447 + len = mtd->size - ofs;
448 + }
449 +
450 + /*
451 + * Need smallest pow such that:
452 + *
453 + * 1 / (2^pow) <= (len / size)
454 + *
455 + * so (assuming power-of-2 size) we do:
456 + *
457 + * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
458 + */
459 + pow = ilog2(mtd->size) - ilog2(len);
460 + val = mask - (pow << shift);
461 + if (val & ~mask)
462 + return -EINVAL;
463 + /* Don't "lock" with no region! */
464 + if (!(val & mask))
465 + return -EINVAL;
466 +
467 + status_new = (status_old & ~mask) | val;
468
469 /* Only modify protection if it will not unlock other areas */
470 - if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
471 - (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
472 - write_enable(nor);
473 - ret = write_sr(nor, status_new);
474 - }
475 + if ((status_new & mask) <= (status_old & mask))
476 + return -EINVAL;
477
478 - return ret;
479 + write_enable(nor);
480 + return write_sr(nor, status_new);
481 }
482
483 +/*
484 + * Unlock a region of the flash. See stm_lock() for more info
485 + *
486 + * Returns negative on errors, 0 on success.
487 + */
488 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
489 {
490 - struct mtd_info *mtd = nor->mtd;
491 - uint32_t offset = ofs;
492 + struct mtd_info *mtd = &nor->mtd;
493 uint8_t status_old, status_new;
494 - int ret = 0;
495 + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
496 + u8 shift = ffs(mask) - 1, pow, val;
497
498 status_old = read_sr(nor);
499
500 - if (offset+len > mtd->size - (mtd->size / 64))
501 - status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
502 - else if (offset+len > mtd->size - (mtd->size / 32))
503 - status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
504 - else if (offset+len > mtd->size - (mtd->size / 16))
505 - status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
506 - else if (offset+len > mtd->size - (mtd->size / 8))
507 - status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
508 - else if (offset+len > mtd->size - (mtd->size / 4))
509 - status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
510 - else if (offset+len > mtd->size - (mtd->size / 2))
511 - status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
512 - else
513 - status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
514 + /* Cannot unlock; would unlock larger region than requested */
515 + if (stm_is_locked_sr(nor, status_old, ofs - mtd->erasesize,
516 + mtd->erasesize))
517 + return -EINVAL;
518
519 - /* Only modify protection if it will not lock other areas */
520 - if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
521 - (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
522 - write_enable(nor);
523 - ret = write_sr(nor, status_new);
524 + /*
525 + * Need largest pow such that:
526 + *
527 + * 1 / (2^pow) >= (len / size)
528 + *
529 + * so (assuming power-of-2 size) we do:
530 + *
531 + * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
532 + */
533 + pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
534 + if (ofs + len == mtd->size) {
535 + val = 0; /* fully unlocked */
536 + } else {
537 + val = mask - (pow << shift);
538 + /* Some power-of-two sizes are not supported */
539 + if (val & ~mask)
540 + return -EINVAL;
541 }
542
543 - return ret;
544 + status_new = (status_old & ~mask) | val;
545 +
546 + /* Only modify protection if it will not lock other areas */
547 + if ((status_new & mask) >= (status_old & mask))
548 + return -EINVAL;
549 +
550 + write_enable(nor);
551 + return write_sr(nor, status_new);
552 +}
553 +
554 +/*
555 + * Check if a region of the flash is (completely) locked. See stm_lock() for
556 + * more info.
557 + *
558 + * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
559 + * negative on errors.
560 + */
561 +static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
562 +{
563 + int status;
564 +
565 + status = read_sr(nor);
566 + if (status < 0)
567 + return status;
568 +
569 + return stm_is_locked_sr(nor, ofs, len, status);
570 }
571
572 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
573 @@ -467,9 +597,23 @@ static int spi_nor_unlock(struct mtd_inf
574 return ret;
575 }
576
577 +static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
578 +{
579 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
580 + int ret;
581 +
582 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
583 + if (ret)
584 + return ret;
585 +
586 + ret = nor->flash_is_locked(nor, ofs, len);
587 +
588 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
589 + return ret;
590 +}
591 +
592 /* Used when the "_ext_id" is two bytes at most */
593 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
594 - ((kernel_ulong_t)&(struct flash_info) { \
595 .id = { \
596 ((_jedec_id) >> 16) & 0xff, \
597 ((_jedec_id) >> 8) & 0xff, \
598 @@ -481,11 +625,9 @@ static int spi_nor_unlock(struct mtd_inf
599 .sector_size = (_sector_size), \
600 .n_sectors = (_n_sectors), \
601 .page_size = 256, \
602 - .flags = (_flags), \
603 - })
604 + .flags = (_flags),
605
606 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
607 - ((kernel_ulong_t)&(struct flash_info) { \
608 .id = { \
609 ((_jedec_id) >> 16) & 0xff, \
610 ((_jedec_id) >> 8) & 0xff, \
611 @@ -498,23 +640,27 @@ static int spi_nor_unlock(struct mtd_inf
612 .sector_size = (_sector_size), \
613 .n_sectors = (_n_sectors), \
614 .page_size = 256, \
615 - .flags = (_flags), \
616 - })
617 + .flags = (_flags),
618
619 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
620 - ((kernel_ulong_t)&(struct flash_info) { \
621 .sector_size = (_sector_size), \
622 .n_sectors = (_n_sectors), \
623 .page_size = (_page_size), \
624 .addr_width = (_addr_width), \
625 - .flags = (_flags), \
626 - })
627 + .flags = (_flags),
628
629 /* NOTE: double check command sets and memory organization when you add
630 * more nor chips. This current list focusses on newer chips, which
631 * have been converging on command sets which including JEDEC ID.
632 + *
633 + * All newly added entries should describe *hardware* and should use SECT_4K
634 + * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
635 + * scenarios excluding small sectors there is config option that can be
636 + * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
637 + * For historical (and compatibility) reasons (before we got above config) some
638 + * old entries may be missing 4K flag.
639 */
640 -static const struct spi_device_id spi_nor_ids[] = {
641 +static const struct flash_info spi_nor_ids[] = {
642 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
643 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
644 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
645 @@ -538,7 +684,7 @@ static const struct spi_device_id spi_no
646 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
647 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
648 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
649 - { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, 0) },
650 + { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
651
652 /* ESMT */
653 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
654 @@ -560,7 +706,11 @@ static const struct spi_device_id spi_no
655 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
656 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
657
658 + /* ISSI */
659 + { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
660 +
661 /* Macronix */
662 + { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
663 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
664 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
665 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
666 @@ -578,7 +728,9 @@ static const struct spi_device_id spi_no
667
668 /* Micron */
669 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
670 - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) },
671 + { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
672 + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
673 + { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
674 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
675 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
676 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
677 @@ -595,25 +747,28 @@ static const struct spi_device_id spi_no
678 * for the chips listed here (without boot sectors).
679 */
680 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
681 - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
682 + { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
683 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
684 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
685 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
686 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
687 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
688 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
689 - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
690 - { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
691 - { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
692 + { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
693 + { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
694 + { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
695 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
696 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
697 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
698 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
699 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
700 - { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
701 - { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
702 + { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
703 + { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
704 + { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
705 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
706 - { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) },
707 + { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
708 + { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
709 + { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
710
711 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
712 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
713 @@ -624,6 +779,8 @@ static const struct spi_device_id spi_no
714 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
715 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
716 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
717 + { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
718 + { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
719 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
720 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
721
722 @@ -672,10 +829,11 @@ static const struct spi_device_id spi_no
723 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
724 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
725 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
726 - { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
727 + { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
728 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
729 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
730 - { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) },
731 + { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
732 + { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
733 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
734 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
735 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
736 @@ -690,11 +848,11 @@ static const struct spi_device_id spi_no
737 { },
738 };
739
740 -static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
741 +static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
742 {
743 int tmp;
744 u8 id[SPI_NOR_MAX_ID_LEN];
745 - struct flash_info *info;
746 + const struct flash_info *info;
747
748 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
749 if (tmp < 0) {
750 @@ -703,7 +861,7 @@ static const struct spi_device_id *spi_n
751 }
752
753 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
754 - info = (void *)spi_nor_ids[tmp].driver_data;
755 + info = &spi_nor_ids[tmp];
756 if (info->id_len) {
757 if (!memcmp(info->id, id, info->id_len))
758 return &spi_nor_ids[tmp];
759 @@ -857,8 +1015,7 @@ static int macronix_quad_enable(struct s
760 val = read_sr(nor);
761 write_enable(nor);
762
763 - nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
764 - nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
765 + write_sr(nor, val | SR_QUAD_EN_MX);
766
767 if (spi_nor_wait_till_ready(nor))
768 return 1;
769 @@ -883,7 +1040,7 @@ static int write_sr_cr(struct spi_nor *n
770 nor->cmd_buf[0] = val & 0xff;
771 nor->cmd_buf[1] = (val >> 8);
772
773 - return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
774 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
775 }
776
777 static int spansion_quad_enable(struct spi_nor *nor)
778 @@ -925,7 +1082,7 @@ static int micron_quad_enable(struct spi
779
780 /* set EVCR, enable quad I/O */
781 nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
782 - ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
783 + ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
784 if (ret < 0) {
785 dev_err(nor->dev, "error while writing EVCR register\n");
786 return ret;
787 @@ -949,19 +1106,19 @@ static int micron_quad_enable(struct spi
788 return 0;
789 }
790
791 -static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
792 +static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
793 {
794 int status;
795
796 switch (JEDEC_MFR(info)) {
797 - case CFI_MFR_MACRONIX:
798 + case SNOR_MFR_MACRONIX:
799 status = macronix_quad_enable(nor);
800 if (status) {
801 dev_err(nor->dev, "Macronix quad-read not enabled\n");
802 return -EINVAL;
803 }
804 return status;
805 - case CFI_MFR_ST:
806 + case SNOR_MFR_MICRON:
807 status = micron_quad_enable(nor);
808 if (status) {
809 dev_err(nor->dev, "Micron quad-read not enabled\n");
810 @@ -991,11 +1148,10 @@ static int spi_nor_check(struct spi_nor
811
812 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
813 {
814 - const struct spi_device_id *id = NULL;
815 - struct flash_info *info;
816 + const struct flash_info *info = NULL;
817 struct device *dev = nor->dev;
818 - struct mtd_info *mtd = nor->mtd;
819 - struct device_node *np = dev->of_node;
820 + struct mtd_info *mtd = &nor->mtd;
821 + struct device_node *np = nor->flash_node;
822 int ret;
823 int i;
824
825 @@ -1003,27 +1159,25 @@ int spi_nor_scan(struct spi_nor *nor, co
826 if (ret)
827 return ret;
828
829 - /* Try to auto-detect if chip name wasn't specified */
830 - if (!name)
831 - id = spi_nor_read_id(nor);
832 - else
833 - id = spi_nor_match_id(name);
834 - if (IS_ERR_OR_NULL(id))
835 + if (name)
836 + info = spi_nor_match_id(name);
837 + /* Try to auto-detect if chip name wasn't specified or not found */
838 + if (!info)
839 + info = spi_nor_read_id(nor);
840 + if (IS_ERR_OR_NULL(info))
841 return -ENOENT;
842
843 - info = (void *)id->driver_data;
844 -
845 /*
846 * If caller has specified name of flash model that can normally be
847 * detected using JEDEC, let's verify it.
848 */
849 if (name && info->id_len) {
850 - const struct spi_device_id *jid;
851 + const struct flash_info *jinfo;
852
853 - jid = spi_nor_read_id(nor);
854 - if (IS_ERR(jid)) {
855 - return PTR_ERR(jid);
856 - } else if (jid != id) {
857 + jinfo = spi_nor_read_id(nor);
858 + if (IS_ERR(jinfo)) {
859 + return PTR_ERR(jinfo);
860 + } else if (jinfo != info) {
861 /*
862 * JEDEC knows better, so overwrite platform ID. We
863 * can't trust partitions any longer, but we'll let
864 @@ -1032,28 +1186,29 @@ int spi_nor_scan(struct spi_nor *nor, co
865 * information, even if it's not 100% accurate.
866 */
867 dev_warn(dev, "found %s, expected %s\n",
868 - jid->name, id->name);
869 - id = jid;
870 - info = (void *)jid->driver_data;
871 + jinfo->name, info->name);
872 + info = jinfo;
873 }
874 }
875
876 mutex_init(&nor->lock);
877
878 /*
879 - * Atmel, SST and Intel/Numonyx serial nor tend to power
880 - * up with the software protection bits set
881 + * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
882 + * with the software protection bits set
883 */
884
885 - if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
886 - JEDEC_MFR(info) == CFI_MFR_INTEL ||
887 - JEDEC_MFR(info) == CFI_MFR_SST) {
888 + if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
889 + JEDEC_MFR(info) == SNOR_MFR_INTEL ||
890 + JEDEC_MFR(info) == SNOR_MFR_SST ||
891 + JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
892 write_enable(nor);
893 write_sr(nor, 0);
894 }
895
896 if (!mtd->name)
897 mtd->name = dev_name(dev);
898 + mtd->priv = nor;
899 mtd->type = MTD_NORFLASH;
900 mtd->writesize = 1;
901 mtd->flags = MTD_CAP_NORFLASH;
902 @@ -1061,15 +1216,18 @@ int spi_nor_scan(struct spi_nor *nor, co
903 mtd->_erase = spi_nor_erase;
904 mtd->_read = spi_nor_read;
905
906 - /* nor protection support for STmicro chips */
907 - if (JEDEC_MFR(info) == CFI_MFR_ST) {
908 + /* NOR protection support for STmicro/Micron chips and similar */
909 + if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
910 + JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
911 nor->flash_lock = stm_lock;
912 nor->flash_unlock = stm_unlock;
913 + nor->flash_is_locked = stm_is_locked;
914 }
915
916 - if (nor->flash_lock && nor->flash_unlock) {
917 + if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
918 mtd->_lock = spi_nor_lock;
919 mtd->_unlock = spi_nor_unlock;
920 + mtd->_is_locked = spi_nor_is_locked;
921 }
922
923 /* sst nor chips use AAI word program */
924 @@ -1156,7 +1314,7 @@ int spi_nor_scan(struct spi_nor *nor, co
925 else if (mtd->size > 0x1000000) {
926 /* enable 4-byte addressing if the device exceeds 16MiB */
927 nor->addr_width = 4;
928 - if (JEDEC_MFR(info) == CFI_MFR_AMD) {
929 + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
930 /* Dedicated 4-byte command set */
931 switch (nor->flash_read) {
932 case SPI_NOR_QUAD:
933 @@ -1184,7 +1342,7 @@ int spi_nor_scan(struct spi_nor *nor, co
934
935 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
936
937 - dev_info(dev, "%s (%lld Kbytes)\n", id->name,
938 + dev_info(dev, "%s (%lld Kbytes)\n", info->name,
939 (long long)mtd->size >> 10);
940
941 dev_dbg(dev,
942 @@ -1207,11 +1365,11 @@ int spi_nor_scan(struct spi_nor *nor, co
943 }
944 EXPORT_SYMBOL_GPL(spi_nor_scan);
945
946 -static const struct spi_device_id *spi_nor_match_id(const char *name)
947 +static const struct flash_info *spi_nor_match_id(const char *name)
948 {
949 - const struct spi_device_id *id = spi_nor_ids;
950 + const struct flash_info *id = spi_nor_ids;
951
952 - while (id->name[0]) {
953 + while (id->name) {
954 if (!strcmp(name, id->name))
955 return id;
956 id++;
957 --- a/include/linux/mtd/spi-nor.h
958 +++ b/include/linux/mtd/spi-nor.h
959 @@ -10,6 +10,23 @@
960 #ifndef __LINUX_MTD_SPI_NOR_H
961 #define __LINUX_MTD_SPI_NOR_H
962
963 +#include <linux/bitops.h>
964 +#include <linux/mtd/cfi.h>
965 +
966 +/*
967 + * Manufacturer IDs
968 + *
969 + * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
970 + * Sometimes these are the same as CFI IDs, but sometimes they aren't.
971 + */
972 +#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
973 +#define SNOR_MFR_INTEL CFI_MFR_INTEL
974 +#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
975 +#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
976 +#define SNOR_MFR_SPANSION CFI_MFR_AMD
977 +#define SNOR_MFR_SST CFI_MFR_SST
978 +#define SNOR_MFR_WINBOND 0xef
979 +
980 /*
981 * Note on opcode nomenclature: some opcodes have a format like
982 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
983 @@ -61,24 +78,24 @@
984 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
985
986 /* Status Register bits. */
987 -#define SR_WIP 1 /* Write in progress */
988 -#define SR_WEL 2 /* Write enable latch */
989 +#define SR_WIP BIT(0) /* Write in progress */
990 +#define SR_WEL BIT(1) /* Write enable latch */
991 /* meaning of other SR_* bits may differ between vendors */
992 -#define SR_BP0 4 /* Block protect 0 */
993 -#define SR_BP1 8 /* Block protect 1 */
994 -#define SR_BP2 0x10 /* Block protect 2 */
995 -#define SR_SRWD 0x80 /* SR write protect */
996 +#define SR_BP0 BIT(2) /* Block protect 0 */
997 +#define SR_BP1 BIT(3) /* Block protect 1 */
998 +#define SR_BP2 BIT(4) /* Block protect 2 */
999 +#define SR_SRWD BIT(7) /* SR write protect */
1000
1001 -#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
1002 +#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
1003
1004 /* Enhanced Volatile Configuration Register bits */
1005 -#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
1006 +#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
1007
1008 /* Flag Status Register bits */
1009 -#define FSR_READY 0x80
1010 +#define FSR_READY BIT(7)
1011
1012 /* Configuration Register bits. */
1013 -#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
1014 +#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
1015
1016 enum read_mode {
1017 SPI_NOR_NORMAL = 0,
1018 @@ -87,33 +104,6 @@ enum read_mode {
1019 SPI_NOR_QUAD,
1020 };
1021
1022 -/**
1023 - * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
1024 - * @wren: command for "Write Enable", or 0x00 for not required
1025 - * @cmd: command for operation
1026 - * @cmd_pins: number of pins to send @cmd (1, 2, 4)
1027 - * @addr: address for operation
1028 - * @addr_pins: number of pins to send @addr (1, 2, 4)
1029 - * @addr_width: number of address bytes
1030 - * (3,4, or 0 for address not required)
1031 - * @mode: mode data
1032 - * @mode_pins: number of pins to send @mode (1, 2, 4)
1033 - * @mode_cycles: number of mode cycles (0 for mode not required)
1034 - * @dummy_cycles: number of dummy cycles (0 for dummy not required)
1035 - */
1036 -struct spi_nor_xfer_cfg {
1037 - u8 wren;
1038 - u8 cmd;
1039 - u8 cmd_pins;
1040 - u32 addr;
1041 - u8 addr_pins;
1042 - u8 addr_width;
1043 - u8 mode;
1044 - u8 mode_pins;
1045 - u8 mode_cycles;
1046 - u8 dummy_cycles;
1047 -};
1048 -
1049 #define SPI_NOR_MAX_CMD_SIZE 8
1050 enum spi_nor_ops {
1051 SPI_NOR_OPS_READ = 0,
1052 @@ -127,11 +117,14 @@ enum spi_nor_option_flags {
1053 SNOR_F_USE_FSR = BIT(0),
1054 };
1055
1056 +struct mtd_info;
1057 +
1058 /**
1059 * struct spi_nor - Structure for defining a the SPI NOR layer
1060 * @mtd: point to a mtd_info structure
1061 * @lock: the lock for the read/write/erase/lock/unlock operations
1062 * @dev: point to a spi device, or a spi nor controller device.
1063 + * @flash_node: point to a device node describing this flash instance.
1064 * @page_size: the page size of the SPI NOR
1065 * @addr_width: number of address bytes
1066 * @erase_opcode: the opcode for erasing a sector
1067 @@ -141,28 +134,28 @@ enum spi_nor_option_flags {
1068 * @flash_read: the mode of the read
1069 * @sst_write_second: used by the SST write operation
1070 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
1071 - * @cfg: used by the read_xfer/write_xfer
1072 * @cmd_buf: used by the write_reg
1073 * @prepare: [OPTIONAL] do some preparations for the
1074 * read/write/erase/lock/unlock operations
1075 * @unprepare: [OPTIONAL] do some post work after the
1076 * read/write/erase/lock/unlock operations
1077 - * @read_xfer: [OPTIONAL] the read fundamental primitive
1078 - * @write_xfer: [OPTIONAL] the writefundamental primitive
1079 * @read_reg: [DRIVER-SPECIFIC] read out the register
1080 * @write_reg: [DRIVER-SPECIFIC] write data to the register
1081 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
1082 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
1083 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
1084 * at the offset @offs
1085 - * @lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
1086 - * @unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
1087 + * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
1088 + * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
1089 + * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
1090 + * completely locked
1091 * @priv: the private data
1092 */
1093 struct spi_nor {
1094 - struct mtd_info *mtd;
1095 + struct mtd_info mtd;
1096 struct mutex lock;
1097 struct device *dev;
1098 + struct device_node *flash_node;
1099 u32 page_size;
1100 u8 addr_width;
1101 u8 erase_opcode;
1102 @@ -172,18 +165,12 @@ struct spi_nor {
1103 enum read_mode flash_read;
1104 bool sst_write_second;
1105 u32 flags;
1106 - struct spi_nor_xfer_cfg cfg;
1107 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
1108
1109 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
1110 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
1111 - int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
1112 - u8 *buf, size_t len);
1113 - int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
1114 - u8 *buf, size_t len);
1115 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
1116 - int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
1117 - int write_enable);
1118 + int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
1119
1120 int (*read)(struct spi_nor *nor, loff_t from,
1121 size_t len, size_t *retlen, u_char *read_buf);
1122 @@ -193,6 +180,7 @@ struct spi_nor {
1123
1124 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
1125 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
1126 + int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
1127
1128 void *priv;
1129 };