ar71xx: fix legacy image build error
[openwrt/openwrt.git] / target / linux / generic / patches-4.1 / 734-net-phy-at803x-allow-to-configure-via-pdata.patch
1 --- a/drivers/net/phy/at803x.c
2 +++ b/drivers/net/phy/at803x.c
3 @@ -12,12 +12,14 @@
4 */
5
6 #include <linux/phy.h>
7 +#include <linux/mdio.h>
8 #include <linux/module.h>
9 #include <linux/string.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/of_gpio.h>
13 #include <linux/gpio/consumer.h>
14 +#include <linux/platform_data/phy-at803x.h>
15
16 #define AT803X_INTR_ENABLE 0x12
17 #define AT803X_INTR_STATUS 0x13
18 @@ -34,8 +36,16 @@
19 #define AT803X_INER 0x0012
20 #define AT803X_INER_INIT 0xec00
21 #define AT803X_INSR 0x0013
22 +
23 +#define AT803X_PCS_SMART_EEE_CTRL3 0x805D
24 +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_MASK 0x3
25 +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT 12
26 +#define AT803X_SMART_EEE_CTRL3_LPI_EN BIT(8)
27 +
28 #define AT803X_DEBUG_ADDR 0x1D
29 #define AT803X_DEBUG_DATA 0x1E
30 +#define AT803X_DBG0_REG 0x00
31 +#define AT803X_DEBUG_RGMII_RX_CLK_DLY BIT(8)
32 #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
33 #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
34
35 @@ -50,6 +60,7 @@ MODULE_LICENSE("GPL");
36 struct at803x_priv {
37 bool phy_reset:1;
38 struct gpio_desc *gpiod_reset;
39 + int prev_speed;
40 };
41
42 struct at803x_context {
43 @@ -61,6 +72,43 @@ struct at803x_context {
44 u16 led_control;
45 };
46
47 +static u16
48 +at803x_dbg_reg_rmw(struct phy_device *phydev, u16 reg, u16 clear, u16 set)
49 +{
50 + struct mii_bus *bus = phydev->bus;
51 + int val;
52 +
53 + mutex_lock(&bus->mdio_lock);
54 +
55 + bus->write(bus, phydev->addr, AT803X_DEBUG_ADDR, reg);
56 + val = bus->read(bus, phydev->addr, AT803X_DEBUG_DATA);
57 + if (val < 0) {
58 + val = 0xffff;
59 + goto out;
60 + }
61 +
62 + val &= ~clear;
63 + val |= set;
64 + bus->write(bus, phydev->addr, AT803X_DEBUG_DATA, val);
65 +
66 +out:
67 + mutex_unlock(&bus->mdio_lock);
68 + return val;
69 +}
70 +
71 +static inline void
72 +at803x_dbg_reg_set(struct phy_device *phydev, u16 reg, u16 set)
73 +{
74 + at803x_dbg_reg_rmw(phydev, reg, 0, set);
75 +}
76 +
77 +static inline void
78 +at803x_dbg_reg_clr(struct phy_device *phydev, u16 reg, u16 clear)
79 +{
80 + at803x_dbg_reg_rmw(phydev, reg, clear, 0);
81 +}
82 +
83 +
84 /* save relevant PHY registers to private copy */
85 static void at803x_context_save(struct phy_device *phydev,
86 struct at803x_context *context)
87 @@ -209,8 +257,16 @@ static int at803x_probe(struct phy_devic
88 return 0;
89 }
90
91 +static void at803x_disable_smarteee(struct phy_device *phydev)
92 +{
93 + phy_write_mmd(phydev, MDIO_MMD_PCS, AT803X_PCS_SMART_EEE_CTRL3,
94 + 1 << AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT);
95 + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
96 +}
97 +
98 static int at803x_config_init(struct phy_device *phydev)
99 {
100 + struct at803x_platform_data *pdata;
101 int ret;
102
103 ret = genphy_config_init(phydev);
104 @@ -228,6 +284,26 @@ static int at803x_config_init(struct phy
105 return ret;
106 }
107
108 + pdata = dev_get_platdata(&phydev->dev);
109 + if (pdata) {
110 + if (pdata->disable_smarteee)
111 + at803x_disable_smarteee(phydev);
112 +
113 + if (pdata->enable_rgmii_rx_delay)
114 + at803x_dbg_reg_set(phydev, AT803X_DBG0_REG,
115 + AT803X_DEBUG_RGMII_RX_CLK_DLY);
116 + else
117 + at803x_dbg_reg_clr(phydev, AT803X_DBG0_REG,
118 + AT803X_DEBUG_RGMII_RX_CLK_DLY);
119 +
120 + if (pdata->enable_rgmii_tx_delay)
121 + at803x_dbg_reg_set(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL,
122 + AT803X_DEBUG_RGMII_TX_CLK_DLY);
123 + else
124 + at803x_dbg_reg_clr(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL,
125 + AT803X_DEBUG_RGMII_TX_CLK_DLY);
126 + }
127 +
128 return 0;
129 }
130
131 @@ -259,6 +335,8 @@ static int at803x_config_intr(struct phy
132 static void at803x_link_change_notify(struct phy_device *phydev)
133 {
134 struct at803x_priv *priv = phydev->priv;
135 + struct at803x_platform_data *pdata;
136 + pdata = dev_get_platdata(&phydev->dev);
137
138 /*
139 * Conduct a hardware reset for AT8030 every time a link loss is
140 @@ -289,6 +367,26 @@ static void at803x_link_change_notify(st
141 priv->phy_reset = false;
142 }
143 }
144 + if (pdata && pdata->fixup_rgmii_tx_delay &&
145 + phydev->speed != priv->prev_speed) {
146 + switch (phydev->speed) {
147 + case SPEED_10:
148 + case SPEED_100:
149 + at803x_dbg_reg_set(phydev,
150 + AT803X_DEBUG_SYSTEM_MODE_CTRL,
151 + AT803X_DEBUG_RGMII_TX_CLK_DLY);
152 + break;
153 + case SPEED_1000:
154 + at803x_dbg_reg_clr(phydev,
155 + AT803X_DEBUG_SYSTEM_MODE_CTRL,
156 + AT803X_DEBUG_RGMII_TX_CLK_DLY);
157 + break;
158 + default:
159 + break;
160 + }
161 +
162 + priv->prev_speed = phydev->speed;
163 + }
164 }
165
166 static struct phy_driver at803x_driver[] = {
167 --- /dev/null
168 +++ b/include/linux/platform_data/phy-at803x.h
169 @@ -0,0 +1,11 @@
170 +#ifndef _PHY_AT803X_PDATA_H
171 +#define _PHY_AT803X_PDATA_H
172 +
173 +struct at803x_platform_data {
174 + int disable_smarteee:1;
175 + int enable_rgmii_tx_delay:1;
176 + int enable_rgmii_rx_delay:1;
177 + int fixup_rgmii_tx_delay:1;
178 +};
179 +
180 +#endif /* _PHY_AT803X_PDATA_H */