target/linux/generic/patches-4.4/078-0004-net-phy-pick-Broadcom-drivers-updates-from-net-next-.patch

   1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   2 Subject: [PATCH 2/2] net: phy: pick Broadcom drivers updates from net-next for
   3  4.11
   4 MIME-Version: 1.0
   5 Content-Type: text/plain; charset=UTF-8
   6 Content-Transfer-Encoding: 8bit
   7
   8 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
   9 ---
  10
  11 --- a/drivers/net/phy/bcm7xxx.c
  12 +++ b/drivers/net/phy/bcm7xxx.c
  13 @@ -163,12 +163,43 @@ static int bcm7xxx_28nm_e0_plus_afe_conf
  14         return 0;
  15  }
  16
  17 +static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
  18 +{
  19 +       /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
  20 +       bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
  21 +
  22 +       /* Cut master bias current by 2% to compensate for RC_CAL offset */
  23 +       bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
  24 +
  25 +       /* Improve hybrid leakage */
  26 +       bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
  27 +
  28 +       /* Change rx_on_tune 8 to 0xf */
  29 +       bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
  30 +
  31 +       /* Change 100Tx EEE bandwidth */
  32 +       bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
  33 +
  34 +       /* Enable ffe zero detection for Vitesse interoperability */
  35 +       bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
  36 +
  37 +       r_rc_cal_reset(phydev);
  38 +
  39 +       return 0;
  40 +}
  41 +
  42  static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
  43  {
  44         u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
  45         u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
  46         int ret = 0;
  47
  48 +       /* Newer devices have moved the revision information back into a
  49 +        * standard location in MII_PHYS_ID[23]
  50 +        */
  51 +       if (rev == 0)
  52 +               rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
  53 +
  54         pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
  55                      dev_name(&phydev->dev), phydev->drv->name, rev, patch);
  56
  57 @@ -192,6 +223,9 @@ static int bcm7xxx_28nm_config_init(stru
  58         case 0x10:
  59                 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
  60                 break;
  61 +       case 0x01:
  62 +               ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
  63 +               break;
  64         default:
  65                 break;
  66         }
  67 @@ -336,6 +370,7 @@ static int bcm7xxx_suspend(struct phy_de
  68
  69  static struct phy_driver bcm7xxx_driver[] = {
  70         BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
  71 +       BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
  72         BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
  73         BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
  74         BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
  75 @@ -350,6 +385,7 @@ static struct phy_driver bcm7xxx_driver[
  76
  77  static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
  78         { PHY_ID_BCM7250, 0xfffffff0, },
  79 +       { PHY_ID_BCM7278, 0xfffffff0, },
  80         { PHY_ID_BCM7364, 0xfffffff0, },
  81         { PHY_ID_BCM7366, 0xfffffff0, },
  82         { PHY_ID_BCM7346, 0xfffffff0, },
  83 --- a/drivers/net/phy/broadcom.c
  84 +++ b/drivers/net/phy/broadcom.c
  85 @@ -30,6 +30,50 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
  86  MODULE_AUTHOR("Maciej W. Rozycki");
  87  MODULE_LICENSE("GPL");
  88
  89 +static int bcm54210e_config_init(struct phy_device *phydev)
  90 +{
  91 +       int val;
  92 +
  93 +       val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  94 +       val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  95 +       val |= MII_BCM54XX_AUXCTL_MISC_WREN;
  96 +       bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
  97 +
  98 +       val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
  99 +       val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
 100 +       bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
 101 +
 102 +       return 0;
 103 +}
 104 +
 105 +static int bcm54612e_config_init(struct phy_device *phydev)
 106 +{
 107 +       /* Clear TX internal delay unless requested. */
 108 +       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
 109 +           (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
 110 +               /* Disable TXD to GTXCLK clock delay (default set) */
 111 +               /* Bit 9 is the only field in shadow register 00011 */
 112 +               bcm_phy_write_shadow(phydev, 0x03, 0);
 113 +       }
 114 +
 115 +       /* Clear RX internal delay unless requested. */
 116 +       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
 117 +           (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
 118 +               u16 reg;
 119 +
 120 +               reg = bcm54xx_auxctl_read(phydev,
 121 +                                         MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
 122 +               /* Disable RXD to RXC delay (default set) */
 123 +               reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
 124 +               /* Clear shadow selector field */
 125 +               reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
 126 +               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
 127 +                                    MII_BCM54XX_AUXCTL_MISC_WREN | reg);
 128 +       }
 129 +
 130 +       return 0;
 131 +}
 132 +
 133  static int bcm54810_config(struct phy_device *phydev)
 134  {
 135         int rc, val;
 136 @@ -230,7 +274,15 @@ static int bcm54xx_config_init(struct ph
 137             (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 138                 bcm54xx_adjust_rxrefclk(phydev);
 139
 140 -       if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
 141 +       if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
 142 +               err = bcm54210e_config_init(phydev);
 143 +               if (err)
 144 +                       return err;
 145 +       } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
 146 +               err = bcm54612e_config_init(phydev);
 147 +               if (err)
 148 +                       return err;
 149 +       } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
 150                 err = bcm54810_config(phydev);
 151                 if (err)
 152                         return err;
 153 @@ -375,41 +427,6 @@ static int bcm5481_config_aneg(struct ph
 154         return ret;
 155  }
 156
 157 -static int bcm54612e_config_aneg(struct phy_device *phydev)
 158 -{
 159 -       int ret;
 160 -
 161 -       /* First, auto-negotiate. */
 162 -       ret = genphy_config_aneg(phydev);
 163 -
 164 -       /* Clear TX internal delay unless requested. */
 165 -       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
 166 -           (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
 167 -               /* Disable TXD to GTXCLK clock delay (default set) */
 168 -               /* Bit 9 is the only field in shadow register 00011 */
 169 -               bcm_phy_write_shadow(phydev, 0x03, 0);
 170 -       }
 171 -
 172 -       /* Clear RX internal delay unless requested. */
 173 -       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
 174 -           (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
 175 -               u16 reg;
 176 -
 177 -               /* Errata: reads require filling in the write selector field */
 178 -               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
 179 -                                    MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
 180 -               reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
 181 -               /* Disable RXD to RXC delay (default set) */
 182 -               reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
 183 -               /* Clear shadow selector field */
 184 -               reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
 185 -               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
 186 -                                    MII_BCM54XX_AUXCTL_MISC_WREN | reg);
 187 -       }
 188 -
 189 -       return ret;
 190 -}
 191 -
 192  static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
 193  {
 194         int val;
 195 @@ -548,6 +565,19 @@ static struct phy_driver broadcom_driver
 196         .config_intr    = bcm_phy_config_intr,
 197         .driver         = { .owner = THIS_MODULE },
 198  }, {
 199 +       .phy_id         = PHY_ID_BCM54210E,
 200 +       .phy_id_mask    = 0xfffffff0,
 201 +       .name           = "Broadcom BCM54210E",
 202 +       .features       = PHY_GBIT_FEATURES |
 203 +                         SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 204 +       .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 205 +       .config_init    = bcm54xx_config_init,
 206 +       .config_aneg    = genphy_config_aneg,
 207 +       .read_status    = genphy_read_status,
 208 +       .ack_interrupt  = bcm_phy_ack_intr,
 209 +       .config_intr    = bcm_phy_config_intr,
 210 +       .driver         = { .owner = THIS_MODULE },
 211 +}, {
 212         .phy_id         = PHY_ID_BCM5461,
 213         .phy_id_mask    = 0xfffffff0,
 214         .name           = "Broadcom BCM5461",
 215 @@ -568,7 +598,7 @@ static struct phy_driver broadcom_driver
 216                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 217         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 218         .config_init    = bcm54xx_config_init,
 219 -       .config_aneg    = bcm54612e_config_aneg,
 220 +       .config_aneg    = genphy_config_aneg,
 221         .read_status    = genphy_read_status,
 222         .ack_interrupt  = bcm_phy_ack_intr,
 223         .config_intr    = bcm_phy_config_intr,
 224 @@ -708,6 +738,7 @@ module_phy_driver(broadcom_drivers);
 225  static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
 226         { PHY_ID_BCM5411, 0xfffffff0 },
 227         { PHY_ID_BCM5421, 0xfffffff0 },
 228 +       { PHY_ID_BCM54210E, 0xfffffff0 },
 229         { PHY_ID_BCM5461, 0xfffffff0 },
 230         { PHY_ID_BCM54612E, 0xfffffff0 },
 231         { PHY_ID_BCM54616S, 0xfffffff0 },
 232 --- a/include/linux/brcmphy.h
 233 +++ b/include/linux/brcmphy.h
 234 @@ -17,6 +17,7 @@
 235  #define PHY_ID_BCM5482                 0x0143bcb0
 236  #define PHY_ID_BCM5411                 0x00206070
 237  #define PHY_ID_BCM5421                 0x002060e0
 238 +#define PHY_ID_BCM54210E               0x600d84a0
 239  #define PHY_ID_BCM5464                 0x002060b0
 240  #define PHY_ID_BCM5461                 0x002060c0
 241  #define PHY_ID_BCM54612E               0x03625e60
 242 @@ -24,6 +25,7 @@
 243  #define PHY_ID_BCM57780                        0x03625d90
 244
 245  #define PHY_ID_BCM7250                 0xae025280
 246 +#define PHY_ID_BCM7278                 0xae0251a0
 247  #define PHY_ID_BCM7364                 0xae025260
 248  #define PHY_ID_BCM7366                 0x600d8490
 249  #define PHY_ID_BCM7346                 0x600d8650
 250 @@ -103,18 +105,17 @@
 251  /*
 252   * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
 253   */
 254 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL      0x0000
 255 +#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL      0x00
 256  #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB         0x0400
 257  #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA      0x0800
 258
 259 -#define MII_BCM54XX_AUXCTL_MISC_WREN   0x8000
 260 -#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW   0x0100
 261 -#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX    0x0200
 262 -#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC     0x7000
 263 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC        0x0007
 264 -#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT  12
 265 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN  (1 << 8)
 266 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC                        0x07
 267 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN   0x0010
 268 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN  0x0100
 269 +#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX            0x0200
 270 +#define MII_BCM54XX_AUXCTL_MISC_WREN                   0x8000
 271
 272 +#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT  12
 273  #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK        0x0007
 274
 275  /*