kernel: add support for kernel 5.4
[openwrt/openwrt.git] / target / linux / generic / pending-5.4 / 470-mtd-spi-nor-support-limiting-4K-sectors-support-base.patch
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Sat, 4 Nov 2017 07:40:23 +0100
3 Subject: [PATCH] mtd: spi-nor: support limiting 4K sectors support based on
4 flash size
5
6 Some devices need 4K sectors to be able to deal with small flash chips.
7 For instance, w25x05 is 64 KiB in size, and without 4K sectors, the
8 entire chip is just one erase block.
9 On bigger flash chip sizes, using 4K sectors can significantly slow down
10 many operations, including using a writable filesystem. There are several
11 platforms where it makes sense to use a single kernel on both kinds of
12 devices.
13
14 To support this properly, allow configuring an upper flash chip size
15 limit for 4K sectors support.
16
17 Signed-off-by: Felix Fietkau <nbd@nbd.name>
18 ---
19
20 --- a/drivers/mtd/spi-nor/Kconfig
21 +++ b/drivers/mtd/spi-nor/Kconfig
22 @@ -34,6 +34,17 @@ config SPI_ASPEED_SMC
23 and support for the SPI flash memory controller (SPI) for
24 the host firmware. The implementation only supports SPI NOR.
25
26 +config MTD_SPI_NOR_USE_4K_SECTORS_LIMIT
27 + int "Maximum flash chip size to use 4K sectors on (in KiB)"
28 + depends on MTD_SPI_NOR_USE_4K_SECTORS
29 + default "4096"
30 + help
31 + There are many flash chips that support 4K sectors, but are so large
32 + that using them significantly slows down writing large amounts of
33 + data or using a writable filesystem.
34 + Any flash chip larger than the size specified in this option will
35 + not use 4K sectors.
36 +
37 config SPI_CADENCE_QUADSPI
38 tristate "Cadence Quad SPI controller"
39 depends on OF && (ARM || ARM64 || COMPILE_TEST)
40 --- a/drivers/mtd/spi-nor/spi-nor.c
41 +++ b/drivers/mtd/spi-nor/spi-nor.c
42 @@ -4464,6 +4464,7 @@ static void spi_nor_info_init_params(str
43 struct spi_nor_erase_map *map = &params->erase_map;
44 const struct flash_info *info = nor->info;
45 struct device_node *np = spi_nor_get_flash_node(nor);
46 + struct mtd_info *mtd = &nor->mtd;
47 u8 i, erase_mask;
48
49 /* Initialize legacy flash parameters and settings. */
50 @@ -4527,6 +4528,21 @@ static void spi_nor_info_init_params(str
51 */
52 erase_mask = 0;
53 i = 0;
54 +#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
55 + if ((info->flags & SECT_4K_PMC) && (mtd->size <=
56 + CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {
57 + erase_mask |= BIT(i);
58 + spi_nor_set_erase_type(&map->erase_type[i], 4096u,
59 + SPINOR_OP_BE_4K_PMC);
60 + i++;
61 + } else if ((info->flags & SECT_4K) && (mtd->size <=
62 + CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {
63 + erase_mask |= BIT(i);
64 + spi_nor_set_erase_type(&map->erase_type[i], 4096u,
65 + SPINOR_OP_BE_4K);
66 + i++;
67 + }
68 +#else
69 if (info->flags & SECT_4K_PMC) {
70 erase_mask |= BIT(i);
71 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
72 @@ -4538,6 +4554,7 @@ static void spi_nor_info_init_params(str
73 SPINOR_OP_BE_4K);
74 i++;
75 }
76 +#endif
77 erase_mask |= BIT(i);
78 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
79 SPINOR_OP_SE);