target/linux/generic/pending-5.4/482-mtd-spi-nor-fix-4-byte-opcode-support-for-w25q256.patch

   1 From: Mantas Pucka <mantas@8devices.com>
   2 To: linux-mtd@lists.infradead.org
   3 Subject: [PATCH] mtd: spi-nor: fix 4-byte opcode support for w25q256
   4 Date: Wed, 15 Apr 2020 16:48:30 +0300
   5 Message-ID: <1586958510-24012-1-git-send-email-mantas@8devices.com>
   6
   7 There are 2 different chips (w25q256fv and w25q256jv) that share
   8 the same JEDEC ID. Only w25q256jv fully supports 4-byte opcodes.
   9 Use SFDP header version to differentiate between them.
  10
  11 for OpenWRT only: rebased to linux-v5.4
  12
  13 Signed-off-by: Mantas Pucka <mantas@8devices.com>
  14 ---
  15
  16 --- a/drivers/mtd/spi-nor/spi-nor.c
  17 +++ b/drivers/mtd/spi-nor/spi-nor.c
  18 @@ -2172,6 +2172,32 @@ static struct spi_nor_fixups gd25q256_fi
  19         .default_init = gd25q256_default_init,
  20  };
  21
  22 +static int
  23 +w25q256_post_bfpt_fixups(struct spi_nor *nor,
  24 +                        const struct sfdp_parameter_header *bfpt_header,
  25 +                        const struct sfdp_bfpt *bfpt,
  26 +                        struct spi_nor_flash_parameter *params)
  27 +{
  28 +       /*
  29 +        * W25Q256JV supports 4B opcodes but W25Q256FV does not.
  30 +        * Unfortunately, Winbond has re-used the same JEDEC ID for both
  31 +        * variants which prevents us from defining a new entry in the parts
  32 +        * table.
  33 +        * To differentiate between W25Q256JV and W25Q256FV check SFDP header
  34 +        * version: only JV has JESD216A compliant structure (version 5)
  35 +        */
  36 +
  37 +       if (bfpt_header->major == SFDP_JESD216_MAJOR &&
  38 +           bfpt_header->minor == SFDP_JESD216A_MINOR)
  39 +               nor->flags |= SNOR_F_4B_OPCODES;
  40 +
  41 +       return 0;
  42 +}
  43 +
  44 +static struct spi_nor_fixups w25q256_fixups = {
  45 +       .post_bfpt = w25q256_post_bfpt_fixups,
  46 +};
  47 +
  48  /* NOTE: double check command sets and memory organization when you add
  49   * more nor chips.  This current list focusses on newer chips, which
  50   * have been converging on command sets which including JEDEC ID.
  51 @@ -2515,7 +2541,8 @@ static const struct flash_info spi_nor_i
  52         { "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
  53         { "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
  54         { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
  55 -       { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  56 +       { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
  57 +                         .fixups = &w25q256_fixups },
  58         { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
  59                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  60         { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,