target/linux/generic/pending-5.4/770-13-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Sun, 13 Sep 2020 08:17:02 +0200
   3 Subject: [PATCH] net: ethernet: mtk_eth_soc: fix parsing packets in GDM
   4
   5 When using DSA, set the special tag in GDM ingress control to allow the MAC
   6 to parse packets properly earlier. This affects rx DMA source port reporting.
   7
   8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
   9 ---
  10
  11 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  12 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  13 @@ -19,6 +19,7 @@
  14  #include <linux/interrupt.h>
  15  #include <linux/pinctrl/devinfo.h>
  16  #include <linux/phylink.h>
  17 +#include <net/dsa.h>
  18
  19  #include "mtk_eth_soc.h"
  20
  21 @@ -1280,13 +1281,12 @@ static int mtk_poll_rx(struct napi_struc
  22                         break;
  23
  24                 /* find out which mac the packet come from. values start at 1 */
  25 -               if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
  26 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) ||
  27 +                   (trxd.rxd4 & RX_DMA_SPECIAL_TAG))
  28                         mac = 0;
  29 -               } else {
  30 -                       mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
  31 -                               RX_DMA_FPORT_MASK;
  32 -                       mac--;
  33 -               }
  34 +               else
  35 +                       mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
  36 +                              RX_DMA_FPORT_MASK) - 1;
  37
  38                 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
  39                              !eth->netdev[mac]))
  40 @@ -2268,6 +2268,9 @@ static void mtk_gdm_config(struct mtk_et
  41
  42                 val |= config;
  43
  44 +               if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))
  45 +                       val |= MTK_GDMA_SPECIAL_TAG;
  46 +
  47                 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
  48         }
  49         /* Reset and enable PSE */
  50 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  51 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  52 @@ -82,6 +82,7 @@
  53
  54  /* GDM Exgress Control Register */
  55  #define MTK_GDMA_FWD_CFG(x)    (0x500 + (x * 0x1000))
  56 +#define MTK_GDMA_SPECIAL_TAG   BIT(24)
  57  #define MTK_GDMA_ICS_EN                BIT(22)
  58  #define MTK_GDMA_TCS_EN                BIT(21)
  59  #define MTK_GDMA_UCS_EN                BIT(20)
  60 @@ -324,6 +325,7 @@
  61  #define RX_DMA_L4_VALID_PDMA   BIT(30)         /* when PDMA is used */
  62  #define RX_DMA_FPORT_SHIFT     19
  63  #define RX_DMA_FPORT_MASK      0x7
  64 +#define RX_DMA_SPECIAL_TAG     BIT(22)
  65
  66  /* PHY Indirect Access Control registers */
  67  #define MTK_PHY_IAC            0x10004