target/linux/imx6/patches-3.10/110-gw5400-a.patch

   1 --- a/arch/arm/boot/dts/Makefile
   2 +++ b/arch/arm/boot/dts/Makefile
   3 @@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
   4         imx6dl-sabresd.dtb \
   5         imx6dl-wandboard.dtb \
   6         imx6q-arm2.dtb \
   7 +       imx6q-gw5400-a.dtb \
   8         imx6q-sabreauto.dtb \
   9         imx6q-sabrelite.dtb \
  10         imx6q-sabresd.dtb \
  11 --- a/arch/arm/boot/dts/imx6q.dtsi
  12 +++ b/arch/arm/boot/dts/imx6q.dtsi
  13 @@ -94,6 +94,14 @@
  14                                                         MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
  15                                                 >;
  16                                         };
  17 +
  18 +                                       pinctrl_audmux_3: audmux-3 {
  19 +                                               fsl,pins = <
  20 +                                                       MX6Q_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
  21 +                                                       MX6Q_PAD_EIM_D25__AUD5_RXC      0x80000000
  22 +                                                       MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
  23 +                                               >;
  24 +                                       };
  25                                 };
  26
  27                                 ecspi1 {
  28 @@ -201,6 +209,12 @@
  29                                                         MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
  30                                                 >;
  31                                         };
  32 +                                       pinctrl_i2c2_2: i2c2grp-2 {
  33 +                                               fsl,pins = <
  34 +                                                       MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  35 +                                                       MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  36 +                                               >;
  37 +                                       };
  38                                 };
  39
  40                                 i2c3 {
  41 @@ -210,6 +224,12 @@
  42                                                         MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
  43                                                 >;
  44                                         };
  45 +                                       pinctrl_i2c3_2: i2c3grp-2 {
  46 +                                               fsl,pins = <
  47 +                                                       MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  48 +                                                       MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  49 +                                               >;
  50 +                                       };
  51                                 };
  52
  53                                 uart1 {
  54 @@ -219,6 +239,12 @@
  55                                                         MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  56                                                 >;
  57                                         };
  58 +                                       pinctrl_uart1_2: uart1grp-2 {
  59 +                                               fsl,pins = <
  60 +                                                       MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  61 +                                                       MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  62 +                                               >;
  63 +                                       };
  64                                 };
  65
  66                                 uart2 {
  67 @@ -228,6 +254,21 @@
  68                                                         MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  69                                                 >;
  70                                         };
  71 +                                       pinctrl_uart2_2: uart2grp-2 {
  72 +                                               fsl,pins = <
  73 +                                                       MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  74 +                                                       MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  75 +                                               >;
  76 +                                       };
  77 +                               };
  78 +
  79 +                               uart3 {
  80 +                                       pinctrl_uart3_1: uart3grp-1 {
  81 +                                               fsl,pins = <
  82 +                                                       MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
  83 +                                                       MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
  84 +                                               >;
  85 +                                       };
  86                                 };
  87
  88                                 uart4 {
  89 @@ -238,6 +279,15 @@
  90                                                 >;
  91                                         };
  92                                 };
  93 +
  94 +                               uart5 {
  95 +                                       pinctrl_uart5_1: uart5grp-1 {
  96 +                                               fsl,pins = <
  97 +                                                       MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  98 +                                                       MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  99 +                                               >;
 100 +                                       };
 101 +                               };
 102
 103                                 usbotg {
 104                                         pinctrl_usbotg_1: usbotggrp-1 {
 105 --- a/arch/arm/mach-imx/mach-imx6q.c
 106 +++ b/arch/arm/mach-imx/mach-imx6q.c
 107 @@ -25,6 +25,7 @@
 108  #include <linux/of_irq.h>
 109  #include <linux/of_platform.h>
 110  #include <linux/opp.h>
 111 +#include <linux/pci.h>
 112  #include <linux/phy.h>
 113  #include <linux/regmap.h>
 114  #include <linux/micrel_phy.h>
 115 @@ -145,6 +146,65 @@ static void __init imx6q_sabrelite_init(
 116         imx6q_sabrelite_cko1_setup();
 117  }
 118
 119 +/*
 120 + * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
 121 + * as they are used for slots1-7 PERST#
 122 + */
 123 +static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
 124 +{
 125 +       u32 dw;
 126 +
 127 +       if (!of_machine_is_compatible("gw,ventana"))
 128 +               return;
 129 +
 130 +       if (dev->devfn != 0)
 131 +               return;
 132 +
 133 +       pci_read_config_dword(dev, 0x62c, &dw);
 134 +       dw |= 0xaaa8; // GPIO1-7 outputs
 135 +       pci_write_config_dword(dev, 0x62c, dw);
 136 +
 137 +       pci_read_config_dword(dev, 0x644, &dw);
 138 +       dw |= 0xfe;   // GPIO1-7 output high
 139 +       pci_write_config_dword(dev, 0x644, dw);
 140 +}
 141 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
 142 +       mx6_ventana_pciesw_early_fixup);
 143 +
 144 +/*
 145 + * configure PCIe core clock and PCIe ref clock
 146 + *
 147 + * TODO: disable CLK1 output and use CLK2 input from si52147 as PCIe ref
 148 + */
 149 +static void __init imx6q_ventana_pcie_setup(void)
 150 +{
 151 +       struct clk *axi_sel, *axi, *ref;
 152 +
 153 +       axi_sel = clk_get_sys(NULL, "pcie_axi_sel");
 154 +       axi = clk_get_sys(NULL, "axi");
 155 +       ref = clk_get_sys(NULL, "pcie_ref_125m");
 156 +       if (IS_ERR(axi_sel) || IS_ERR(axi) || IS_ERR(ref)) {
 157 +               pr_err("pcie setup failed - can't get clocks\n");
 158 +               goto put_clk;
 159 +       }
 160 +       clk_set_parent(axi_sel, axi);
 161 +       clk_prepare_enable(ref);
 162 +
 163 +put_clk:
 164 +       if (!IS_ERR(axi_sel))
 165 +               clk_put(axi_sel);
 166 +       if (!IS_ERR(axi))
 167 +               clk_put(axi);
 168 +       if (!IS_ERR(ref))
 169 +               clk_put(ref);
 170 +}
 171 +
 172 +static void __init imx6q_ventana_init(void)
 173 +{
 174 +       imx6q_ventana_pcie_setup();
 175 +       imx6q_sabrelite_cko1_setup();
 176 +}
 177 +
 178  static void __init imx6q_1588_init(void)
 179  {
 180         struct regmap *gpr;
 181 @@ -163,6 +223,9 @@ static void __init imx6q_usb_init(void)
 182
 183  static void __init imx6q_init_machine(void)
 184  {
 185 +       if (of_machine_is_compatible("gw,ventana"))
 186 +               imx6q_ventana_init();
 187 +
 188         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
 189                 imx6q_sabrelite_init();
 190