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[openwrt/openwrt.git] / target / linux / imx6 / patches-4.19 / 002-ARM-dts-imx-Add-GW5910-board-support.patch
1 From a1fb69366bb16753f0fba6a891fbef5cdd97cfbe Mon Sep 17 00:00:00 2001
2 From: Tim Harvey <tharvey@gateworks.com>
3 Date: Wed, 8 Jan 2020 07:44:22 -0800
4 Subject: [PATCH 2/4] ARM: dts: imx: Add GW5910 board support
5
6 The Gateworks GW5910 is an IMX6 SoC based single board computer with:
7 - IMX6Q or IMX6DL
8 - 32bit DDR3 DRAM
9 - FEC GbE RJ45 front-panel
10 - 1x miniPCIe socket with PCI Gen2, USB2
11 - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
12 - 5V to 60V DC input barrel jack
13 - 3axis accelerometer (lis2de12)
14 - GPS (ublox ZOE-M8Q)
15 - bi-color front-panel LED
16 - 256MB NAND boot device
17 - microSD socket (with UHS-I support)
18 - user pushbutton
19 - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
20 - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6)
21 - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6)
22 - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
23 - off-board SPI connector (1x chip-select)
24
25 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
26 Signed-off-by: Robert Jones <rjones@gateworks.com>
27 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
28 ---
29 arch/arm/boot/dts/Makefile | 2 +
30 arch/arm/boot/dts/imx6dl-gw5910.dts | 14 +
31 arch/arm/boot/dts/imx6q-gw5910.dts | 14 +
32 arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 491 ++++++++++++++++++++++++++++++++++
33 4 files changed, 521 insertions(+)
34 create mode 100644 arch/arm/boot/dts/imx6dl-gw5910.dts
35 create mode 100644 arch/arm/boot/dts/imx6q-gw5910.dts
36 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5910.dtsi
37
38 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
39 index 9ee80e2..85e53cc 100644
40 --- a/arch/arm/boot/dts/Makefile
41 +++ b/arch/arm/boot/dts/Makefile
42 @@ -423,6 +423,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
43 imx6dl-gw5903.dtb \
44 imx6dl-gw5904.dtb \
45 imx6dl-gw5907.dtb \
46 + imx6dl-gw5910.dtb \
47 imx6dl-hummingboard.dtb \
48 imx6dl-hummingboard-emmc-som-v15.dtb \
49 imx6dl-hummingboard-som-v15.dtb \
50 @@ -495,6 +496,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
51 imx6q-gw5903.dtb \
52 imx6q-gw5904.dtb \
53 imx6q-gw5907.dtb \
54 + imx6q-gw5910.dtb \
55 imx6q-h100.dtb \
56 imx6q-hummingboard.dtb \
57 imx6q-hummingboard-emmc-som-v15.dtb \
58 diff --git a/arch/arm/boot/dts/imx6dl-gw5910.dts b/arch/arm/boot/dts/imx6dl-gw5910.dts
59 new file mode 100644
60 index 00000000..0d5e7e5
61 --- /dev/null
62 +++ b/arch/arm/boot/dts/imx6dl-gw5910.dts
63 @@ -0,0 +1,14 @@
64 +// SPDX-License-Identifier: GPL-2.0
65 +/*
66 + * Copyright 2019 Gateworks Corporation
67 + */
68 +
69 +/dts-v1/;
70 +
71 +#include "imx6dl.dtsi"
72 +#include "imx6qdl-gw5910.dtsi"
73 +
74 +/ {
75 + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
76 + compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
77 +};
78 diff --git a/arch/arm/boot/dts/imx6q-gw5910.dts b/arch/arm/boot/dts/imx6q-gw5910.dts
79 new file mode 100644
80 index 00000000..6aafa2f
81 --- /dev/null
82 +++ b/arch/arm/boot/dts/imx6q-gw5910.dts
83 @@ -0,0 +1,14 @@
84 +// SPDX-License-Identifier: GPL-2.0
85 +/*
86 + * Copyright 2019 Gateworks Corporation
87 + */
88 +
89 +/dts-v1/;
90 +
91 +#include "imx6q.dtsi"
92 +#include "imx6qdl-gw5910.dtsi"
93 +
94 +/ {
95 + model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
96 + compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
97 +};
98 diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
99 new file mode 100644
100 index 00000000..be1af74
101 --- /dev/null
102 +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
103 @@ -0,0 +1,491 @@
104 +// SPDX-License-Identifier: GPL-2.0
105 +/*
106 + * Copyright 2019 Gateworks Corporation
107 + */
108 +
109 +#include <dt-bindings/gpio/gpio.h>
110 +
111 +/ {
112 + /* these are used by bootloader for disabling nodes */
113 + aliases {
114 + led0 = &led0;
115 + led1 = &led1;
116 + led2 = &led2;
117 + };
118 +
119 + chosen {
120 + stdout-path = &uart2;
121 + };
122 +
123 + memory@10000000 {
124 + device_type = "memory";
125 + reg = <0x10000000 0x20000000>;
126 + };
127 +
128 + leds {
129 + compatible = "gpio-leds";
130 + pinctrl-names = "default";
131 + pinctrl-0 = <&pinctrl_gpio_leds>;
132 +
133 + led0: user1 {
134 + label = "user1";
135 + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
136 + default-state = "on";
137 + linux,default-trigger = "heartbeat";
138 + };
139 +
140 + led1: user2 {
141 + label = "user2";
142 + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
143 + default-state = "off";
144 + };
145 +
146 + led2: user3 {
147 + label = "user3";
148 + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
149 + default-state = "off";
150 + };
151 + };
152 +
153 + pps {
154 + compatible = "pps-gpio";
155 + pinctrl-names = "default";
156 + pinctrl-0 = <&pinctrl_pps>;
157 + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
158 + status = "okay";
159 + };
160 +
161 + reg_3p3v: regulator-3p3v {
162 + compatible = "regulator-fixed";
163 + regulator-name = "3P3V";
164 + regulator-min-microvolt = <3300000>;
165 + regulator-max-microvolt = <3300000>;
166 + regulator-always-on;
167 + };
168 +
169 + reg_5p0v: regulator-5p0v {
170 + compatible = "regulator-fixed";
171 + regulator-name = "5P0V";
172 + regulator-min-microvolt = <5000000>;
173 + regulator-max-microvolt = <5000000>;
174 + regulator-always-on;
175 + };
176 +
177 + reg_wl: regulator-wl {
178 + pinctrl-names = "default";
179 + pinctrl-0 = <&pinctrl_reg_wl>;
180 + compatible = "regulator-fixed";
181 + regulator-name = "wl";
182 + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
183 + startup-delay-us = <100>;
184 + enable-active-high;
185 + regulator-min-microvolt = <3300000>;
186 + regulator-max-microvolt = <3300000>;
187 + regulator-always-on;
188 + };
189 +
190 + reg_bt: regulator-bt {
191 + pinctrl-names = "default";
192 + pinctrl-0 = <&pinctrl_reg_bt>;
193 + compatible = "regulator-fixed";
194 + regulator-name = "bt";
195 + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
196 + startup-delay-us = <100>;
197 + enable-active-high;
198 + regulator-min-microvolt = <3300000>;
199 + regulator-max-microvolt = <3300000>;
200 + regulator-always-on;
201 + };
202 +};
203 +
204 +
205 +&ecspi3 {
206 + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
207 + pinctrl-names = "default";
208 + pinctrl-0 = <&pinctrl_ecspi3>;
209 + status = "okay";
210 +};
211 +
212 +&fec {
213 + pinctrl-names = "default";
214 + pinctrl-0 = <&pinctrl_enet>;
215 + phy-mode = "rgmii-id";
216 + status = "okay";
217 +};
218 +
219 +&gpmi {
220 + pinctrl-names = "default";
221 + pinctrl-0 = <&pinctrl_gpmi_nand>;
222 + status = "okay";
223 +};
224 +
225 +&i2c1 {
226 + clock-frequency = <100000>;
227 + pinctrl-names = "default";
228 + pinctrl-0 = <&pinctrl_i2c1>;
229 + status = "okay";
230 +
231 + gpio@23 {
232 + compatible = "nxp,pca9555";
233 + reg = <0x23>;
234 + gpio-controller;
235 + #gpio-cells = <2>;
236 + };
237 +
238 + eeprom@50 {
239 + compatible = "atmel,24c02";
240 + reg = <0x50>;
241 + pagesize = <16>;
242 + };
243 +
244 + eeprom@51 {
245 + compatible = "atmel,24c02";
246 + reg = <0x51>;
247 + pagesize = <16>;
248 + };
249 +
250 + eeprom@52 {
251 + compatible = "atmel,24c02";
252 + reg = <0x52>;
253 + pagesize = <16>;
254 + };
255 +
256 + eeprom@53 {
257 + compatible = "atmel,24c02";
258 + reg = <0x53>;
259 + pagesize = <16>;
260 + };
261 +
262 + rtc@68 {
263 + compatible = "dallas,ds1672";
264 + reg = <0x68>;
265 + };
266 +};
267 +
268 +&i2c2 {
269 + clock-frequency = <100000>;
270 + pinctrl-names = "default";
271 + pinctrl-0 = <&pinctrl_i2c2>;
272 + status = "okay";
273 +};
274 +
275 +&i2c3 {
276 + clock-frequency = <100000>;
277 + pinctrl-names = "default";
278 + pinctrl-0 = <&pinctrl_i2c3>;
279 + status = "okay";
280 +
281 + accel@19 {
282 + pinctrl-names = "default";
283 + pinctrl-0 = <&pinctrl_accel>;
284 + compatible = "st,lis2de12";
285 + reg = <0x19>;
286 + st,drdy-int-pin = <1>;
287 + interrupt-parent = <&gpio7>;
288 + interrupts = <13 0>;
289 + interrupt-names = "INT1";
290 + };
291 +};
292 +
293 +&pcie {
294 + pinctrl-names = "default";
295 + pinctrl-0 = <&pinctrl_pcie>;
296 + reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
297 + status = "okay";
298 +};
299 +
300 +&pwm2 {
301 + pinctrl-names = "default";
302 + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
303 + status = "disabled";
304 +};
305 +
306 +&pwm3 {
307 + pinctrl-names = "default";
308 + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
309 + status = "disabled";
310 +};
311 +
312 +/* off-board RS232 */
313 +&uart1 {
314 + pinctrl-names = "default";
315 + pinctrl-0 = <&pinctrl_uart1>;
316 + status = "okay";
317 +};
318 +
319 +/* serial console */
320 +&uart2 {
321 + pinctrl-names = "default";
322 + pinctrl-0 = <&pinctrl_uart2>;
323 + status = "okay";
324 +};
325 +
326 +/* Sterling-LWB Bluetooth */
327 +&uart4 {
328 + pinctrl-names = "default";
329 + pinctrl-0 = <&pinctrl_uart4>;
330 + uart-has-rtscts;
331 + status = "okay";
332 +};
333 +
334 +/* GPS */
335 +&uart5 {
336 + pinctrl-names = "default";
337 + pinctrl-0 = <&pinctrl_uart5>;
338 + status = "okay";
339 +};
340 +
341 +&usbotg {
342 + vbus-supply = <&reg_5p0v>;
343 + pinctrl-names = "default";
344 + pinctrl-0 = <&pinctrl_usbotg>;
345 + disable-over-current;
346 + status = "okay";
347 +};
348 +
349 +&usbh1 {
350 + status = "okay";
351 +};
352 +
353 +/* Sterling-LWB SDIO WiFi */
354 +&usdhc2 {
355 + pinctrl-names = "default";
356 + pinctrl-0 = <&pinctrl_usdhc2>;
357 + vmmc-supply = <&reg_3p3v>;
358 + non-removable;
359 + bus-width = <4>;
360 + status = "okay";
361 +};
362 +
363 +&usdhc3 {
364 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
365 + pinctrl-0 = <&pinctrl_usdhc3>;
366 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
367 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
368 + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
369 + vmmc-supply = <&reg_3p3v>;
370 + status = "okay";
371 +};
372 +
373 +&wdog1 {
374 + pinctrl-names = "default";
375 + pinctrl-0 = <&pinctrl_wdog>;
376 + fsl,ext-reset-output;
377 +};
378 +
379 +&iomuxc {
380 + pinctrl_accel: accelmuxgrp {
381 + fsl,pins = <
382 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
383 + >;
384 + };
385 +
386 + pinctrl_ecspi3: escpi3grp {
387 + fsl,pins = <
388 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
389 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
390 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
391 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
392 + >;
393 + };
394 +
395 + pinctrl_enet: enetgrp {
396 + fsl,pins = <
397 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
398 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
399 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
400 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
401 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
402 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
403 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
404 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
405 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
406 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
407 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
408 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
409 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
410 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
411 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
412 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
413 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
414 + >;
415 + };
416 +
417 + pinctrl_gpio_leds: gpioledsgrp {
418 + fsl,pins = <
419 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
420 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
421 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
422 + >;
423 + };
424 +
425 + pinctrl_gpmi_nand: gpminandgrp {
426 + fsl,pins = <
427 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
428 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
429 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
430 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
431 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
432 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
433 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
434 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
435 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
436 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
437 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
438 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
439 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
440 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
441 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
442 + >;
443 + };
444 +
445 + pinctrl_i2c1: i2c1grp {
446 + fsl,pins = <
447 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
448 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
449 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
450 + >;
451 + };
452 +
453 + pinctrl_i2c2: i2c2grp {
454 + fsl,pins = <
455 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
456 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
457 + >;
458 + };
459 +
460 + pinctrl_i2c3: i2c3grp {
461 + fsl,pins = <
462 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
463 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
464 + >;
465 + };
466 +
467 + pinctrl_pcie: pciegrp {
468 + fsl,pins = <
469 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
470 + >;
471 + };
472 +
473 + pinctrl_pps: ppsgrp {
474 + fsl,pins = <
475 + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
476 + >;
477 + };
478 +
479 + pinctrl_pwm2: pwm2grp {
480 + fsl,pins = <
481 + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
482 + >;
483 + };
484 +
485 + pinctrl_pwm3: pwm3grp {
486 + fsl,pins = <
487 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
488 + >;
489 + };
490 +
491 + pinctrl_reg_bt: regbtgrp {
492 + fsl,pins = <
493 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
494 + >;
495 + };
496 +
497 + pinctrl_reg_wl: regwlgrp {
498 + fsl,pins = <
499 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
500 + >;
501 + };
502 +
503 + pinctrl_uart1: uart1grp {
504 + fsl,pins = <
505 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
506 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
507 + >;
508 + };
509 +
510 + pinctrl_uart2: uart2grp {
511 + fsl,pins = <
512 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
513 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
514 + >;
515 + };
516 +
517 + pinctrl_uart4: uart4grp {
518 + fsl,pins = <
519 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
520 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
521 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
522 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
523 + >;
524 + };
525 +
526 + pinctrl_uart5: uart5grp {
527 + fsl,pins = <
528 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
529 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
530 + >;
531 + };
532 +
533 + pinctrl_usbotg: usbotggrp {
534 + fsl,pins = <
535 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
536 + >;
537 + };
538 +
539 + pinctrl_usdhc2: usdhc2grp {
540 + fsl,pins = <
541 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
542 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
543 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
544 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
545 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
546 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
547 + >;
548 + };
549 +
550 + pinctrl_usdhc3: usdhc3grp {
551 + fsl,pins = <
552 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
553 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
554 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
555 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
556 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
557 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
558 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
559 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
560 + >;
561 + };
562 +
563 + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
564 + fsl,pins = <
565 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
566 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
567 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
568 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
569 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
570 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
571 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
572 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
573 + >;
574 + };
575 +
576 + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
577 + fsl,pins = <
578 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
579 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
580 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
581 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
582 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
583 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
584 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
585 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
586 + >;
587 + };
588 +
589 + pinctrl_wdog: wdoggrp {
590 + fsl,pins = <
591 + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
592 + >;
593 + };
594 +};
595 --
596 2.7.4
597
OpenWrt Source Repository