target/linux/imx6/patches-4.4/040-ARM-dts-imx-ventana-add-pwm-nodes.patch

   1 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
   2 +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
   3 @@ -174,6 +174,24 @@
   4         status = "okay";
   5  };
   6
   7 +&pwm2 {
   8 +       pinctrl-names = "default";
   9 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  10 +       status = "disabled";
  11 +};
  12 +
  13 +&pwm3 {
  14 +       pinctrl-names = "default";
  15 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  16 +       status = "disabled";
  17 +};
  18 +
  19 +&pwm4 {
  20 +       pinctrl-names = "default";
  21 +       pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  22 +       status = "disabled";
  23 +};
  24 +
  25  &uart1 {
  26         pinctrl-names = "default";
  27         pinctrl-0 = <&pinctrl_uart1>;
  28 @@ -294,6 +312,24 @@
  29                         >;
  30                 };
  31
  32 +               pinctrl_pwm2: pwm2grp {
  33 +                       fsl,pins = <
  34 +                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
  35 +                       >;
  36 +               };
  37 +
  38 +               pinctrl_pwm3: pwm3grp {
  39 +                       fsl,pins = <
  40 +                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
  41 +                       >;
  42 +               };
  43 +
  44 +               pinctrl_pwm4: pwm4grp {
  45 +                       fsl,pins = <
  46 +                               MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
  47 +                       >;
  48 +               };
  49 +
  50                 pinctrl_uart1: uart1grp {
  51                         fsl,pins = <
  52                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
  53 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
  54 +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
  55 @@ -282,6 +282,18 @@
  56         status = "okay";
  57  };
  58
  59 +&pwm2 {
  60 +       pinctrl-names = "default";
  61 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  62 +       status = "disabled";
  63 +};
  64 +
  65 +&pwm3 {
  66 +       pinctrl-names = "default";
  67 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  68 +       status = "disabled";
  69 +};
  70 +
  71  &pwm4 {
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_pwm4>;
  74 @@ -436,6 +448,18 @@
  75                         >;
  76                 };
  77
  78 +               pinctrl_pwm2: pwm2grp {
  79 +                       fsl,pins = <
  80 +                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
  81 +                       >;
  82 +               };
  83 +
  84 +               pinctrl_pwm3: pwm3grp {
  85 +                       fsl,pins = <
  86 +                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
  87 +                       >;
  88 +               };
  89 +
  90                 pinctrl_pwm4: pwm4grp {
  91                         fsl,pins = <
  92                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
  93 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
  94 +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
  95 @@ -287,6 +287,18 @@
  96         };
  97  };
  98
  99 +&pwm2 {
 100 +       pinctrl-names = "default";
 101 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 102 +       status = "disabled";
 103 +};
 104 +
 105 +&pwm3 {
 106 +       pinctrl-names = "default";
 107 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 108 +       status = "disabled";
 109 +};
 110 +
 111  &pwm4 {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_pwm4>;
 114 @@ -442,6 +454,18 @@
 115                         >;
 116                 };
 117
 118 +               pinctrl_pwm2: pwm2grp {
 119 +                       fsl,pins = <
 120 +                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 121 +                       >;
 122 +               };
 123 +
 124 +               pinctrl_pwm3: pwm3grp {
 125 +                       fsl,pins = <
 126 +                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 127 +                       >;
 128 +               };
 129 +
 130                 pinctrl_pwm4: pwm4grp {
 131                         fsl,pins = <
 132                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 133 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
 134 +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
 135 @@ -378,6 +378,24 @@
 136         };
 137  };
 138
 139 +&pwm1 {
 140 +       pinctrl-names = "default";
 141 +       pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
 142 +       status = "disabled";
 143 +};
 144 +
 145 +&pwm2 {
 146 +       pinctrl-names = "default";
 147 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 148 +       status = "disabled";
 149 +};
 150 +
 151 +&pwm3 {
 152 +       pinctrl-names = "default";
 153 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 154 +       status = "disabled";
 155 +};
 156 +
 157  &pwm4 {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_pwm4>;
 160 @@ -537,6 +555,24 @@
 161                         >;
 162                 };
 163
 164 +               pinctrl_pwm1: pwm1grp {
 165 +                       fsl,pins = <
 166 +                               MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 167 +                       >;
 168 +               };
 169 +
 170 +               pinctrl_pwm2: pwm2grp {
 171 +                       fsl,pins = <
 172 +                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 173 +                       >;
 174 +               };
 175 +
 176 +               pinctrl_pwm3: pwm3grp {
 177 +                       fsl,pins = <
 178 +                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 179 +                       >;
 180 +               };
 181 +
 182                 pinctrl_pwm4: pwm4grp {
 183                         fsl,pins = <
 184                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 185 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
 186 +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
 187 @@ -198,6 +198,18 @@
 188         status = "okay";
 189  };
 190
 191 +&pwm2 {
 192 +       pinctrl-names = "default";
 193 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 194 +       status = "disabled";
 195 +};
 196 +
 197 +&pwm3 {
 198 +       pinctrl-names = "default";
 199 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 200 +       status = "disabled";
 201 +};
 202 +
 203  &ssi1 {
 204         status = "okay";
 205  };
 206 @@ -290,6 +302,18 @@
 207                         >;
 208                 };
 209
 210 +               pinctrl_pwm2: pwm2grp {
 211 +                       fsl,pins = <
 212 +                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 213 +                       >;
 214 +               };
 215 +
 216 +               pinctrl_pwm3: pwm3grp {
 217 +                       fsl,pins = <
 218 +                               MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 219 +                       >;
 220 +               };
 221 +
 222                 pinctrl_uart2: uart2grp {
 223                         fsl,pins = <
 224                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 225 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
 226 +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
 227 @@ -164,6 +164,18 @@
 228         status = "okay";
 229  };
 230
 231 +&pwm2 {
 232 +       pinctrl-names = "default";
 233 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 234 +       status = "disabled";
 235 +};
 236 +
 237 +&pwm3 {
 238 +       pinctrl-names = "default";
 239 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 240 +       status = "disabled";
 241 +};
 242 +
 243  &uart2 {
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_uart2>;
 246 @@ -242,6 +254,18 @@
 247                         >;
 248                 };
 249
 250 +               pinctrl_pwm2: pwm2grp {
 251 +                       fsl,pins = <
 252 +                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 253 +                       >;
 254 +               };
 255 +
 256 +               pinctrl_pwm3: pwm3grp {
 257 +                       fsl,pins = <
 258 +                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 259 +                       >;
 260 +               };
 261 +
 262                 pinctrl_uart2: uart2grp {
 263                         fsl,pins = <
 264                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1