target/linux/imx6/patches-4.4/110-serial-imx-repair-and-complete-handshaking.patch

   1 From 90ebc4838666d148eac5bbac6f4044e5b25cd2d6 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
   3 Date: Sun, 18 Oct 2015 21:34:46 +0200
   4 Subject: [PATCH] serial: imx: repair and complete handshaking
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The .get_mctrl callback should not report the status of RTS or LOOP, so
  10 drop this. Instead implement reporting the state of CAR (aka DCD) and
  11 RI.
  12
  13 For .set_mctrl implement setting the DTR line.
  14
  15 Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
  16 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  17 Signed-off-by: Petr Štetiar <ynezz@true.cz>
  18 ---
  19  drivers/tty/serial/imx.c | 23 +++++++++++++++++------
  20  1 file changed, 17 insertions(+), 6 deletions(-)
  21
  22 --- a/drivers/tty/serial/imx.c
  23 +++ b/drivers/tty/serial/imx.c
  24 @@ -148,8 +148,11 @@
  25  #define USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
  26  #define USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
  27  #define USR2_IDLE       (1<<12) /* Idle condition */
  28 +#define USR2_RIDELT     (1<<10) /* Ring Interrupt Delta */
  29 +#define USR2_RIIN       (1<<9)  /* Ring Indicator Input */
  30  #define USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
  31  #define USR2_WAKE       (1<<7)  /* Wake */
  32 +#define USR2_DCDIN      (1<<5)  /* Data Carrier Detect Input */
  33  #define USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
  34  #define USR2_TXDC       (1<<3)  /* Transmitter complete */
  35  #define USR2_BRCD       (1<<2)  /* Break condition */
  36 @@ -804,16 +807,19 @@ static unsigned int imx_tx_empty(struct
  37  static unsigned int imx_get_mctrl(struct uart_port *port)
  38  {
  39         struct imx_port *sport = (struct imx_port *)port;
  40 -       unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
  41 +       unsigned int tmp = TIOCM_DSR;
  42 +       unsigned usr1 = readl(sport->port.membase + USR1);
  43
  44 -       if (readl(sport->port.membase + USR1) & USR1_RTSS)
  45 +       if (usr1 & USR1_RTSS)
  46                 tmp |= TIOCM_CTS;
  47
  48 -       if (readl(sport->port.membase + UCR2) & UCR2_CTS)
  49 -               tmp |= TIOCM_RTS;
  50 -
  51 -       if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
  52 -               tmp |= TIOCM_LOOP;
  53 +       /* in DCE mode DCDIN is always 0 */
  54 +       if (!(usr1 & USR2_DCDIN))
  55 +               tmp |= TIOCM_CAR;
  56 +
  57 +       /* in DCE mode RIIN is always 0 */
  58 +       if (readl(sport->port.membase + USR2) & USR2_RIIN)
  59 +               tmp |= TIOCM_RI;
  60
  61         return tmp;
  62  }
  63 @@ -831,6 +837,11 @@ static void imx_set_mctrl(struct uart_po
  64                 writel(temp, sport->port.membase + UCR2);
  65         }
  66
  67 +       temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
  68 +       if (!(mctrl & TIOCM_DTR))
  69 +               temp |= UCR3_DSR;
  70 +       writel(temp, sport->port.membase + UCR3);
  71 +
  72         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
  73         if (mctrl & TIOCM_LOOP)
  74                 temp |= UTS_LOOP;