target/linux/imx6/patches-4.4/113-serial-imx-make-sure-unhandled-irqs-are-disabled.patch

   1 From a58c6360b9eb3a2374b0b069ba9ce7baec0f26df Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
   3 Date: Thu, 24 Mar 2016 14:24:22 +0100
   4 Subject: [PATCH 3/3] serial: imx: make sure unhandled irqs are disabled
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Make sure that events that are not handled in the irq function don't
  10 trigger an interrupt.
  11
  12 When the serial port is operated in DTE mode, the events for DCD and RI
  13 events are enabled after a system reset by default.
  14
  15 Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
  16 Signed-off-by: Petr Štetiar <ynezz@true.cz>
  17 ---
  18  drivers/tty/serial/imx.c | 23 ++++++++++++++++++++++-
  19  1 file changed, 22 insertions(+), 1 deletion(-)
  20
  21 --- a/drivers/tty/serial/imx.c
  22 +++ b/drivers/tty/serial/imx.c
  23 @@ -1184,11 +1184,32 @@ static int imx_startup(struct uart_port
  24         temp |= (UCR2_RXEN | UCR2_TXEN);
  25         if (!sport->have_rtscts)
  26                 temp |= UCR2_IRTS;
  27 +       /*
  28 +        * make sure the edge sensitive RTS-irq is disabled,
  29 +        * we're using RTSD instead.
  30 +        */
  31 +       if (!is_imx1_uart(sport))
  32 +               temp &= ~UCR2_RTSEN;
  33         writel(temp, sport->port.membase + UCR2);
  34
  35         if (!is_imx1_uart(sport)) {
  36                 temp = readl(sport->port.membase + UCR3);
  37 -               temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
  38 +
  39 +               /*
  40 +                * The effect of RI and DCD differs depending on the UFCR_DCEDTE
  41 +                * bit. In DCE mode they control the outputs, in DTE mode they
  42 +                * enable the respective irqs. At least the DCD irq cannot be
  43 +                * cleared on i.MX25 at least, so it's not usable and must be
  44 +                * disabled. I don't have test hardware to check if RI has the
  45 +                * same problem but I consider this likely so it's disabled for
  46 +                * now, too.
  47 +                */
  48 +               temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
  49 +                       UCR3_RI | UCR3_DCD;
  50 +
  51 +               if (sport->dte_mode)
  52 +                       temp &= ~(UCR3_RI | UCR3_DCD);
  53 +
  54                 writel(temp, sport->port.membase + UCR3);
  55         }
  56