ipq40xx: use patches that were sent upstream
[openwrt/openwrt.git] / target / linux / ipq40xx / files-4.14 / arch / arm / boot / dts / qcom-ipq4018-ex61x0v2.dtsi
1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 */
17
18 #include "qcom-ipq4019.dtsi"
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/input/input.h>
21 #include <dt-bindings/soc/qcom,tcsr.h>
22
23 / {
24 model = "Netgear EX61X0v2";
25 compatible = "netgear,ex61x0v2", "qcom,ipq4019";
26
27 soc {
28 mdio@90000 {
29 status = "okay";
30 };
31
32 ess-psgmii@98000 {
33 status = "okay";
34 };
35
36 tcsr@1949000 {
37 compatible = "qcom,tcsr";
38 reg = <0x1949000 0x100>;
39 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
40 };
41
42 ess_tcsr@1953000 {
43 compatible = "qcom,tcsr";
44 reg = <0x1953000 0x1000>;
45 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
46 };
47
48 tcsr@1957000 {
49 compatible = "qcom,tcsr";
50 reg = <0x1957000 0x100>;
51 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
52 };
53
54 serial@78af000 {
55 pinctrl-0 = <&serial_pins>;
56 pinctrl-names = "default";
57 status = "okay";
58 };
59
60 crypto@8e3a000 {
61 status = "okay";
62 };
63
64 watchdog@b017000 {
65 status = "okay";
66 };
67
68 ess-switch@c000000 {
69 status = "okay";
70 };
71
72 edma@c080000 {
73 status = "okay";
74 qcom,num_gmac = <1>;
75 };
76 };
77
78 aliases {
79 led-boot = &power_amber;
80 led-failsafe = &power_amber;
81 led-running = &power_green;
82 led-upgrade = &power_amber;
83 };
84
85 gpio-keys {
86 compatible = "gpio-keys";
87
88 wps {
89 label = "wps";
90 gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
91 linux,code = <KEY_WPS_BUTTON>;
92 };
93
94 reset {
95 label = "reset";
96 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
97 linux,code = <KEY_RESTART>;
98 };
99 };
100
101 led_spi {
102 compatible = "spi-gpio";
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 gpio-sck = <&tlmm 5 GPIO_ACTIVE_HIGH>;
107 gpio-mosi = <&tlmm 4 GPIO_ACTIVE_HIGH>;
108 num-chipselects = <0>;
109
110 led_gpio: led_gpio@0 {
111 compatible = "fairchild,74hc595";
112 reg = <0>;
113 gpio-controller;
114 #gpio-cells = <2>;
115 registers-number = <1>;
116 spi-max-frequency = <1000000>;
117 };
118 };
119
120 gpio-leds {
121 compatible = "gpio-leds";
122
123 power_amber: power_amber {
124 label = "ex61x0v2:amber:power";
125 gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
126 };
127
128 power_green: power_green {
129 label = "ex61x0v2:green:power";
130 gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
131 };
132
133 right {
134 label = "ex61x0v2:blue:right";
135 gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
136 };
137
138 left {
139 label = "ex61x0v2:blue:left";
140 gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
141 };
142
143 client_green {
144 label = "ex61x0v2:green:client";
145 gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
146 };
147
148 client_red {
149 label = "ex61x0v2:red:client";
150 gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
151 };
152
153 router_green {
154 label = "ex61x0v2:green:router";
155 gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
156 };
157
158 router_red {
159 label = "ex61x0v2:red:router";
160 gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
161 };
162
163 wps {
164 label = "ex61x0v2:green:wps";
165 gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
166 };
167 };
168 };
169
170 &tlmm {
171 serial_pins: serial_pinmux {
172 mux {
173 pins = "gpio60", "gpio61";
174 function = "blsp_uart0";
175 bias-disable;
176 };
177 };
178
179 spi_0_pins: spi_0_pinmux {
180 pin {
181 function = "blsp_spi0";
182 pins = "gpio55", "gpio56", "gpio57";
183 drive-strength = <12>;
184 bias-disable;
185 };
186 pin_cs {
187 function = "gpio";
188 pins = "gpio54";
189 drive-strength = <2>;
190 bias-disable;
191 output-high;
192 };
193 };
194 };
195
196 &blsp1_spi1 {
197 pinctrl-0 = <&spi_0_pins>;
198 pinctrl-names = "default";
199 status = "okay";
200 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
201
202 mx25l12805d@0 {
203 compatible = "jedec,spi-nor";
204 reg = <0>;
205 spi-max-frequency = <24000000>;
206
207 partitions {
208 compatible = "fixed-partitions";
209 #address-cells = <1>;
210 #size-cells = <1>;
211
212 partition0@0 {
213 label = "SBL1";
214 reg = <0x00000000 0x00040000>;
215 read-only;
216 };
217
218 partition1@40000 {
219 label = "MIBIB";
220 reg = <0x00040000 0x00020000>;
221 read-only;
222 };
223
224 partition2@60000 {
225 label = "QSEE";
226 reg = <0x00060000 0x00060000>;
227 read-only;
228 };
229
230 partition3@c0000 {
231 label = "CDT";
232 reg = <0x000c0000 0x00010000>;
233 read-only;
234 };
235
236 partition4@d0000 {
237 label = "DDRPARAMS";
238 reg = <0x000d0000 0x00010000>;
239 read-only;
240 };
241
242 partition5@E0000 {
243 label = "APPSBLENV";
244 reg = <0x000e0000 0x00010000>;
245 read-only;
246 };
247
248 partition6@F0000 {
249 label = "APPSBL";
250 reg = <0x000f0000 0x00080000>;
251 read-only;
252 };
253
254 partition7@170000 {
255 label = "ART";
256 reg = <0x00170000 0x00010000>;
257 read-only;
258 };
259
260 partition8@180000 {
261 label = "config";
262 reg = <0x00180000 0x00010000>;
263 read-only;
264 };
265
266 partition9@190000 {
267 label = "pot";
268 reg = <0x00190000 0x00010000>;
269 read-only;
270 };
271
272 partition10@1a0000 {
273 label = "dnidata";
274 reg = <0x001a0000 0x00010000>;
275 read-only;
276 };
277
278 partition11@1b0000 {
279 label = "firmware";
280 reg = <0x001b0000 0x00e10000>;
281 };
282
283 partition12@fc0000 {
284 label = "language";
285 reg = <0x00fc0000 0x00040000>;
286 read-only;
287 };
288 };
289 };
290 };
291
292 &blsp_dma {
293 status = "okay";
294 };
295
296 &cryptobam {
297 status = "okay";
298 };
299
300 &wifi0 {
301 status = "okay";
302 };
303
304 &wifi1 {
305 status = "okay";
306 };