target/linux/ipq40xx/patches-4.14/071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch

   1 From 364123029d8d547336323fbd3d659ecd0bba913f Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Mon, 23 Jul 2018 08:41:02 +0200
   4 Subject: [PATCH 5/8] qcom: ipq4019: use v2 of the kpss bringup mechanism
   5
   6 v1 was the incorrect choice here and sometimes the board
   7 would not come up properly.
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 ---
  13  arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
  14  1 file changed, 17 insertions(+), 8 deletions(-)
  15
  16 diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  17 index 93647db5d90b..06434fd02d40 100644
  18 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  19 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  20 @@ -52,7 +52,8 @@
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a7";
  24 -                       enable-method = "qcom,kpss-acc-v1";
  25 +                       enable-method = "qcom,kpss-acc-v2";
  26 +                       next-level-cache = <&L2>;
  27                         qcom,acc = <&acc0>;
  28                         qcom,saw = <&saw0>;
  29                         reg = <0x0>;
  30 @@ -71,7 +72,8 @@
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34 -                       enable-method = "qcom,kpss-acc-v1";
  35 +                       enable-method = "qcom,kpss-acc-v2";
  36 +                       next-level-cache = <&L2>;
  37                         qcom,acc = <&acc1>;
  38                         qcom,saw = <&saw1>;
  39                         reg = <0x1>;
  40 @@ -82,7 +84,8 @@
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44 -                       enable-method = "qcom,kpss-acc-v1";
  45 +                       enable-method = "qcom,kpss-acc-v2";
  46 +                       next-level-cache = <&L2>;
  47                         qcom,acc = <&acc2>;
  48                         qcom,saw = <&saw2>;
  49                         reg = <0x2>;
  50 @@ -93,13 +96,19 @@
  51                 cpu@3 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a7";
  54 -                       enable-method = "qcom,kpss-acc-v1";
  55 +                       enable-method = "qcom,kpss-acc-v2";
  56 +                       next-level-cache = <&L2>;
  57                         qcom,acc = <&acc3>;
  58                         qcom,saw = <&saw3>;
  59                         reg = <0x3>;
  60                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  61                         clock-frequency = <0>;
  62                 };
  63 +
  64 +               L2: l2-cache {
  65 +                       compatible = "cache";
  66 +                       cache-level = <2>;
  67 +               };
  68         };
  69
  70         pmu {
  71 @@ -268,22 +277,22 @@
  72                 };
  73
  74                  acc0: clock-controller@b088000 {
  75 -                        compatible = "qcom,kpss-acc-v1";
  76 +                       compatible = "qcom,kpss-acc-v2";
  77                          reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
  78                  };
  79
  80                  acc1: clock-controller@b098000 {
  81 -                        compatible = "qcom,kpss-acc-v1";
  82 +                       compatible = "qcom,kpss-acc-v2";
  83                          reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
  84                  };
  85
  86                  acc2: clock-controller@b0a8000 {
  87 -                        compatible = "qcom,kpss-acc-v1";
  88 +                       compatible = "qcom,kpss-acc-v2";
  89                          reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
  90                  };
  91
  92                  acc3: clock-controller@b0b8000 {
  93 -                        compatible = "qcom,kpss-acc-v1";
  94 +                       compatible = "qcom,kpss-acc-v2";
  95                          reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
  96                  };
  97
  98 --
  99 2.11.0
 100