target/linux/ipq40xx/patches-4.14/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch

   1 From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Fri, 8 Apr 2016 15:26:10 -0500
   4 Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
   5
   6 v1 was the incorrect choice here and sometimes the board
   7 would not come up properly.
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  11 ---
  12 Changes:
  13         - moved L2-Cache to be a subnode of cpu0
  14 ---
  15  arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
  16  1 file changed, 24 insertions(+), 8 deletions(-)
  17
  18 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  19 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  20 @@ -36,19 +36,27 @@
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a7";
  24 -                       enable-method = "qcom,kpss-acc-v1";
  25 +                       enable-method = "qcom,kpss-acc-v2";
  26 +                       next-level-cache = <&L2>;
  27                         qcom,acc = <&acc0>;
  28                         qcom,saw = <&saw0>;
  29                         reg = <0x0>;
  30                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  31                         clock-frequency = <0>;
  32                         operating-points-v2 = <&cpu0_opp_table>;
  33 +
  34 +                       L2: l2-cache {
  35 +                               compatible = "qcom,arch-cache";
  36 +                               cache-level = <2>;
  37 +                               qcom,saw = <&saw_l2>;
  38 +                       };
  39                 };
  40
  41                 cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44 -                       enable-method = "qcom,kpss-acc-v1";
  45 +                       enable-method = "qcom,kpss-acc-v2";
  46 +                       next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         reg = <0x1>;
  50 @@ -60,7 +68,8 @@
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a7";
  54 -                       enable-method = "qcom,kpss-acc-v1";
  55 +                       enable-method = "qcom,kpss-acc-v2";
  56 +                       next-level-cache = <&L2>;
  57                         qcom,acc = <&acc2>;
  58                         qcom,saw = <&saw2>;
  59                         reg = <0x2>;
  60 @@ -72,7 +81,8 @@
  61                 cpu@3 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a7";
  64 -                       enable-method = "qcom,kpss-acc-v1";
  65 +                       enable-method = "qcom,kpss-acc-v2";
  66 +                       next-level-cache = <&L2>;
  67                         qcom,acc = <&acc3>;
  68                         qcom,saw = <&saw3>;
  69                         reg = <0x3>;
  70 @@ -265,22 +275,22 @@
  71                 };
  72
  73                  acc0: clock-controller@b088000 {
  74 -                        compatible = "qcom,kpss-acc-v1";
  75 +                        compatible = "qcom,kpss-acc-v2";
  76                          reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
  77                  };
  78
  79                  acc1: clock-controller@b098000 {
  80 -                        compatible = "qcom,kpss-acc-v1";
  81 +                        compatible = "qcom,kpss-acc-v2";
  82                          reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
  83                  };
  84
  85                  acc2: clock-controller@b0a8000 {
  86 -                        compatible = "qcom,kpss-acc-v1";
  87 +                        compatible = "qcom,kpss-acc-v2";
  88                          reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
  89                  };
  90
  91                  acc3: clock-controller@b0b8000 {
  92 -                        compatible = "qcom,kpss-acc-v1";
  93 +                        compatible = "qcom,kpss-acc-v2";
  94                          reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
  95                  };
  96
  97 @@ -308,6 +318,12 @@
  98                          regulator;
  99                  };
 100
 101 +               saw_l2: regulator@b012000 {
 102 +                       compatible = "qcom,saw2";
 103 +                       reg = <0xb012000 0x1000>;
 104 +                       regulator;
 105 +               };
 106 +
 107                 serial@78af000 {
 108                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 109                         reg = <0x78af000 0x200>;