ipq40xx: add target
[openwrt/openwrt.git] / target / linux / ipq40xx / patches-4.14 / 310-msm-adhoc-bus-support.patch
1 From: Christian Lamparter <chunkeey@googlemail.com>
2 Subject: BUS: add MSM_BUS
3 --- a/drivers/bus/Makefile
4 +++ b/drivers/bus/Makefile
5 @@ -11,6 +11,7 @@ obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmst
6 obj-$(CONFIG_IMX_WEIM) += imx-weim.o
7 obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o
8 obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
9 +obj-$(CONFIG_BUS_TOPOLOGY_ADHOC)+= msm_bus/
10
11 # Interconnect bus driver for OMAP SoCs.
12 obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
13 --- a/drivers/bus/Kconfig
14 +++ b/drivers/bus/Kconfig
15 @@ -93,6 +93,8 @@ config MVEBU_MBUS
16 Driver needed for the MBus configuration on Marvell EBU SoCs
17 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
18
19 +source "drivers/bus/msm_bus/Kconfig"
20 +
21 config OMAP_INTERCONNECT
22 tristate "OMAP INTERCONNECT DRIVER"
23 depends on ARCH_OMAP2PLUS
24 --- /dev/null
25 +++ b/include/dt-bindings/msm/msm-bus-ids.h
26 @@ -0,0 +1,869 @@
27 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
28 + *
29 + * This program is free software; you can redistribute it and/or modify
30 + * it under the terms of the GNU General Public License version 2 and
31 + * only version 2 as published by the Free Software Foundation.
32 + *
33 + * This program is distributed in the hope that it will be useful,
34 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 + * GNU General Public License for more details.
37 + */
38 +
39 +#ifndef __MSM_BUS_IDS_H
40 +#define __MSM_BUS_IDS_H
41 +
42 +/* Topology related enums */
43 +#define MSM_BUS_FAB_DEFAULT 0
44 +#define MSM_BUS_FAB_APPSS 0
45 +#define MSM_BUS_FAB_SYSTEM 1024
46 +#define MSM_BUS_FAB_MMSS 2048
47 +#define MSM_BUS_FAB_SYSTEM_FPB 3072
48 +#define MSM_BUS_FAB_CPSS_FPB 4096
49 +
50 +#define MSM_BUS_FAB_BIMC 0
51 +#define MSM_BUS_FAB_SYS_NOC 1024
52 +#define MSM_BUS_FAB_MMSS_NOC 2048
53 +#define MSM_BUS_FAB_OCMEM_NOC 3072
54 +#define MSM_BUS_FAB_PERIPH_NOC 4096
55 +#define MSM_BUS_FAB_CONFIG_NOC 5120
56 +#define MSM_BUS_FAB_OCMEM_VNOC 6144
57 +#define MSM_BUS_FAB_MMSS_AHB 2049
58 +#define MSM_BUS_FAB_A0_NOC 6145
59 +#define MSM_BUS_FAB_A1_NOC 6146
60 +#define MSM_BUS_FAB_A2_NOC 6147
61 +
62 +#define MSM_BUS_MASTER_FIRST 1
63 +#define MSM_BUS_MASTER_AMPSS_M0 1
64 +#define MSM_BUS_MASTER_AMPSS_M1 2
65 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3
66 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
67 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
68 +#define MSM_BUS_MASTER_SPS 6
69 +#define MSM_BUS_MASTER_ADM_PORT0 7
70 +#define MSM_BUS_MASTER_ADM_PORT1 8
71 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
72 +#define MSM_BUS_MASTER_ADM1_PORT1 10
73 +#define MSM_BUS_MASTER_LPASS_PROC 11
74 +#define MSM_BUS_MASTER_MSS_PROCI 12
75 +#define MSM_BUS_MASTER_MSS_PROCD 13
76 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14
77 +#define MSM_BUS_MASTER_LPASS 15
78 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
79 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
80 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
81 +#define MSM_BUS_MASTER_ADM1_CI 19
82 +#define MSM_BUS_MASTER_ADM0_CI 20
83 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21
84 +#define MSM_BUS_MASTER_MDP_PORT0 22
85 +#define MSM_BUS_MASTER_MDP_PORT1 23
86 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
87 +#define MSM_BUS_MASTER_ROTATOR 25
88 +#define MSM_BUS_MASTER_GRAPHICS_3D 26
89 +#define MSM_BUS_MASTER_JPEG_DEC 27
90 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
91 +#define MSM_BUS_MASTER_VFE 29
92 +#define MSM_BUS_MASTER_VPE 30
93 +#define MSM_BUS_MASTER_JPEG_ENC 31
94 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
95 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33
96 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34
97 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35
98 +#define MSM_BUS_MASTER_SPDM 36
99 +#define MSM_BUS_MASTER_RPM 37
100 +#define MSM_BUS_MASTER_MSS 38
101 +#define MSM_BUS_MASTER_RIVA 39
102 +#define MSM_BUS_MASTER_SNOC_VMEM 40
103 +#define MSM_BUS_MASTER_MSS_SW_PROC 41
104 +#define MSM_BUS_MASTER_MSS_FW_PROC 42
105 +#define MSM_BUS_MASTER_HMSS 43
106 +#define MSM_BUS_MASTER_GSS_NAV 44
107 +#define MSM_BUS_MASTER_PCIE 45
108 +#define MSM_BUS_MASTER_SATA 46
109 +#define MSM_BUS_MASTER_CRYPTO 47
110 +#define MSM_BUS_MASTER_VIDEO_CAP 48
111 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
112 +#define MSM_BUS_MASTER_VIDEO_ENC 50
113 +#define MSM_BUS_MASTER_VIDEO_DEC 51
114 +#define MSM_BUS_MASTER_LPASS_AHB 52
115 +#define MSM_BUS_MASTER_QDSS_BAM 53
116 +#define MSM_BUS_MASTER_SNOC_CFG 54
117 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55
118 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56
119 +#define MSM_BUS_MASTER_MSS_NAV 57
120 +#define MSM_BUS_MASTER_OCMEM_DMA 58
121 +#define MSM_BUS_MASTER_WCSS 59
122 +#define MSM_BUS_MASTER_QDSS_ETR 60
123 +#define MSM_BUS_MASTER_USB3 61
124 +#define MSM_BUS_MASTER_JPEG 62
125 +#define MSM_BUS_MASTER_VIDEO_P0 63
126 +#define MSM_BUS_MASTER_VIDEO_P1 64
127 +#define MSM_BUS_MASTER_MSS_PROC 65
128 +#define MSM_BUS_MASTER_JPEG_OCMEM 66
129 +#define MSM_BUS_MASTER_MDP_OCMEM 67
130 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
131 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
132 +#define MSM_BUS_MASTER_VFE_OCMEM 70
133 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71
134 +#define MSM_BUS_MASTER_RPM_INST 72
135 +#define MSM_BUS_MASTER_RPM_DATA 73
136 +#define MSM_BUS_MASTER_RPM_SYS 74
137 +#define MSM_BUS_MASTER_DEHR 75
138 +#define MSM_BUS_MASTER_QDSS_DAP 76
139 +#define MSM_BUS_MASTER_TIC 77
140 +#define MSM_BUS_MASTER_SDCC_1 78
141 +#define MSM_BUS_MASTER_SDCC_3 79
142 +#define MSM_BUS_MASTER_SDCC_4 80
143 +#define MSM_BUS_MASTER_SDCC_2 81
144 +#define MSM_BUS_MASTER_TSIF 82
145 +#define MSM_BUS_MASTER_BAM_DMA 83
146 +#define MSM_BUS_MASTER_BLSP_2 84
147 +#define MSM_BUS_MASTER_USB_HSIC 85
148 +#define MSM_BUS_MASTER_BLSP_1 86
149 +#define MSM_BUS_MASTER_USB_HS 87
150 +#define MSM_BUS_MASTER_PNOC_CFG 88
151 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89
152 +#define MSM_BUS_MASTER_IPA 90
153 +#define MSM_BUS_MASTER_QPIC 91
154 +#define MSM_BUS_MASTER_MDPE 92
155 +#define MSM_BUS_MASTER_USB_HS2 93
156 +#define MSM_BUS_MASTER_VPU 94
157 +#define MSM_BUS_MASTER_UFS 95
158 +#define MSM_BUS_MASTER_BCAST 96
159 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97
160 +#define MSM_BUS_MASTER_EMAC 98
161 +#define MSM_BUS_MASTER_VPU_1 99
162 +#define MSM_BUS_MASTER_PCIE_1 100
163 +#define MSM_BUS_MASTER_USB3_1 101
164 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
165 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103
166 +#define MSM_BUS_MASTER_TCU_0 104
167 +#define MSM_BUS_MASTER_TCU_1 105
168 +#define MSM_BUS_MASTER_CPP 106
169 +#define MSM_BUS_MASTER_AUDIO 107
170 +#define MSM_BUS_MASTER_PCIE_2 108
171 +#define MSM_BUS_MASTER_BLSP_BAM 109
172 +#define MSM_BUS_MASTER_USB2_BAM 110
173 +#define MSM_BUS_MASTER_ADDS_DMA0 111
174 +#define MSM_BUS_MASTER_ADDS_DMA1 112
175 +#define MSM_BUS_MASTER_ADDS_DMA2 113
176 +#define MSM_BUS_MASTER_ADDS_DMA3 114
177 +#define MSM_BUS_MASTER_QPIC_BAM 115
178 +#define MSM_BUS_MASTER_SDCC_BAM 116
179 +#define MSM_BUS_MASTER_DDRC_SNOC 117
180 +#define MSM_BUS_MASTER_WSS_0 118
181 +#define MSM_BUS_MASTER_WSS_1 119
182 +#define MSM_BUS_MASTER_ESS 120
183 +#define MSM_BUS_MASTER_QDSS_BAMNDP 121
184 +#define MSM_BUS_MASTER_QDSS_SNOC_CFG 122
185 +#define MSM_BUS_MASTER_LAST 130
186 +
187 +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
188 +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
189 +
190 +#define MSM_BUS_SNOC_MM_INT_0 10000
191 +#define MSM_BUS_SNOC_MM_INT_1 10001
192 +#define MSM_BUS_SNOC_MM_INT_2 10002
193 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003
194 +#define MSM_BUS_SNOC_INT_0 10004
195 +#define MSM_BUS_SNOC_INT_1 10005
196 +#define MSM_BUS_SNOC_INT_BIMC 10006
197 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007
198 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008
199 +#define MSM_BUS_SNOC_QDSS_INT 10009
200 +#define MSM_BUS_PNOC_SNOC_MAS 10010
201 +#define MSM_BUS_PNOC_SNOC_SLV 10011
202 +#define MSM_BUS_PNOC_INT_0 10012
203 +#define MSM_BUS_PNOC_INT_1 10013
204 +#define MSM_BUS_PNOC_M_0 10014
205 +#define MSM_BUS_PNOC_M_1 10015
206 +#define MSM_BUS_BIMC_SNOC_MAS 10016
207 +#define MSM_BUS_BIMC_SNOC_SLV 10017
208 +#define MSM_BUS_PNOC_SLV_0 10018
209 +#define MSM_BUS_PNOC_SLV_1 10019
210 +#define MSM_BUS_PNOC_SLV_2 10020
211 +#define MSM_BUS_PNOC_SLV_3 10021
212 +#define MSM_BUS_PNOC_SLV_4 10022
213 +#define MSM_BUS_PNOC_SLV_8 10023
214 +#define MSM_BUS_PNOC_SLV_9 10024
215 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025
216 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026
217 +#define MSM_BUS_MNOC_BIMC_MAS 10027
218 +#define MSM_BUS_MNOC_BIMC_SLV 10028
219 +#define MSM_BUS_BIMC_MNOC_MAS 10029
220 +#define MSM_BUS_BIMC_MNOC_SLV 10030
221 +#define MSM_BUS_SNOC_BIMC_MAS 10031
222 +#define MSM_BUS_SNOC_BIMC_SLV 10032
223 +#define MSM_BUS_CNOC_SNOC_MAS 10033
224 +#define MSM_BUS_CNOC_SNOC_SLV 10034
225 +#define MSM_BUS_SNOC_CNOC_MAS 10035
226 +#define MSM_BUS_SNOC_CNOC_SLV 10036
227 +#define MSM_BUS_OVNOC_SNOC_MAS 10037
228 +#define MSM_BUS_OVNOC_SNOC_SLV 10038
229 +#define MSM_BUS_SNOC_OVNOC_MAS 10039
230 +#define MSM_BUS_SNOC_OVNOC_SLV 10040
231 +#define MSM_BUS_SNOC_PNOC_MAS 10041
232 +#define MSM_BUS_SNOC_PNOC_SLV 10042
233 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043
234 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044
235 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045
236 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046
237 +#define MSM_BUS_PNOC_SLV_5 10047
238 +#define MSM_BUS_PNOC_SLV_6 10048
239 +#define MSM_BUS_PNOC_INT_2 10049
240 +#define MSM_BUS_PNOC_INT_3 10050
241 +#define MSM_BUS_PNOC_INT_4 10051
242 +#define MSM_BUS_PNOC_INT_5 10052
243 +#define MSM_BUS_PNOC_INT_6 10053
244 +#define MSM_BUS_PNOC_INT_7 10054
245 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055
246 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056
247 +#define MSM_BUS_PNOC_A1NOC_MAS 10057
248 +#define MSM_BUS_PNOC_A1NOC_SLV 10058
249 +#define MSM_BUS_CNOC_A1NOC_MAS 10059
250 +#define MSM_BUS_A0NOC_SNOC_MAS 10060
251 +#define MSM_BUS_A0NOC_SNOC_SLV 10061
252 +#define MSM_BUS_A1NOC_SNOC_SLV 10062
253 +#define MSM_BUS_A1NOC_SNOC_MAS 10063
254 +#define MSM_BUS_A2NOC_SNOC_MAS 10064
255 +#define MSM_BUS_A2NOC_SNOC_SLV 10065
256 +#define MSM_BUS_PNOC_SLV_7 10066
257 +#define MSM_BUS_INT_LAST 10067
258 +
259 +#define MSM_BUS_SLAVE_FIRST 512
260 +#define MSM_BUS_SLAVE_EBI_CH0 512
261 +#define MSM_BUS_SLAVE_EBI_CH1 513
262 +#define MSM_BUS_SLAVE_AMPSS_L2 514
263 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
264 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
265 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
266 +#define MSM_BUS_SLAVE_SPS 518
267 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519
268 +#define MSM_BUS_SLAVE_AMPSS 520
269 +#define MSM_BUS_SLAVE_MSS 521
270 +#define MSM_BUS_SLAVE_LPASS 522
271 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
272 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
273 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
274 +#define MSM_BUS_SLAVE_CORESIGHT 526
275 +#define MSM_BUS_SLAVE_RIVA 527
276 +#define MSM_BUS_SLAVE_SMI 528
277 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529
278 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
279 +#define MSM_BUS_SLAVE_MM_IMEM 531
280 +#define MSM_BUS_SLAVE_CRYPTO 532
281 +#define MSM_BUS_SLAVE_SPDM 533
282 +#define MSM_BUS_SLAVE_RPM 534
283 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535
284 +#define MSM_BUS_SLAVE_MPM 536
285 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
286 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
287 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
288 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
289 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
290 +#define MSM_BUS_SLAVE_GSBI1_UART 542
291 +#define MSM_BUS_SLAVE_GSBI2_UART 543
292 +#define MSM_BUS_SLAVE_GSBI3_UART 544
293 +#define MSM_BUS_SLAVE_GSBI4_UART 545
294 +#define MSM_BUS_SLAVE_GSBI5_UART 546
295 +#define MSM_BUS_SLAVE_GSBI6_UART 547
296 +#define MSM_BUS_SLAVE_GSBI7_UART 548
297 +#define MSM_BUS_SLAVE_GSBI8_UART 549
298 +#define MSM_BUS_SLAVE_GSBI9_UART 550
299 +#define MSM_BUS_SLAVE_GSBI10_UART 551
300 +#define MSM_BUS_SLAVE_GSBI11_UART 552
301 +#define MSM_BUS_SLAVE_GSBI12_UART 553
302 +#define MSM_BUS_SLAVE_GSBI1_QUP 554
303 +#define MSM_BUS_SLAVE_GSBI2_QUP 555
304 +#define MSM_BUS_SLAVE_GSBI3_QUP 556
305 +#define MSM_BUS_SLAVE_GSBI4_QUP 557
306 +#define MSM_BUS_SLAVE_GSBI5_QUP 558
307 +#define MSM_BUS_SLAVE_GSBI6_QUP 559
308 +#define MSM_BUS_SLAVE_GSBI7_QUP 560
309 +#define MSM_BUS_SLAVE_GSBI8_QUP 561
310 +#define MSM_BUS_SLAVE_GSBI9_QUP 562
311 +#define MSM_BUS_SLAVE_GSBI10_QUP 563
312 +#define MSM_BUS_SLAVE_GSBI11_QUP 564
313 +#define MSM_BUS_SLAVE_GSBI12_QUP 565
314 +#define MSM_BUS_SLAVE_EBI2_NAND 566
315 +#define MSM_BUS_SLAVE_EBI2_CS0 567
316 +#define MSM_BUS_SLAVE_EBI2_CS1 568
317 +#define MSM_BUS_SLAVE_EBI2_CS2 569
318 +#define MSM_BUS_SLAVE_EBI2_CS3 570
319 +#define MSM_BUS_SLAVE_EBI2_CS4 571
320 +#define MSM_BUS_SLAVE_EBI2_CS5 572
321 +#define MSM_BUS_SLAVE_USB_FS1 573
322 +#define MSM_BUS_SLAVE_USB_FS2 574
323 +#define MSM_BUS_SLAVE_TSIF 575
324 +#define MSM_BUS_SLAVE_MSM_TSSC 576
325 +#define MSM_BUS_SLAVE_MSM_PDM 577
326 +#define MSM_BUS_SLAVE_MSM_DIMEM 578
327 +#define MSM_BUS_SLAVE_MSM_TCSR 579
328 +#define MSM_BUS_SLAVE_MSM_PRNG 580
329 +#define MSM_BUS_SLAVE_GSS 581
330 +#define MSM_BUS_SLAVE_SATA 582
331 +#define MSM_BUS_SLAVE_USB3 583
332 +#define MSM_BUS_SLAVE_WCSS 584
333 +#define MSM_BUS_SLAVE_OCIMEM 585
334 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586
335 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587
336 +#define MSM_BUS_SLAVE_QDSS_STM 588
337 +#define MSM_BUS_SLAVE_CAMERA_CFG 589
338 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590
339 +#define MSM_BUS_SLAVE_OCMEM_CFG 591
340 +#define MSM_BUS_SLAVE_CPR_CFG 592
341 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593
342 +#define MSM_BUS_SLAVE_MISC_CFG 594
343 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595
344 +#define MSM_BUS_SLAVE_VENUS_CFG 596
345 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597
346 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
347 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599
348 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
349 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601
350 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602
351 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603
352 +#define MSM_BUS_SLAVE_OCMEM 604
353 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605
354 +#define MSM_BUS_SLAVE_SDCC_1 606
355 +#define MSM_BUS_SLAVE_SDCC_3 607
356 +#define MSM_BUS_SLAVE_SDCC_2 608
357 +#define MSM_BUS_SLAVE_SDCC_4 609
358 +#define MSM_BUS_SLAVE_BAM_DMA 610
359 +#define MSM_BUS_SLAVE_BLSP_2 611
360 +#define MSM_BUS_SLAVE_USB_HSIC 612
361 +#define MSM_BUS_SLAVE_BLSP_1 613
362 +#define MSM_BUS_SLAVE_USB_HS 614
363 +#define MSM_BUS_SLAVE_PDM 615
364 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616
365 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617
366 +#define MSM_BUS_SLAVE_PRNG 618
367 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619
368 +#define MSM_BUS_SLAVE_CLK_CTL 620
369 +#define MSM_BUS_SLAVE_CNOC_MSS 621
370 +#define MSM_BUS_SLAVE_SECURITY 622
371 +#define MSM_BUS_SLAVE_TCSR 623
372 +#define MSM_BUS_SLAVE_TLMM 624
373 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625
374 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626
375 +#define MSM_BUS_SLAVE_IMEM_CFG 627
376 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628
377 +#define MSM_BUS_SLAVE_BIMC_CFG 629
378 +#define MSM_BUS_SLAVE_BOOT_ROM 630
379 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
380 +#define MSM_BUS_SLAVE_PMIC_ARB 632
381 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633
382 +#define MSM_BUS_SLAVE_DEHR_CFG 634
383 +#define MSM_BUS_SLAVE_QDSS_CFG 635
384 +#define MSM_BUS_SLAVE_RBCPR_CFG 636
385 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
386 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638
387 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
388 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
389 +#define MSM_BUS_SLAVE_PNOC_CFG 641
390 +#define MSM_BUS_SLAVE_SNOC_CFG 642
391 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643
392 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644
393 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645
394 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646
395 +#define MSM_BUS_SLAVE_IPS_CFG 647
396 +#define MSM_BUS_SLAVE_QPIC 648
397 +#define MSM_BUS_SLAVE_DSI_CFG 649
398 +#define MSM_BUS_SLAVE_UFS_CFG 650
399 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651
400 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652
401 +#define MSM_BUS_SLAVE_PCIE_CFG 653
402 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654
403 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
404 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656
405 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657
406 +#define MSM_BUS_SLAVE_VPU_CFG 658
407 +#define MSM_BUS_SLAVE_BCAST_CFG 659
408 +#define MSM_BUS_SLAVE_KLM_CFG 660
409 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661
410 +#define MSM_BUS_SLAVE_OCMEM_GFX 662
411 +#define MSM_BUS_SLAVE_CATS_128 663
412 +#define MSM_BUS_SLAVE_OCMEM_64 664
413 +#define MSM_BUS_SLAVE_PCIE_0 665
414 +#define MSM_BUS_SLAVE_PCIE_1 666
415 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667
416 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668
417 +#define MSM_BUS_SLAVE_SRVC_MNOC 669
418 +#define MSM_BUS_SLAVE_USB_HS2 670
419 +#define MSM_BUS_SLAVE_AUDIO 671
420 +#define MSM_BUS_SLAVE_TCU 672
421 +#define MSM_BUS_SLAVE_APPSS 673
422 +#define MSM_BUS_SLAVE_PCIE_PARF 674
423 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675
424 +#define MSM_BUS_SLAVE_IPA_CFG 676
425 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677
426 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678
427 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679
428 +#define MSM_BUS_SLAVE_HMSS_L3 680
429 +#define MSM_BUS_SLAVE_PIMEM_CFG 681
430 +#define MSM_BUS_SLAVE_DCC_CFG 682
431 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
432 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684
433 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
434 +#define MSM_BUS_SLAVE_A0NOC_CFG 686
435 +#define MSM_BUS_SLAVE_A1NOC_CFG 687
436 +#define MSM_BUS_SLAVE_A2NOC_CFG 688
437 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
438 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
439 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
440 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
441 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
442 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
443 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695
444 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
445 +#define MSM_BUS_SLAVE_SSC_CFG 697
446 +#define MSM_BUS_SLAVE_DSA_CFG 698
447 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699
448 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
449 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701
450 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
451 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703
452 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
453 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
454 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706
455 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
456 +#define MSM_BUS_SLAVE_VMEM_CFG 708
457 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 700
458 +#define MSM_BUS_SLAVE_VMEM 709
459 +#define MSM_BUS_SLAVE_AHB2PHY 710
460 +#define MSM_BUS_SLAVE_PIMEM 711
461 +#define MSM_BUS_SLAVE_SNOC_VMEM 712
462 +#define MSM_BUS_SLAVE_PCIE_2 713
463 +#define MSM_BUS_SLAVE_RBCPR_MX 714
464 +#define MSM_BUS_SLAVE_RBCPR_CX 715
465 +#define MSM_BUS_SLAVE_PRNG_APU_CFG 716
466 +#define MSM_BUS_SLAVE_PERIPH_MPU_CFG 717
467 +#define MSM_BUS_SLAVE_GCNT 718
468 +#define MSM_BUS_SLAVE_ADSS_CFG 719
469 +#define MSM_BUS_SLAVE_ADSS_VMIDMT_CFG 720
470 +#define MSM_BUS_SLAVE_QHSS_APU_CFG 721
471 +#define MSM_BUS_SLAVE_MDIO 722
472 +#define MSM_BUS_SLAVE_FEPHY_CFG 723
473 +#define MSM_BUS_SLAVE_SRIF 724
474 +#define MSM_BUS_SLAVE_LAST 730
475 +#define MSM_BUS_SLAVE_DDRC_CFG 731
476 +#define MSM_BUS_SLAVE_DDRC_APU_CFG 732
477 +#define MSM_BUS_SLAVE_MPU0_CFG 733
478 +#define MSM_BUS_SLAVE_MPU1_CFG 734
479 +#define MSM_BUS_SLAVE_MPU2_CFG 734
480 +#define MSM_BUS_SLAVE_ESS_VMIDMT_CFG 735
481 +#define MSM_BUS_SLAVE_ESS_APU_CFG 736
482 +#define MSM_BUS_SLAVE_USB2_CFG 737
483 +#define MSM_BUS_SLAVE_BLSP_CFG 738
484 +#define MSM_BUS_SLAVE_QPIC_CFG 739
485 +#define MSM_BUS_SLAVE_SDCC_CFG 740
486 +#define MSM_BUS_SLAVE_WSS0_VMIDMT_CFG 741
487 +#define MSM_BUS_SLAVE_WSS0_APU_CFG 742
488 +#define MSM_BUS_SLAVE_WSS1_VMIDMT_CFG 743
489 +#define MSM_BUS_SLAVE_WSS1_APU_CFG 744
490 +#define MSM_BUS_SLAVE_SRVC_PCNOC 745
491 +#define MSM_BUS_SLAVE_SNOC_DDRC 746
492 +#define MSM_BUS_SLAVE_A7SS 747
493 +#define MSM_BUS_SLAVE_WSS0_CFG 748
494 +#define MSM_BUS_SLAVE_WSS1_CFG 749
495 +#define MSM_BUS_SLAVE_PCIE 750
496 +#define MSM_BUS_SLAVE_USB3_CFG 751
497 +#define MSM_BUS_SLAVE_CRYPTO_CFG 752
498 +#define MSM_BUS_SLAVE_ESS_CFG 753
499 +#define MSM_BUS_SLAVE_SRVC_SNOC 754
500 +
501 +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
502 +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
503 +
504 +/*
505 + * ID's used in RPM messages
506 + */
507 +#define ICBID_MASTER_APPSS_PROC 0
508 +#define ICBID_MASTER_MSS_PROC 1
509 +#define ICBID_MASTER_MNOC_BIMC 2
510 +#define ICBID_MASTER_SNOC_BIMC 3
511 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
512 +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
513 +#define ICBID_MASTER_CNOC_MNOC_CFG 5
514 +#define ICBID_MASTER_GFX3D 6
515 +#define ICBID_MASTER_JPEG 7
516 +#define ICBID_MASTER_MDP 8
517 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
518 +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
519 +#define ICBID_MASTER_VIDEO 9
520 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
521 +#define ICBID_MASTER_VIDEO_P1 10
522 +#define ICBID_MASTER_VFE 11
523 +#define ICBID_MASTER_CNOC_ONOC_CFG 12
524 +#define ICBID_MASTER_JPEG_OCMEM 13
525 +#define ICBID_MASTER_MDP_OCMEM 14
526 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15
527 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16
528 +#define ICBID_MASTER_VFE_OCMEM 17
529 +#define ICBID_MASTER_LPASS_AHB 18
530 +#define ICBID_MASTER_QDSS_BAM 19
531 +#define ICBID_MASTER_SNOC_CFG 20
532 +#define ICBID_MASTER_BIMC_SNOC 21
533 +#define ICBID_MASTER_CNOC_SNOC 22
534 +#define ICBID_MASTER_CRYPTO 23
535 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
536 +#define ICBID_MASTER_CRYPTO_CORE1 24
537 +#define ICBID_MASTER_LPASS_PROC 25
538 +#define ICBID_MASTER_MSS 26
539 +#define ICBID_MASTER_MSS_NAV 27
540 +#define ICBID_MASTER_OCMEM_DMA 28
541 +#define ICBID_MASTER_PNOC_SNOC 29
542 +#define ICBID_MASTER_WCSS 30
543 +#define ICBID_MASTER_QDSS_ETR 31
544 +#define ICBID_MASTER_USB3 32
545 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
546 +#define ICBID_MASTER_SDCC_1 33
547 +#define ICBID_MASTER_SDCC_3 34
548 +#define ICBID_MASTER_SDCC_2 35
549 +#define ICBID_MASTER_SDCC_4 36
550 +#define ICBID_MASTER_TSIF 37
551 +#define ICBID_MASTER_BAM_DMA 38
552 +#define ICBID_MASTER_BLSP_2 39
553 +#define ICBID_MASTER_USB_HSIC 40
554 +#define ICBID_MASTER_BLSP_1 41
555 +#define ICBID_MASTER_USB_HS 42
556 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
557 +#define ICBID_MASTER_PNOC_CFG 43
558 +#define ICBID_MASTER_SNOC_PNOC 44
559 +#define ICBID_MASTER_RPM_INST 45
560 +#define ICBID_MASTER_RPM_DATA 46
561 +#define ICBID_MASTER_RPM_SYS 47
562 +#define ICBID_MASTER_DEHR 48
563 +#define ICBID_MASTER_QDSS_DAP 49
564 +#define ICBID_MASTER_SPDM 50
565 +#define ICBID_MASTER_TIC 51
566 +#define ICBID_MASTER_SNOC_CNOC 52
567 +#define ICBID_MASTER_GFX3D_OCMEM 53
568 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
569 +#define ICBID_MASTER_OVIRT_SNOC 54
570 +#define ICBID_MASTER_SNOC_OVIRT 55
571 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
572 +#define ICBID_MASTER_ONOC_OVIRT 56
573 +#define ICBID_MASTER_USB_HS2 57
574 +#define ICBID_MASTER_QPIC 58
575 +#define ICBID_MASTER_IPA 59
576 +#define ICBID_MASTER_DSI 60
577 +#define ICBID_MASTER_MDP1 61
578 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
579 +#define ICBID_MASTER_VPU_PROC 62
580 +#define ICBID_MASTER_VPU 63
581 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
582 +#define ICBID_MASTER_CRYPTO_CORE2 64
583 +#define ICBID_MASTER_PCIE_0 65
584 +#define ICBID_MASTER_PCIE_1 66
585 +#define ICBID_MASTER_SATA 67
586 +#define ICBID_MASTER_UFS 68
587 +#define ICBID_MASTER_USB3_1 69
588 +#define ICBID_MASTER_VIDEO_OCMEM 70
589 +#define ICBID_MASTER_VPU1 71
590 +#define ICBID_MASTER_VCAP 72
591 +#define ICBID_MASTER_EMAC 73
592 +#define ICBID_MASTER_BCAST 74
593 +#define ICBID_MASTER_MMSS_PROC 75
594 +#define ICBID_MASTER_SNOC_BIMC_1 76
595 +#define ICBID_MASTER_SNOC_PCNOC 77
596 +#define ICBID_MASTER_AUDIO 78
597 +#define ICBID_MASTER_MM_INT_0 79
598 +#define ICBID_MASTER_MM_INT_1 80
599 +#define ICBID_MASTER_MM_INT_2 81
600 +#define ICBID_MASTER_MM_INT_BIMC 82
601 +#define ICBID_MASTER_MSS_INT 83
602 +#define ICBID_MASTER_PCNOC_CFG 84
603 +#define ICBID_MASTER_PCNOC_INT_0 85
604 +#define ICBID_MASTER_PCNOC_INT_1 86
605 +#define ICBID_MASTER_PCNOC_M_0 87
606 +#define ICBID_MASTER_PCNOC_M_1 88
607 +#define ICBID_MASTER_PCNOC_S_0 89
608 +#define ICBID_MASTER_PCNOC_S_1 90
609 +#define ICBID_MASTER_PCNOC_S_2 91
610 +#define ICBID_MASTER_PCNOC_S_3 92
611 +#define ICBID_MASTER_PCNOC_S_4 93
612 +#define ICBID_MASTER_PCNOC_S_6 94
613 +#define ICBID_MASTER_PCNOC_S_7 95
614 +#define ICBID_MASTER_PCNOC_S_8 96
615 +#define ICBID_MASTER_PCNOC_S_9 97
616 +#define ICBID_MASTER_QDSS_INT 98
617 +#define ICBID_MASTER_SNOC_INT_0 99
618 +#define ICBID_MASTER_SNOC_INT_1 100
619 +#define ICBID_MASTER_SNOC_INT_BIMC 101
620 +#define ICBID_MASTER_TCU_0 102
621 +#define ICBID_MASTER_TCU_1 103
622 +#define ICBID_MASTER_BIMC_INT_0 104
623 +#define ICBID_MASTER_BIMC_INT_1 105
624 +#define ICBID_MASTER_CAMERA 106
625 +#define ICBID_MASTER_RICA 107
626 +#define ICBID_MASTER_PCNOC_S_5 129
627 +#define ICBID_MASTER_PCNOC_INT_2 124
628 +#define ICBID_MASTER_PCNOC_INT_3 125
629 +#define ICBID_MASTER_PCNOC_INT_4 126
630 +#define ICBID_MASTER_PCNOC_INT_5 127
631 +#define ICBID_MASTER_PCNOC_INT_6 128
632 +#define ICBID_MASTER_PCIE_2 119
633 +#define ICBID_MASTER_MASTER_CNOC_A1NOC 116
634 +#define ICBID_MASTER_A0NOC_SNOC 110
635 +#define ICBID_MASTER_A1NOC_SNOC 111
636 +#define ICBID_MASTER_A2NOC_SNOC 112
637 +#define ICBID_MASTER_PNOC_A1NOC 117
638 +#define ICBID_MASTER_ROTATOR 120
639 +#define ICBID_MASTER_SNOC_VMEM 114
640 +#define ICBID_MASTER_VENUS_VMEM 121
641 +#define ICBID_MASTER_HMSS 118
642 +#define ICBID_MASTER_BIMC_SNOC_1 109
643 +#define ICBID_MASTER_CNOC_A1NOC 116
644 +#define ICBID_MASTER_CPP 115
645 +#define ICBID_MASTER_BLSP_BAM 130
646 +#define ICBID_MASTER_USB2_BAM 131
647 +#define ICBID_MASTER_ADSS_DMA0 132
648 +#define ICBID_MASTER_ADSS_DMA1 133
649 +#define ICBID_MASTER_ADSS_DMA2 134
650 +#define ICBID_MASTER_ADSS_DMA3 135
651 +#define ICBID_MASTER_QPIC_BAM 136
652 +#define ICBID_MASTER_SDCC_BAM 137
653 +#define ICBID_MASTER_DDRC_SNOC 138
654 +#define ICBID_MASTER_WSS_0 139
655 +#define ICBID_MASTER_WSS_1 140
656 +#define ICBID_MASTER_ESS 141
657 +#define ICBID_MASTER_PCIE 142
658 +#define ICBID_MASTER_QDSS_BAMNDP 143
659 +#define ICBID_MASTER_QDSS_SNOC_CFG 144
660 +
661 +#define ICBID_SLAVE_EBI1 0
662 +#define ICBID_SLAVE_APPSS_L2 1
663 +#define ICBID_SLAVE_BIMC_SNOC 2
664 +#define ICBID_SLAVE_CAMERA_CFG 3
665 +#define ICBID_SLAVE_DISPLAY_CFG 4
666 +#define ICBID_SLAVE_OCMEM_CFG 5
667 +#define ICBID_SLAVE_CPR_CFG 6
668 +#define ICBID_SLAVE_CPR_XPU_CFG 7
669 +#define ICBID_SLAVE_MISC_CFG 8
670 +#define ICBID_SLAVE_MISC_XPU_CFG 9
671 +#define ICBID_SLAVE_VENUS_CFG 10
672 +#define ICBID_SLAVE_GFX3D_CFG 11
673 +#define ICBID_SLAVE_MMSS_CLK_CFG 12
674 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
675 +#define ICBID_SLAVE_MNOC_MPU_CFG 14
676 +#define ICBID_SLAVE_ONOC_MPU_CFG 15
677 +#define ICBID_SLAVE_MNOC_BIMC 16
678 +#define ICBID_SLAVE_SERVICE_MNOC 17
679 +#define ICBID_SLAVE_OCMEM 18
680 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
681 +#define ICBID_SLAVE_SERVICE_ONOC 19
682 +#define ICBID_SLAVE_APPSS 20
683 +#define ICBID_SLAVE_LPASS 21
684 +#define ICBID_SLAVE_USB3 22
685 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
686 +#define ICBID_SLAVE_WCSS 23
687 +#define ICBID_SLAVE_SNOC_BIMC 24
688 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
689 +#define ICBID_SLAVE_SNOC_CNOC 25
690 +#define ICBID_SLAVE_IMEM 26
691 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
692 +#define ICBID_SLAVE_SNOC_OVIRT 27
693 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
694 +#define ICBID_SLAVE_SNOC_PNOC 28
695 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
696 +#define ICBID_SLAVE_SERVICE_SNOC 29
697 +#define ICBID_SLAVE_QDSS_STM 30
698 +#define ICBID_SLAVE_SDCC_1 31
699 +#define ICBID_SLAVE_SDCC_3 32
700 +#define ICBID_SLAVE_SDCC_2 33
701 +#define ICBID_SLAVE_SDCC_4 34
702 +#define ICBID_SLAVE_TSIF 35
703 +#define ICBID_SLAVE_BAM_DMA 36
704 +#define ICBID_SLAVE_BLSP_2 37
705 +#define ICBID_SLAVE_USB_HSIC 38
706 +#define ICBID_SLAVE_BLSP_1 39
707 +#define ICBID_SLAVE_USB_HS 40
708 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
709 +#define ICBID_SLAVE_PDM 41
710 +#define ICBID_SLAVE_PERIPH_APU_CFG 42
711 +#define ICBID_SLAVE_PNOC_MPU_CFG 43
712 +#define ICBID_SLAVE_PRNG 44
713 +#define ICBID_SLAVE_PNOC_SNOC 45
714 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
715 +#define ICBID_SLAVE_SERVICE_PNOC 46
716 +#define ICBID_SLAVE_CLK_CTL 47
717 +#define ICBID_SLAVE_CNOC_MSS 48
718 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
719 +#define ICBID_SLAVE_SECURITY 49
720 +#define ICBID_SLAVE_TCSR 50
721 +#define ICBID_SLAVE_TLMM 51
722 +#define ICBID_SLAVE_CRYPTO_0_CFG 52
723 +#define ICBID_SLAVE_CRYPTO_1_CFG 53
724 +#define ICBID_SLAVE_IMEM_CFG 54
725 +#define ICBID_SLAVE_MESSAGE_RAM 55
726 +#define ICBID_SLAVE_BIMC_CFG 56
727 +#define ICBID_SLAVE_BOOT_ROM 57
728 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
729 +#define ICBID_SLAVE_PMIC_ARB 59
730 +#define ICBID_SLAVE_SPDM_WRAPPER 60
731 +#define ICBID_SLAVE_DEHR_CFG 61
732 +#define ICBID_SLAVE_MPM 62
733 +#define ICBID_SLAVE_QDSS_CFG 63
734 +#define ICBID_SLAVE_RBCPR_CFG 64
735 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
736 +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
737 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66
738 +#define ICBID_SLAVE_SNOC_MPU_CFG 67
739 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68
740 +#define ICBID_SLAVE_PNOC_CFG 69
741 +#define ICBID_SLAVE_SNOC_CFG 70
742 +#define ICBID_SLAVE_EBI1_DLL_CFG 71
743 +#define ICBID_SLAVE_PHY_APU_CFG 72
744 +#define ICBID_SLAVE_EBI1_PHY_CFG 73
745 +#define ICBID_SLAVE_RPM 74
746 +#define ICBID_SLAVE_CNOC_SNOC 75
747 +#define ICBID_SLAVE_SERVICE_CNOC 76
748 +#define ICBID_SLAVE_OVIRT_SNOC 77
749 +#define ICBID_SLAVE_OVIRT_OCMEM 78
750 +#define ICBID_SLAVE_USB_HS2 79
751 +#define ICBID_SLAVE_QPIC 80
752 +#define ICBID_SLAVE_IPS_CFG 81
753 +#define ICBID_SLAVE_DSI_CFG 82
754 +#define ICBID_SLAVE_USB3_1 83
755 +#define ICBID_SLAVE_PCIE_0 84
756 +#define ICBID_SLAVE_PCIE_1 85
757 +#define ICBID_SLAVE_PSS_SMMU_CFG 86
758 +#define ICBID_SLAVE_CRYPTO_2_CFG 87
759 +#define ICBID_SLAVE_PCIE_0_CFG 88
760 +#define ICBID_SLAVE_PCIE_1_CFG 89
761 +#define ICBID_SLAVE_SATA_CFG 90
762 +#define ICBID_SLAVE_SPSS_GENI_IR 91
763 +#define ICBID_SLAVE_UFS_CFG 92
764 +#define ICBID_SLAVE_AVSYNC_CFG 93
765 +#define ICBID_SLAVE_VPU_CFG 94
766 +#define ICBID_SLAVE_USB_PHY_CFG 95
767 +#define ICBID_SLAVE_RBCPR_MX_CFG 96
768 +#define ICBID_SLAVE_PCIE_PARF 97
769 +#define ICBID_SLAVE_VCAP_CFG 98
770 +#define ICBID_SLAVE_EMAC_CFG 99
771 +#define ICBID_SLAVE_BCAST_CFG 100
772 +#define ICBID_SLAVE_KLM_CFG 101
773 +#define ICBID_SLAVE_DISPLAY_PWM 102
774 +#define ICBID_SLAVE_GENI 103
775 +#define ICBID_SLAVE_SNOC_BIMC_1 104
776 +#define ICBID_SLAVE_AUDIO 105
777 +#define ICBID_SLAVE_CATS_0 106
778 +#define ICBID_SLAVE_CATS_1 107
779 +#define ICBID_SLAVE_MM_INT_0 108
780 +#define ICBID_SLAVE_MM_INT_1 109
781 +#define ICBID_SLAVE_MM_INT_2 110
782 +#define ICBID_SLAVE_MM_INT_BIMC 111
783 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
784 +#define ICBID_SLAVE_MSS_INT 113
785 +#define ICBID_SLAVE_PCNOC_INT_0 114
786 +#define ICBID_SLAVE_PCNOC_INT_1 115
787 +#define ICBID_SLAVE_PCNOC_M_0 116
788 +#define ICBID_SLAVE_PCNOC_M_1 117
789 +#define ICBID_SLAVE_PCNOC_S_0 118
790 +#define ICBID_SLAVE_PCNOC_S_1 119
791 +#define ICBID_SLAVE_PCNOC_S_2 120
792 +#define ICBID_SLAVE_PCNOC_S_3 121
793 +#define ICBID_SLAVE_PCNOC_S_4 122
794 +#define ICBID_SLAVE_PCNOC_S_6 123
795 +#define ICBID_SLAVE_PCNOC_S_7 124
796 +#define ICBID_SLAVE_PCNOC_S_8 125
797 +#define ICBID_SLAVE_PCNOC_S_9 126
798 +#define ICBID_SLAVE_PRNG_XPU_CFG 127
799 +#define ICBID_SLAVE_QDSS_INT 128
800 +#define ICBID_SLAVE_RPM_XPU_CFG 129
801 +#define ICBID_SLAVE_SNOC_INT_0 130
802 +#define ICBID_SLAVE_SNOC_INT_1 131
803 +#define ICBID_SLAVE_SNOC_INT_BIMC 132
804 +#define ICBID_SLAVE_TCU 133
805 +#define ICBID_SLAVE_BIMC_INT_0 134
806 +#define ICBID_SLAVE_BIMC_INT_1 135
807 +#define ICBID_SLAVE_RICA_CFG 136
808 +#define ICBID_SLAVE_PCNOC_S_5 189
809 +#define ICBID_SLAVE_PCNOC_S_7 124
810 +#define ICBID_SLAVE_PCNOC_INT_2 184
811 +#define ICBID_SLAVE_PCNOC_INT_3 185
812 +#define ICBID_SLAVE_PCNOC_INT_4 186
813 +#define ICBID_SLAVE_PCNOC_INT_5 187
814 +#define ICBID_SLAVE_PCNOC_INT_6 188
815 +#define ICBID_SLAVE_USB3_PHY_CFG 182
816 +#define ICBID_SLAVE_IPA_CFG 183
817 +
818 +#define ICBID_SLAVE_A0NOC_SNOC 141
819 +#define ICBID_SLAVE_A1NOC_SNOC 142
820 +#define ICBID_SLAVE_A2NOC_SNOC 143
821 +#define ICBID_SLAVE_BIMC_SNOC_1 138
822 +#define ICBID_SLAVE_PIMEM 167
823 +#define ICBID_SLAVE_PIMEM_CFG 168
824 +#define ICBID_SLAVE_DCC_CFG 155
825 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
826 +#define ICBID_SLAVE_A0NOC_CFG 144
827 +#define ICBID_SLAVE_PCIE_2_CFG 165
828 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163
829 +#define ICBID_SLAVE_PCIE_2 164
830 +#define ICBID_SLAVE_A1NOC_CFG 147
831 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148
832 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
833 +#define ICBID_SLAVE_A2NOC_CFG 150
834 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151
835 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
836 +#define ICBID_SLAVE_AHB2PHY 153
837 +#define ICBID_SLAVE_HMSS_L3 161
838 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161
839 +#define ICBID_SLAVE_MMAGIC_CFG 162
840 +#define ICBID_SLAVE_SSC_CFG 177
841 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
842 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
843 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
844 +#define ICBID_SLAVE_DSA_CFG 157
845 +#define ICBID_SLAVE_DSA_MPU_CFG 158
846 +#define ICBID_SLAVE_SMMU_CPP_CFG 171
847 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172
848 +#define ICBID_SLAVE_SMMU_MDP_CFG 173
849 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
850 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175
851 +#define ICBID_SLAVE_SMMU_VFE_CFG 176
852 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145
853 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
854 +#define ICBID_SLAVE_VMEM_CFG 180
855 +#define ICBID_SLAVE_VMEM 179
856 +#define ICBID_SLAVE_PNOC_A1NOC 139
857 +#define ICBID_SLAVE_SNOC_VMEM 140
858 +#define ICBID_SLAVE_RBCPR_MX 170
859 +#define ICBID_SLAVE_RBCPR_CX 169
860 +#define ICBID_SLAVE_PRNG_APU_CFG 190
861 +#define ICBID_SLAVE_PERIPH_MPU_CFG 191
862 +#define ICBID_SLAVE_GCNT 192
863 +#define ICBID_SLAVE_ADSS_CFG 193
864 +#define ICBID_SLAVE_ADSS_APU 194
865 +#define ICBID_SLAVE_ADSS_VMIDMT_CFG 195
866 +#define ICBID_SLAVE_QHSS_APU_CFG 196
867 +#define ICBID_SLAVE_MDIO 197
868 +#define ICBID_SLAVE_FEPHY_CFG 198
869 +#define ICBID_SLAVE_SRIF 199
870 +#define ICBID_SLAVE_DDRC_CFG 200
871 +#define ICBID_SLAVE_DDRC_APU_CFG 201
872 +#define ICBID_SLAVE_DDRC_MPU0_CFG 202
873 +#define ICBID_SLAVE_DDRC_MPU1_CFG 203
874 +#define ICBID_SLAVE_DDRC_MPU2_CFG 210
875 +#define ICBID_SLAVE_ESS_VMIDMT_CFG 211
876 +#define ICBID_SLAVE_ESS_APU_CFG 212
877 +#define ICBID_SLAVE_USB2_CFG 213
878 +#define ICBID_SLAVE_BLSP_CFG 214
879 +#define ICBID_SLAVE_QPIC_CFG 215
880 +#define ICBID_SLAVE_SDCC_CFG 216
881 +#define ICBID_SLAVE_WSS0_VMIDMT_CFG 217
882 +#define ICBID_SLAVE_WSS0_APU_CFG 218
883 +#define ICBID_SLAVE_WSS1_VMIDMT_CFG 219
884 +#define ICBID_SLAVE_WSS1_APU_CFG 220
885 +#define ICBID_SLAVE_SRVC_PCNOC 221
886 +#define ICBID_SLAVE_SNOC_DDRC 222
887 +#define ICBID_SLAVE_A7SS 223
888 +#define ICBID_SLAVE_WSS0_CFG 224
889 +#define ICBID_SLAVE_WSS1_CFG 225
890 +#define ICBID_SLAVE_PCIE 226
891 +#define ICBID_SLAVE_USB3_CFG 227
892 +#define ICBID_SLAVE_CRYPTO_CFG 228
893 +#define ICBID_SLAVE_ESS_CFG 229
894 +#define ICBID_SLAVE_SRVC_SNOC 230
895 +#endif
896 --- /dev/null
897 +++ b/include/dt-bindings/msm/msm-bus-rule-ops.h
898 @@ -0,0 +1,32 @@
899 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
900 + *
901 + * This program is free software; you can redistribute it and/or modify
902 + * it under the terms of the GNU General Public License version 2 and
903 + * only version 2 as published by the Free Software Foundation.
904 + *
905 + * This program is distributed in the hope that it will be useful,
906 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
907 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
908 + * GNU General Public License for more details.
909 + */
910 +
911 +#ifndef __MSM_BUS_RULE_OPS_H
912 +#define __MSM_BUS_RULE_OPS_H
913 +
914 +#define FLD_IB 0
915 +#define FLD_AB 1
916 +#define FLD_CLK 2
917 +
918 +#define OP_LE 0
919 +#define OP_LT 1
920 +#define OP_GE 2
921 +#define OP_GT 3
922 +#define OP_NOOP 4
923 +
924 +#define RULE_STATE_NOT_APPLIED 0
925 +#define RULE_STATE_APPLIED 1
926 +
927 +#define THROTTLE_ON 0
928 +#define THROTTLE_OFF 1
929 +
930 +#endif
931 --- /dev/null
932 +++ b/drivers/bus/msm_bus/Kconfig
933 @@ -0,0 +1,19 @@
934 +config BUS_TOPOLOGY_ADHOC
935 + bool "ad-hoc bus scaling topology"
936 + depends on ARCH_QCOM
937 + default n
938 + help
939 + This option enables a driver that can handle adhoc bus topologies.
940 + Adhoc bus topology driver allows one to many connections and maintains
941 + directionality of connections by explicitly listing device connections
942 + thus avoiding illegal routes.
943 +
944 +config MSM_BUS_SCALING
945 + bool "Bus scaling driver"
946 + depends on BUS_TOPOLOGY_ADHOC
947 + default n
948 + help
949 + This option enables bus scaling on MSM devices. Bus scaling
950 + allows devices to request the clocks be set to rates sufficient
951 + for the active devices needs without keeping the clocks at max
952 + frequency when a slower speed is sufficient.
953 --- /dev/null
954 +++ b/drivers/bus/msm_bus/Makefile
955 @@ -0,0 +1,12 @@
956 +#
957 +# Makefile for msm-bus driver specific files
958 +#
959 +obj-y += msm_bus_bimc.o msm_bus_noc.o msm_bus_core.o msm_bus_client_api.o \
960 + msm_bus_id.o
961 +obj-$(CONFIG_OF) += msm_bus_of.o
962 +
963 +obj-y += msm_bus_fabric_adhoc.o msm_bus_arb_adhoc.o msm_bus_rules.o
964 +obj-$(CONFIG_OF) += msm_bus_of_adhoc.o
965 +obj-$(CONFIG_CORESIGHT) += msm_buspm_coresight_adhoc.o
966 +
967 +obj-$(CONFIG_DEBUG_FS) += msm_bus_dbg.o
968 --- /dev/null
969 +++ b/drivers/bus/msm_bus/msm-bus-board.h
970 @@ -0,0 +1,198 @@
971 +/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
972 + *
973 + * This program is free software; you can redistribute it and/or modify
974 + * it under the terms of the GNU General Public License version 2 and
975 + * only version 2 as published by the Free Software Foundation.
976 + *
977 + * This program is distributed in the hope that it will be useful,
978 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
979 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
980 + * GNU General Public License for more details.
981 + */
982 +
983 +#ifndef __ASM_ARCH_MSM_BUS_BOARD_H
984 +#define __ASM_ARCH_MSM_BUS_BOARD_H
985 +
986 +#include <linux/types.h>
987 +#include <linux/input.h>
988 +
989 +enum context {
990 + DUAL_CTX,
991 + ACTIVE_CTX,
992 + NUM_CTX
993 +};
994 +
995 +struct msm_bus_fabric_registration {
996 + unsigned int id;
997 + const char *name;
998 + struct msm_bus_node_info *info;
999 + unsigned int len;
1000 + int ahb;
1001 + const char *fabclk[NUM_CTX];
1002 + const char *iface_clk;
1003 + unsigned int offset;
1004 + unsigned int haltid;
1005 + unsigned int rpm_enabled;
1006 + unsigned int nmasters;
1007 + unsigned int nslaves;
1008 + unsigned int ntieredslaves;
1009 + bool il_flag;
1010 + const struct msm_bus_board_algorithm *board_algo;
1011 + int hw_sel;
1012 + void *hw_data;
1013 + uint32_t qos_freq;
1014 + uint32_t qos_baseoffset;
1015 + u64 nr_lim_thresh;
1016 + uint32_t eff_fact;
1017 + uint32_t qos_delta;
1018 + bool virt;
1019 +};
1020 +
1021 +struct msm_bus_device_node_registration {
1022 + struct msm_bus_node_device_type *info;
1023 + unsigned int num_devices;
1024 + bool virt;
1025 +};
1026 +
1027 +enum msm_bus_bw_tier_type {
1028 + MSM_BUS_BW_TIER1 = 1,
1029 + MSM_BUS_BW_TIER2,
1030 + MSM_BUS_BW_COUNT,
1031 + MSM_BUS_BW_SIZE = 0x7FFFFFFF,
1032 +};
1033 +
1034 +struct msm_bus_halt_vector {
1035 + uint32_t haltval;
1036 + uint32_t haltmask;
1037 +};
1038 +
1039 +extern struct msm_bus_fabric_registration msm_bus_apps_fabric_pdata;
1040 +extern struct msm_bus_fabric_registration msm_bus_sys_fabric_pdata;
1041 +extern struct msm_bus_fabric_registration msm_bus_mm_fabric_pdata;
1042 +extern struct msm_bus_fabric_registration msm_bus_sys_fpb_pdata;
1043 +extern struct msm_bus_fabric_registration msm_bus_cpss_fpb_pdata;
1044 +extern struct msm_bus_fabric_registration msm_bus_def_fab_pdata;
1045 +
1046 +extern struct msm_bus_fabric_registration msm_bus_8960_apps_fabric_pdata;
1047 +extern struct msm_bus_fabric_registration msm_bus_8960_sys_fabric_pdata;
1048 +extern struct msm_bus_fabric_registration msm_bus_8960_mm_fabric_pdata;
1049 +extern struct msm_bus_fabric_registration msm_bus_8960_sg_mm_fabric_pdata;
1050 +extern struct msm_bus_fabric_registration msm_bus_8960_sys_fpb_pdata;
1051 +extern struct msm_bus_fabric_registration msm_bus_8960_cpss_fpb_pdata;
1052 +
1053 +extern struct msm_bus_fabric_registration msm_bus_8064_apps_fabric_pdata;
1054 +extern struct msm_bus_fabric_registration msm_bus_8064_sys_fabric_pdata;
1055 +extern struct msm_bus_fabric_registration msm_bus_8064_mm_fabric_pdata;
1056 +extern struct msm_bus_fabric_registration msm_bus_8064_sys_fpb_pdata;
1057 +extern struct msm_bus_fabric_registration msm_bus_8064_cpss_fpb_pdata;
1058 +
1059 +extern struct msm_bus_fabric_registration msm_bus_9615_sys_fabric_pdata;
1060 +extern struct msm_bus_fabric_registration msm_bus_9615_def_fab_pdata;
1061 +
1062 +extern struct msm_bus_fabric_registration msm_bus_8930_apps_fabric_pdata;
1063 +extern struct msm_bus_fabric_registration msm_bus_8930_sys_fabric_pdata;
1064 +extern struct msm_bus_fabric_registration msm_bus_8930_mm_fabric_pdata;
1065 +extern struct msm_bus_fabric_registration msm_bus_8930_sys_fpb_pdata;
1066 +extern struct msm_bus_fabric_registration msm_bus_8930_cpss_fpb_pdata;
1067 +
1068 +extern struct msm_bus_fabric_registration msm_bus_8974_sys_noc_pdata;
1069 +extern struct msm_bus_fabric_registration msm_bus_8974_mmss_noc_pdata;
1070 +extern struct msm_bus_fabric_registration msm_bus_8974_bimc_pdata;
1071 +extern struct msm_bus_fabric_registration msm_bus_8974_ocmem_noc_pdata;
1072 +extern struct msm_bus_fabric_registration msm_bus_8974_periph_noc_pdata;
1073 +extern struct msm_bus_fabric_registration msm_bus_8974_config_noc_pdata;
1074 +extern struct msm_bus_fabric_registration msm_bus_8974_ocmem_vnoc_pdata;
1075 +
1076 +extern struct msm_bus_fabric_registration msm_bus_9625_sys_noc_pdata;
1077 +extern struct msm_bus_fabric_registration msm_bus_9625_bimc_pdata;
1078 +extern struct msm_bus_fabric_registration msm_bus_9625_periph_noc_pdata;
1079 +extern struct msm_bus_fabric_registration msm_bus_9625_config_noc_pdata;
1080 +
1081 +extern int msm_bus_device_match_adhoc(struct device *dev, void *id);
1082 +
1083 +void msm_bus_rpm_set_mt_mask(void);
1084 +int msm_bus_board_rpm_get_il_ids(uint16_t *id);
1085 +int msm_bus_board_get_iid(int id);
1086 +
1087 +#define NFAB_MSM8226 6
1088 +#define NFAB_MSM8610 5
1089 +
1090 +/*
1091 + * These macros specify the convention followed for allocating
1092 + * ids to fabrics, masters and slaves for 8x60.
1093 + *
1094 + * A node can be identified as a master/slave/fabric by using
1095 + * these ids.
1096 + */
1097 +#define FABRIC_ID_KEY 1024
1098 +#define SLAVE_ID_KEY ((FABRIC_ID_KEY) >> 1)
1099 +#define MAX_FAB_KEY 7168 /* OR(All fabric ids) */
1100 +#define INT_NODE_START 10000
1101 +
1102 +#define GET_FABID(id) ((id) & MAX_FAB_KEY)
1103 +
1104 +#define NODE_ID(id) ((id) & (FABRIC_ID_KEY - 1))
1105 +#define IS_SLAVE(id) ((NODE_ID(id)) >= SLAVE_ID_KEY ? 1 : 0)
1106 +#define CHECK_ID(iid, id) (((iid & id) != id) ? -ENXIO : iid)
1107 +
1108 +/*
1109 + * The following macros are used to format the data for port halt
1110 + * and unhalt requests.
1111 + */
1112 +#define MSM_BUS_CLK_HALT 0x1
1113 +#define MSM_BUS_CLK_HALT_MASK 0x1
1114 +#define MSM_BUS_CLK_HALT_FIELDSIZE 0x1
1115 +#define MSM_BUS_CLK_UNHALT 0x0
1116 +
1117 +#define MSM_BUS_MASTER_SHIFT(master, fieldsize) \
1118 + ((master) * (fieldsize))
1119 +
1120 +#define MSM_BUS_SET_BITFIELD(word, fieldmask, fieldvalue) \
1121 + { \
1122 + (word) &= ~(fieldmask); \
1123 + (word) |= (fieldvalue); \
1124 + }
1125 +
1126 +
1127 +#define MSM_BUS_MASTER_HALT(u32haltmask, u32haltval, master) \
1128 + MSM_BUS_SET_BITFIELD(u32haltmask, \
1129 + MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
1130 + MSM_BUS_CLK_HALT_FIELDSIZE), \
1131 + MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
1132 + MSM_BUS_CLK_HALT_FIELDSIZE))\
1133 + MSM_BUS_SET_BITFIELD(u32haltval, \
1134 + MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
1135 + MSM_BUS_CLK_HALT_FIELDSIZE), \
1136 + MSM_BUS_CLK_HALT<<MSM_BUS_MASTER_SHIFT((master),\
1137 + MSM_BUS_CLK_HALT_FIELDSIZE))\
1138 +
1139 +#define MSM_BUS_MASTER_UNHALT(u32haltmask, u32haltval, master) \
1140 + MSM_BUS_SET_BITFIELD(u32haltmask, \
1141 + MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
1142 + MSM_BUS_CLK_HALT_FIELDSIZE), \
1143 + MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
1144 + MSM_BUS_CLK_HALT_FIELDSIZE))\
1145 + MSM_BUS_SET_BITFIELD(u32haltval, \
1146 + MSM_BUS_CLK_HALT_MASK<<MSM_BUS_MASTER_SHIFT((master),\
1147 + MSM_BUS_CLK_HALT_FIELDSIZE), \
1148 + MSM_BUS_CLK_UNHALT<<MSM_BUS_MASTER_SHIFT((master),\
1149 + MSM_BUS_CLK_HALT_FIELDSIZE))\
1150 +
1151 +#define RPM_BUS_SLAVE_REQ 0x766c7362
1152 +#define RPM_BUS_MASTER_REQ 0x73616d62
1153 +
1154 +enum msm_bus_rpm_slave_field_type {
1155 + RPM_SLAVE_FIELD_BW = 0x00007762,
1156 +};
1157 +
1158 +enum msm_bus_rpm_mas_field_type {
1159 + RPM_MASTER_FIELD_BW = 0x00007762,
1160 + RPM_MASTER_FIELD_BW_T0 = 0x30747762,
1161 + RPM_MASTER_FIELD_BW_T1 = 0x31747762,
1162 + RPM_MASTER_FIELD_BW_T2 = 0x32747762,
1163 +};
1164 +
1165 +#include <dt-bindings/msm/msm-bus-ids.h>
1166 +
1167 +
1168 +#endif /*__ASM_ARCH_MSM_BUS_BOARD_H */
1169 --- /dev/null
1170 +++ b/drivers/bus/msm_bus/msm-bus.h
1171 @@ -0,0 +1,139 @@
1172 +/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
1173 + *
1174 + * This program is free software; you can redistribute it and/or modify
1175 + * it under the terms of the GNU General Public License version 2 and
1176 + * only version 2 as published by the Free Software Foundation.
1177 + *
1178 + * This program is distributed in the hope that it will be useful,
1179 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1180 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1181 + * GNU General Public License for more details.
1182 + */
1183 +
1184 +#ifndef _ARCH_ARM_MACH_MSM_BUS_H
1185 +#define _ARCH_ARM_MACH_MSM_BUS_H
1186 +
1187 +#include <linux/types.h>
1188 +#include <linux/input.h>
1189 +#include <linux/platform_device.h>
1190 +
1191 +/*
1192 + * Macros for clients to convert their data to ib and ab
1193 + * Ws : Time window over which to transfer the data in SECONDS
1194 + * Bs : Size of the data block in bytes
1195 + * Per : Recurrence period
1196 + * Tb : Throughput bandwidth to prevent stalling
1197 + * R : Ratio of actual bandwidth used to Tb
1198 + * Ib : Instantaneous bandwidth
1199 + * Ab : Arbitrated bandwidth
1200 + *
1201 + * IB_RECURRBLOCK and AB_RECURRBLOCK:
1202 + * These are used if the requirement is to transfer a
1203 + * recurring block of data over a known time window.
1204 + *
1205 + * IB_THROUGHPUTBW and AB_THROUGHPUTBW:
1206 + * These are used for CPU style masters. Here the requirement
1207 + * is to have minimum throughput bandwidth available to avoid
1208 + * stalling.
1209 + */
1210 +#define IB_RECURRBLOCK(Ws, Bs) ((Ws) == 0 ? 0 : ((Bs)/(Ws)))
1211 +#define AB_RECURRBLOCK(Ws, Per) ((Ws) == 0 ? 0 : ((Bs)/(Per)))
1212 +#define IB_THROUGHPUTBW(Tb) (Tb)
1213 +#define AB_THROUGHPUTBW(Tb, R) ((Tb) * (R))
1214 +
1215 +struct msm_bus_vectors {
1216 + int src; /* Master */
1217 + int dst; /* Slave */
1218 + uint64_t ab; /* Arbitrated bandwidth */
1219 + uint64_t ib; /* Instantaneous bandwidth */
1220 +};
1221 +
1222 +struct msm_bus_paths {
1223 + int num_paths;
1224 + struct msm_bus_vectors *vectors;
1225 +};
1226 +
1227 +struct msm_bus_scale_pdata {
1228 + struct msm_bus_paths *usecase;
1229 + int num_usecases;
1230 + const char *name;
1231 + /*
1232 + * If the active_only flag is set to 1, the BW request is applied
1233 + * only when at least one CPU is active (powered on). If the flag
1234 + * is set to 0, then the BW request is always applied irrespective
1235 + * of the CPU state.
1236 + */
1237 + unsigned int active_only;
1238 +};
1239 +
1240 +/* Scaling APIs */
1241 +
1242 +/*
1243 + * This function returns a handle to the client. This should be used to
1244 + * call msm_bus_scale_client_update_request.
1245 + * The function returns 0 if bus driver is unable to register a client
1246 + */
1247 +
1248 +#if (defined(CONFIG_MSM_BUS_SCALING) || defined(CONFIG_BUS_TOPOLOGY_ADHOC))
1249 +int __init msm_bus_fabric_init_driver(void);
1250 +uint32_t msm_bus_scale_register_client(struct msm_bus_scale_pdata *pdata);
1251 +int msm_bus_scale_client_update_request(uint32_t cl, unsigned int index);
1252 +void msm_bus_scale_unregister_client(uint32_t cl);
1253 +/* AXI Port configuration APIs */
1254 +int msm_bus_axi_porthalt(int master_port);
1255 +int msm_bus_axi_portunhalt(int master_port);
1256 +
1257 +#else
1258 +static inline int __init msm_bus_fabric_init_driver(void) { return 0; }
1259 +
1260 +static inline uint32_t
1261 +msm_bus_scale_register_client(struct msm_bus_scale_pdata *pdata)
1262 +{
1263 + return 1;
1264 +}
1265 +
1266 +static inline int
1267 +msm_bus_scale_client_update_request(uint32_t cl, unsigned int index)
1268 +{
1269 + return 0;
1270 +}
1271 +
1272 +static inline void
1273 +msm_bus_scale_unregister_client(uint32_t cl)
1274 +{
1275 +}
1276 +
1277 +static inline int msm_bus_axi_porthalt(int master_port)
1278 +{
1279 + return 0;
1280 +}
1281 +
1282 +static inline int msm_bus_axi_portunhalt(int master_port)
1283 +{
1284 + return 0;
1285 +}
1286 +#endif
1287 +
1288 +#if defined(CONFIG_OF) && defined(CONFIG_MSM_BUS_SCALING)
1289 +struct msm_bus_scale_pdata *msm_bus_pdata_from_node(
1290 + struct platform_device *pdev, struct device_node *of_node);
1291 +struct msm_bus_scale_pdata *msm_bus_cl_get_pdata(struct platform_device *pdev);
1292 +void msm_bus_cl_clear_pdata(struct msm_bus_scale_pdata *pdata);
1293 +#else
1294 +static inline struct msm_bus_scale_pdata
1295 +*msm_bus_cl_get_pdata(struct platform_device *pdev)
1296 +{
1297 + return NULL;
1298 +}
1299 +
1300 +static inline struct msm_bus_scale_pdata *msm_bus_pdata_from_node(
1301 + struct platform_device *pdev, struct device_node *of_node)
1302 +{
1303 + return NULL;
1304 +}
1305 +
1306 +static inline void msm_bus_cl_clear_pdata(struct msm_bus_scale_pdata *pdata)
1307 +{
1308 +}
1309 +#endif
1310 +#endif /*_ARCH_ARM_MACH_MSM_BUS_H*/
1311 --- /dev/null
1312 +++ b/drivers/bus/msm_bus/msm_bus_adhoc.h
1313 @@ -0,0 +1,141 @@
1314 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
1315 + *
1316 + * This program is free software; you can redistribute it and/or modify
1317 + * it under the terms of the GNU General Public License version 2 and
1318 + * only version 2 as published by the Free Software Foundation.
1319 + *
1320 + * This program is distributed in the hope that it will be useful,
1321 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1322 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1323 + * GNU General Public License for more details.
1324 + */
1325 +
1326 +#ifndef _ARCH_ARM_MACH_MSM_BUS_ADHOC_H
1327 +#define _ARCH_ARM_MACH_MSM_BUS_ADHOC_H
1328 +
1329 +#include <linux/types.h>
1330 +#include <linux/device.h>
1331 +#include "msm-bus-board.h"
1332 +#include "msm-bus.h"
1333 +#include "msm_bus_rules.h"
1334 +#include "msm_bus_core.h"
1335 +
1336 +struct msm_bus_node_device_type;
1337 +struct link_node {
1338 + uint64_t lnode_ib[NUM_CTX];
1339 + uint64_t lnode_ab[NUM_CTX];
1340 + int next;
1341 + struct device *next_dev;
1342 + struct list_head link;
1343 + uint32_t in_use;
1344 +};
1345 +
1346 +/* New types introduced for adhoc topology */
1347 +struct msm_bus_noc_ops {
1348 + int (*qos_init)(struct msm_bus_node_device_type *dev,
1349 + void __iomem *qos_base, uint32_t qos_off,
1350 + uint32_t qos_delta, uint32_t qos_freq);
1351 + int (*set_bw)(struct msm_bus_node_device_type *dev,
1352 + void __iomem *qos_base, uint32_t qos_off,
1353 + uint32_t qos_delta, uint32_t qos_freq);
1354 + int (*limit_mport)(struct msm_bus_node_device_type *dev,
1355 + void __iomem *qos_base, uint32_t qos_off,
1356 + uint32_t qos_delta, uint32_t qos_freq, bool enable_lim,
1357 + uint64_t lim_bw);
1358 + bool (*update_bw_reg)(int mode);
1359 +};
1360 +
1361 +struct nodebw {
1362 + uint64_t ab[NUM_CTX];
1363 + bool dirty;
1364 +};
1365 +
1366 +struct msm_bus_fab_device_type {
1367 + void __iomem *qos_base;
1368 + phys_addr_t pqos_base;
1369 + size_t qos_range;
1370 + uint32_t base_offset;
1371 + uint32_t qos_freq;
1372 + uint32_t qos_off;
1373 + uint32_t util_fact;
1374 + uint32_t vrail_comp;
1375 + struct msm_bus_noc_ops noc_ops;
1376 + enum msm_bus_hw_sel bus_type;
1377 + bool bypass_qos_prg;
1378 +};
1379 +
1380 +struct qos_params_type {
1381 + int mode;
1382 + unsigned int prio_lvl;
1383 + unsigned int prio_rd;
1384 + unsigned int prio_wr;
1385 + unsigned int prio1;
1386 + unsigned int prio0;
1387 + unsigned int gp;
1388 + unsigned int thmp;
1389 + unsigned int ws;
1390 + int cur_mode;
1391 + u64 bw_buffer;
1392 +};
1393 +
1394 +struct msm_bus_node_info_type {
1395 + const char *name;
1396 + unsigned int id;
1397 + int mas_rpm_id;
1398 + int slv_rpm_id;
1399 + int num_ports;
1400 + int num_qports;
1401 + int *qport;
1402 + struct qos_params_type qos_params;
1403 + unsigned int num_connections;
1404 + unsigned int num_blist;
1405 + bool is_fab_dev;
1406 + bool virt_dev;
1407 + bool is_traversed;
1408 + unsigned int *connections;
1409 + unsigned int *black_listed_connections;
1410 + struct device **dev_connections;
1411 + struct device **black_connections;
1412 + unsigned int bus_device_id;
1413 + struct device *bus_device;
1414 + unsigned int buswidth;
1415 + struct rule_update_path_info rule;
1416 + uint64_t lim_bw;
1417 + uint32_t util_fact;
1418 + uint32_t vrail_comp;
1419 +};
1420 +
1421 +struct msm_bus_node_device_type {
1422 + struct msm_bus_node_info_type *node_info;
1423 + struct msm_bus_fab_device_type *fabdev;
1424 + int num_lnodes;
1425 + struct link_node *lnode_list;
1426 + uint64_t cur_clk_hz[NUM_CTX];
1427 + struct nodebw node_ab;
1428 + struct list_head link;
1429 + unsigned int ap_owned;
1430 + struct nodeclk clk[NUM_CTX];
1431 + struct nodeclk qos_clk;
1432 +};
1433 +
1434 +int msm_bus_enable_limiter(struct msm_bus_node_device_type *nodedev,
1435 + bool throttle_en, uint64_t lim_bw);
1436 +int msm_bus_update_clks(struct msm_bus_node_device_type *nodedev,
1437 + int ctx, int **dirty_nodes, int *num_dirty);
1438 +int msm_bus_commit_data(int *dirty_nodes, int ctx, int num_dirty);
1439 +int msm_bus_update_bw(struct msm_bus_node_device_type *nodedev, int ctx,
1440 + int64_t add_bw, int **dirty_nodes, int *num_dirty);
1441 +void *msm_bus_realloc_devmem(struct device *dev, void *p, size_t old_size,
1442 + size_t new_size, gfp_t flags);
1443 +
1444 +extern struct msm_bus_device_node_registration
1445 + *msm_bus_of_to_pdata(struct platform_device *pdev);
1446 +extern void msm_bus_arb_setops_adhoc(struct msm_bus_arb_ops *arb_ops);
1447 +extern int msm_bus_bimc_set_ops(struct msm_bus_node_device_type *bus_dev);
1448 +extern int msm_bus_noc_set_ops(struct msm_bus_node_device_type *bus_dev);
1449 +extern int msm_bus_of_get_static_rules(struct platform_device *pdev,
1450 + struct bus_rule_type **static_rule);
1451 +extern int msm_rules_update_path(struct list_head *input_list,
1452 + struct list_head *output_list);
1453 +extern void print_all_rules(void);
1454 +#endif /* _ARCH_ARM_MACH_MSM_BUS_ADHOC_H */
1455 --- /dev/null
1456 +++ b/drivers/bus/msm_bus/msm_bus_arb_adhoc.c
1457 @@ -0,0 +1,998 @@
1458 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
1459 + *
1460 + * This program is Mree software; you can redistribute it and/or modify
1461 + * it under the terms of the GNU General Public License version 2 and
1462 + * only version 2 as published by the Free Software Foundation.
1463 + *
1464 + * This program is distributed in the hope that it will be useful,
1465 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1466 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1467 + * GNU General Public License for more details.
1468 + */
1469 +#include <linux/kernel.h>
1470 +#include <linux/init.h>
1471 +#include <linux/list.h>
1472 +#include <linux/module.h>
1473 +#include <linux/slab.h>
1474 +#include <linux/mutex.h>
1475 +#include <linux/clk.h>
1476 +#include "msm-bus.h"
1477 +#include "msm_bus_core.h"
1478 +#include "msm_bus_adhoc.h"
1479 +
1480 +#define NUM_CL_HANDLES 50
1481 +#define NUM_LNODES 3
1482 +
1483 +struct bus_search_type {
1484 + struct list_head link;
1485 + struct list_head node_list;
1486 +};
1487 +
1488 +struct handle_type {
1489 + int num_entries;
1490 + struct msm_bus_client **cl_list;
1491 +};
1492 +
1493 +static struct handle_type handle_list;
1494 +struct list_head input_list;
1495 +struct list_head apply_list;
1496 +
1497 +DEFINE_MUTEX(msm_bus_adhoc_lock);
1498 +
1499 +static bool chk_bl_list(struct list_head *black_list, unsigned int id)
1500 +{
1501 + struct msm_bus_node_device_type *bus_node = NULL;
1502 +
1503 + list_for_each_entry(bus_node, black_list, link) {
1504 + if (bus_node->node_info->id == id)
1505 + return true;
1506 + }
1507 + return false;
1508 +}
1509 +
1510 +static void copy_remaining_nodes(struct list_head *edge_list, struct list_head
1511 + *traverse_list, struct list_head *route_list)
1512 +{
1513 + struct bus_search_type *search_node;
1514 +
1515 + if (list_empty(edge_list) && list_empty(traverse_list))
1516 + return;
1517 +
1518 + search_node = kzalloc(sizeof(struct bus_search_type), GFP_KERNEL);
1519 + INIT_LIST_HEAD(&search_node->node_list);
1520 + list_splice_init(edge_list, traverse_list);
1521 + list_splice_init(traverse_list, &search_node->node_list);
1522 + list_add_tail(&search_node->link, route_list);
1523 +}
1524 +
1525 +/*
1526 + * Duplicate instantiaion from msm_bus_arb.c. Todo there needs to be a
1527 + * "util" file for these common func/macros.
1528 + *
1529 + * */
1530 +uint64_t msm_bus_div64(unsigned int w, uint64_t bw)
1531 +{
1532 + uint64_t *b = &bw;
1533 +
1534 + if ((bw > 0) && (bw < w))
1535 + return 1;
1536 +
1537 + switch (w) {
1538 + case 0:
1539 + WARN(1, "AXI: Divide by 0 attempted\n");
1540 + case 1: return bw;
1541 + case 2: return (bw >> 1);
1542 + case 4: return (bw >> 2);
1543 + case 8: return (bw >> 3);
1544 + case 16: return (bw >> 4);
1545 + case 32: return (bw >> 5);
1546 + }
1547 +
1548 + do_div(*b, w);
1549 + return *b;
1550 +}
1551 +
1552 +int msm_bus_device_match_adhoc(struct device *dev, void *id)
1553 +{
1554 + int ret = 0;
1555 + struct msm_bus_node_device_type *bnode = dev->platform_data;
1556 +
1557 + if (bnode)
1558 + ret = (bnode->node_info->id == *(unsigned int *)id);
1559 + else
1560 + ret = 0;
1561 +
1562 + return ret;
1563 +}
1564 +
1565 +static int gen_lnode(struct device *dev,
1566 + int next_hop, int prev_idx)
1567 +{
1568 + struct link_node *lnode;
1569 + struct msm_bus_node_device_type *cur_dev = NULL;
1570 + int lnode_idx = -1;
1571 +
1572 + if (!dev)
1573 + goto exit_gen_lnode;
1574 +
1575 + cur_dev = dev->platform_data;
1576 + if (!cur_dev) {
1577 + MSM_BUS_ERR("%s: Null device ptr", __func__);
1578 + goto exit_gen_lnode;
1579 + }
1580 +
1581 + if (!cur_dev->num_lnodes) {
1582 + cur_dev->lnode_list = devm_kzalloc(dev,
1583 + sizeof(struct link_node) * NUM_LNODES,
1584 + GFP_KERNEL);
1585 + if (!cur_dev->lnode_list)
1586 + goto exit_gen_lnode;
1587 +
1588 + lnode = cur_dev->lnode_list;
1589 + cur_dev->num_lnodes = NUM_LNODES;
1590 + lnode_idx = 0;
1591 + } else {
1592 + int i;
1593 + for (i = 0; i < cur_dev->num_lnodes; i++) {
1594 + if (!cur_dev->lnode_list[i].in_use)
1595 + break;
1596 + }
1597 +
1598 + if (i < cur_dev->num_lnodes) {
1599 + lnode = &cur_dev->lnode_list[i];
1600 + lnode_idx = i;
1601 + } else {
1602 + struct link_node *realloc_list;
1603 + size_t cur_size = sizeof(struct link_node) *
1604 + cur_dev->num_lnodes;
1605 +
1606 + cur_dev->num_lnodes += NUM_LNODES;
1607 + realloc_list = msm_bus_realloc_devmem(
1608 + dev,
1609 + cur_dev->lnode_list,
1610 + cur_size,
1611 + sizeof(struct link_node) *
1612 + cur_dev->num_lnodes, GFP_KERNEL);
1613 +
1614 + if (!realloc_list)
1615 + goto exit_gen_lnode;
1616 +
1617 + cur_dev->lnode_list = realloc_list;
1618 + lnode = &cur_dev->lnode_list[i];
1619 + lnode_idx = i;
1620 + }
1621 + }
1622 +
1623 + lnode->in_use = 1;
1624 + if (next_hop == cur_dev->node_info->id) {
1625 + lnode->next = -1;
1626 + lnode->next_dev = NULL;
1627 + } else {
1628 + lnode->next = prev_idx;
1629 + lnode->next_dev = bus_find_device(&msm_bus_type, NULL,
1630 + (void *) &next_hop,
1631 + msm_bus_device_match_adhoc);
1632 + }
1633 +
1634 + memset(lnode->lnode_ib, 0, sizeof(uint64_t) * NUM_CTX);
1635 + memset(lnode->lnode_ab, 0, sizeof(uint64_t) * NUM_CTX);
1636 +
1637 +exit_gen_lnode:
1638 + return lnode_idx;
1639 +}
1640 +
1641 +static int remove_lnode(struct msm_bus_node_device_type *cur_dev,
1642 + int lnode_idx)
1643 +{
1644 + int ret = 0;
1645 +
1646 + if (!cur_dev) {
1647 + MSM_BUS_ERR("%s: Null device ptr", __func__);
1648 + ret = -ENODEV;
1649 + goto exit_remove_lnode;
1650 + }
1651 +
1652 + if (lnode_idx != -1) {
1653 + if (!cur_dev->num_lnodes ||
1654 + (lnode_idx > (cur_dev->num_lnodes - 1))) {
1655 + MSM_BUS_ERR("%s: Invalid Idx %d, num_lnodes %d",
1656 + __func__, lnode_idx, cur_dev->num_lnodes);
1657 + ret = -ENODEV;
1658 + goto exit_remove_lnode;
1659 + }
1660 +
1661 + cur_dev->lnode_list[lnode_idx].next = -1;
1662 + cur_dev->lnode_list[lnode_idx].next_dev = NULL;
1663 + cur_dev->lnode_list[lnode_idx].in_use = 0;
1664 + }
1665 +
1666 +exit_remove_lnode:
1667 + return ret;
1668 +}
1669 +
1670 +static int prune_path(struct list_head *route_list, int dest, int src,
1671 + struct list_head *black_list, int found)
1672 +{
1673 + struct bus_search_type *search_node, *temp_search_node;
1674 + struct msm_bus_node_device_type *bus_node;
1675 + struct list_head *bl_list;
1676 + struct list_head *temp_bl_list;
1677 + int search_dev_id = dest;
1678 + struct device *dest_dev = bus_find_device(&msm_bus_type, NULL,
1679 + (void *) &dest,
1680 + msm_bus_device_match_adhoc);
1681 + int lnode_hop = -1;
1682 +
1683 + if (!found)
1684 + goto reset_links;
1685 +
1686 + if (!dest_dev) {
1687 + MSM_BUS_ERR("%s: Can't find dest dev %d", __func__, dest);
1688 + goto exit_prune_path;
1689 + }
1690 +
1691 + lnode_hop = gen_lnode(dest_dev, search_dev_id, lnode_hop);
1692 +
1693 + list_for_each_entry_reverse(search_node, route_list, link) {
1694 + list_for_each_entry(bus_node, &search_node->node_list, link) {
1695 + unsigned int i;
1696 + for (i = 0; i < bus_node->node_info->num_connections;
1697 + i++) {
1698 + if (bus_node->node_info->connections[i] ==
1699 + search_dev_id) {
1700 + dest_dev = bus_find_device(
1701 + &msm_bus_type,
1702 + NULL,
1703 + (void *)
1704 + &bus_node->node_info->
1705 + id,
1706 + msm_bus_device_match_adhoc);
1707 +
1708 + if (!dest_dev) {
1709 + lnode_hop = -1;
1710 + goto reset_links;
1711 + }
1712 +
1713 + lnode_hop = gen_lnode(dest_dev,
1714 + search_dev_id,
1715 + lnode_hop);
1716 + search_dev_id =
1717 + bus_node->node_info->id;
1718 + break;
1719 + }
1720 + }
1721 + }
1722 + }
1723 +reset_links:
1724 + list_for_each_entry_safe(search_node, temp_search_node, route_list,
1725 + link) {
1726 + list_for_each_entry(bus_node, &search_node->node_list,
1727 + link)
1728 + bus_node->node_info->is_traversed = false;
1729 +
1730 + list_del(&search_node->link);
1731 + kfree(search_node);
1732 + }
1733 +
1734 + list_for_each_safe(bl_list, temp_bl_list, black_list)
1735 + list_del(bl_list);
1736 +
1737 +exit_prune_path:
1738 + return lnode_hop;
1739 +}
1740 +
1741 +static void setup_bl_list(struct msm_bus_node_device_type *node,
1742 + struct list_head *black_list)
1743 +{
1744 + unsigned int i;
1745 +
1746 + for (i = 0; i < node->node_info->num_blist; i++) {
1747 + struct msm_bus_node_device_type *bdev;
1748 + bdev = node->node_info->black_connections[i]->platform_data;
1749 + list_add_tail(&bdev->link, black_list);
1750 + }
1751 +}
1752 +
1753 +static int getpath(int src, int dest)
1754 +{
1755 + struct list_head traverse_list;
1756 + struct list_head edge_list;
1757 + struct list_head route_list;
1758 + struct list_head black_list;
1759 + struct device *src_dev = bus_find_device(&msm_bus_type, NULL,
1760 + (void *) &src,
1761 + msm_bus_device_match_adhoc);
1762 + struct msm_bus_node_device_type *src_node;
1763 + struct bus_search_type *search_node;
1764 + int found = 0;
1765 + int depth_index = 0;
1766 + int first_hop = -1;
1767 +
1768 + INIT_LIST_HEAD(&traverse_list);
1769 + INIT_LIST_HEAD(&edge_list);
1770 + INIT_LIST_HEAD(&route_list);
1771 + INIT_LIST_HEAD(&black_list);
1772 +
1773 + if (!src_dev) {
1774 + MSM_BUS_ERR("%s: Cannot locate src dev %d", __func__, src);
1775 + goto exit_getpath;
1776 + }
1777 +
1778 + src_node = src_dev->platform_data;
1779 + if (!src_node) {
1780 + MSM_BUS_ERR("%s:Fatal, Source dev %d not found", __func__, src);
1781 + goto exit_getpath;
1782 + }
1783 + list_add_tail(&src_node->link, &traverse_list);
1784 +
1785 + while ((!found && !list_empty(&traverse_list))) {
1786 + struct msm_bus_node_device_type *bus_node = NULL;
1787 + /* Locate dest_id in the traverse list */
1788 + list_for_each_entry(bus_node, &traverse_list, link) {
1789 + if (bus_node->node_info->id == dest) {
1790 + found = 1;
1791 + break;
1792 + }
1793 + }
1794 +
1795 + if (!found) {
1796 + unsigned int i;
1797 + /* Setup the new edge list */
1798 + list_for_each_entry(bus_node, &traverse_list, link) {
1799 + /* Setup list of black-listed nodes */
1800 + setup_bl_list(bus_node, &black_list);
1801 +
1802 + for (i = 0; i < bus_node->node_info->
1803 + num_connections; i++) {
1804 + bool skip;
1805 + struct msm_bus_node_device_type
1806 + *node_conn;
1807 + node_conn = bus_node->node_info->
1808 + dev_connections[i]->
1809 + platform_data;
1810 + if (node_conn->node_info->
1811 + is_traversed) {
1812 + MSM_BUS_ERR("Circ Path %d\n",
1813 + node_conn->node_info->id);
1814 + goto reset_traversed;
1815 + }
1816 + skip = chk_bl_list(&black_list,
1817 + bus_node->node_info->
1818 + connections[i]);
1819 + if (!skip) {
1820 + list_add_tail(&node_conn->link,
1821 + &edge_list);
1822 + node_conn->node_info->
1823 + is_traversed = true;
1824 + }
1825 + }
1826 + }
1827 +
1828 + /* Keep tabs of the previous search list */
1829 + search_node = kzalloc(sizeof(struct bus_search_type),
1830 + GFP_KERNEL);
1831 + INIT_LIST_HEAD(&search_node->node_list);
1832 + list_splice_init(&traverse_list,
1833 + &search_node->node_list);
1834 + /* Add the previous search list to a route list */
1835 + list_add_tail(&search_node->link, &route_list);
1836 + /* Advancing the list depth */
1837 + depth_index++;
1838 + list_splice_init(&edge_list, &traverse_list);
1839 + }
1840 + }
1841 +reset_traversed:
1842 + copy_remaining_nodes(&edge_list, &traverse_list, &route_list);
1843 + first_hop = prune_path(&route_list, dest, src, &black_list, found);
1844 +
1845 +exit_getpath:
1846 + return first_hop;
1847 +}
1848 +
1849 +static uint64_t arbitrate_bus_req(struct msm_bus_node_device_type *bus_dev,
1850 + int ctx)
1851 +{
1852 + int i;
1853 + uint64_t max_ib = 0;
1854 + uint64_t sum_ab = 0;
1855 + uint64_t bw_max_hz;
1856 + struct msm_bus_node_device_type *fab_dev = NULL;
1857 + uint32_t util_fact = 0;
1858 + uint32_t vrail_comp = 0;
1859 +
1860 + /* Find max ib */
1861 + for (i = 0; i < bus_dev->num_lnodes; i++) {
1862 + max_ib = max(max_ib, bus_dev->lnode_list[i].lnode_ib[ctx]);
1863 + sum_ab += bus_dev->lnode_list[i].lnode_ab[ctx];
1864 + }
1865 + /*
1866 + * Account for Util factor and vrail comp. The new aggregation
1867 + * formula is:
1868 + * Freq_hz = max((sum(ab) * util_fact)/num_chan, max(ib)/vrail_comp)
1869 + * / bus-width
1870 + * util_fact and vrail comp are obtained from fabric/Node's dts
1871 + * properties.
1872 + * They default to 100 if absent.
1873 + */
1874 + fab_dev = bus_dev->node_info->bus_device->platform_data;
1875 + /* Don't do this for virtual fabrics */
1876 + if (fab_dev && fab_dev->fabdev) {
1877 + util_fact = bus_dev->node_info->util_fact ?
1878 + bus_dev->node_info->util_fact :
1879 + fab_dev->fabdev->util_fact;
1880 + vrail_comp = bus_dev->node_info->vrail_comp ?
1881 + bus_dev->node_info->vrail_comp :
1882 + fab_dev->fabdev->vrail_comp;
1883 + sum_ab *= util_fact;
1884 + sum_ab = msm_bus_div64(100, sum_ab);
1885 + max_ib *= 100;
1886 + max_ib = msm_bus_div64(vrail_comp, max_ib);
1887 + }
1888 +
1889 + /* Account for multiple channels if any */
1890 + if (bus_dev->node_info->num_qports > 1)
1891 + sum_ab = msm_bus_div64(bus_dev->node_info->num_qports,
1892 + sum_ab);
1893 +
1894 + if (!bus_dev->node_info->buswidth) {
1895 + MSM_BUS_WARN("No bus width found for %d. Using default\n",
1896 + bus_dev->node_info->id);
1897 + bus_dev->node_info->buswidth = 8;
1898 + }
1899 +
1900 + bw_max_hz = max(max_ib, sum_ab);
1901 + bw_max_hz = msm_bus_div64(bus_dev->node_info->buswidth,
1902 + bw_max_hz);
1903 +
1904 + return bw_max_hz;
1905 +}
1906 +
1907 +static void del_inp_list(struct list_head *list)
1908 +{
1909 + struct rule_update_path_info *rule_node;
1910 + struct rule_update_path_info *rule_node_tmp;
1911 +
1912 + list_for_each_entry_safe(rule_node, rule_node_tmp, list, link)
1913 + list_del(&rule_node->link);
1914 +}
1915 +
1916 +static void del_op_list(struct list_head *list)
1917 +{
1918 + struct rule_apply_rcm_info *rule;
1919 + struct rule_apply_rcm_info *rule_tmp;
1920 +
1921 + list_for_each_entry_safe(rule, rule_tmp, list, link)
1922 + list_del(&rule->link);
1923 +}
1924 +
1925 +static int msm_bus_apply_rules(struct list_head *list, bool after_clk_commit)
1926 +{
1927 + struct rule_apply_rcm_info *rule;
1928 + struct device *dev = NULL;
1929 + struct msm_bus_node_device_type *dev_info = NULL;
1930 + int ret = 0;
1931 + bool throttle_en = false;
1932 +
1933 + list_for_each_entry(rule, list, link) {
1934 + if (!rule)
1935 + break;
1936 +
1937 + if (rule && (rule->after_clk_commit != after_clk_commit))
1938 + continue;
1939 +
1940 + dev = bus_find_device(&msm_bus_type, NULL,
1941 + (void *) &rule->id,
1942 + msm_bus_device_match_adhoc);
1943 +
1944 + if (!dev) {
1945 + MSM_BUS_ERR("Can't find dev node for %d", rule->id);
1946 + continue;
1947 + }
1948 + dev_info = dev->platform_data;
1949 +
1950 + throttle_en = ((rule->throttle == THROTTLE_ON) ? true : false);
1951 + ret = msm_bus_enable_limiter(dev_info, throttle_en,
1952 + rule->lim_bw);
1953 + if (ret)
1954 + MSM_BUS_ERR("Failed to set limiter for %d", rule->id);
1955 + }
1956 +
1957 + return ret;
1958 +}
1959 +
1960 +static uint64_t get_node_aggab(struct msm_bus_node_device_type *bus_dev)
1961 +{
1962 + int i;
1963 + int ctx;
1964 + uint64_t max_agg_ab = 0;
1965 + uint64_t agg_ab = 0;
1966 +
1967 + for (ctx = 0; ctx < NUM_CTX; ctx++) {
1968 + for (i = 0; i < bus_dev->num_lnodes; i++)
1969 + agg_ab += bus_dev->lnode_list[i].lnode_ab[ctx];
1970 +
1971 + if (bus_dev->node_info->num_qports > 1)
1972 + agg_ab = msm_bus_div64(bus_dev->node_info->num_qports,
1973 + agg_ab);
1974 +
1975 + max_agg_ab = max(max_agg_ab, agg_ab);
1976 + }
1977 +
1978 + return max_agg_ab;
1979 +}
1980 +
1981 +static uint64_t get_node_ib(struct msm_bus_node_device_type *bus_dev)
1982 +{
1983 + int i;
1984 + int ctx;
1985 + uint64_t max_ib = 0;
1986 +
1987 + for (ctx = 0; ctx < NUM_CTX; ctx++) {
1988 + for (i = 0; i < bus_dev->num_lnodes; i++)
1989 + max_ib = max(max_ib,
1990 + bus_dev->lnode_list[i].lnode_ib[ctx]);
1991 + }
1992 + return max_ib;
1993 +}
1994 +
1995 +static int update_path(int src, int dest, uint64_t req_ib, uint64_t req_bw,
1996 + uint64_t cur_ib, uint64_t cur_bw, int src_idx, int ctx)
1997 +{
1998 + struct device *src_dev = NULL;
1999 + struct device *next_dev = NULL;
2000 + struct link_node *lnode = NULL;
2001 + struct msm_bus_node_device_type *dev_info = NULL;
2002 + int curr_idx;
2003 + int ret = 0;
2004 + int *dirty_nodes = NULL;
2005 + int num_dirty = 0;
2006 + struct rule_update_path_info *rule_node;
2007 + bool rules_registered = msm_rule_are_rules_registered();
2008 +
2009 + src_dev = bus_find_device(&msm_bus_type, NULL,
2010 + (void *) &src,
2011 + msm_bus_device_match_adhoc);
2012 +
2013 + if (!src_dev) {
2014 + MSM_BUS_ERR("%s: Can't find source device %d", __func__, src);
2015 + ret = -ENODEV;
2016 + goto exit_update_path;
2017 + }
2018 +
2019 + next_dev = src_dev;
2020 +
2021 + if (src_idx < 0) {
2022 + MSM_BUS_ERR("%s: Invalid lnode idx %d", __func__, src_idx);
2023 + ret = -ENXIO;
2024 + goto exit_update_path;
2025 + }
2026 + curr_idx = src_idx;
2027 +
2028 + INIT_LIST_HEAD(&input_list);
2029 + INIT_LIST_HEAD(&apply_list);
2030 +
2031 + while (next_dev) {
2032 + dev_info = next_dev->platform_data;
2033 +
2034 + if (curr_idx >= dev_info->num_lnodes) {
2035 + MSM_BUS_ERR("%s: Invalid lnode Idx %d num lnodes %d",
2036 + __func__, curr_idx, dev_info->num_lnodes);
2037 + ret = -ENXIO;
2038 + goto exit_update_path;
2039 + }
2040 +
2041 + lnode = &dev_info->lnode_list[curr_idx];
2042 + lnode->lnode_ib[ctx] = req_ib;
2043 + lnode->lnode_ab[ctx] = req_bw;
2044 +
2045 + dev_info->cur_clk_hz[ctx] = arbitrate_bus_req(dev_info, ctx);
2046 +
2047 + /* Start updating the clocks at the first hop.
2048 + * Its ok to figure out the aggregated
2049 + * request at this node.
2050 + */
2051 + if (src_dev != next_dev) {
2052 + ret = msm_bus_update_clks(dev_info, ctx, &dirty_nodes,
2053 + &num_dirty);
2054 + if (ret) {
2055 + MSM_BUS_ERR("%s: Failed to update clks dev %d",
2056 + __func__, dev_info->node_info->id);
2057 + goto exit_update_path;
2058 + }
2059 + }
2060 +
2061 + ret = msm_bus_update_bw(dev_info, ctx, req_bw, &dirty_nodes,
2062 + &num_dirty);
2063 + if (ret) {
2064 + MSM_BUS_ERR("%s: Failed to update bw dev %d",
2065 + __func__, dev_info->node_info->id);
2066 + goto exit_update_path;
2067 + }
2068 +
2069 + if (rules_registered) {
2070 + rule_node = &dev_info->node_info->rule;
2071 + rule_node->id = dev_info->node_info->id;
2072 + rule_node->ib = get_node_ib(dev_info);
2073 + rule_node->ab = get_node_aggab(dev_info);
2074 + rule_node->clk = max(dev_info->cur_clk_hz[ACTIVE_CTX],
2075 + dev_info->cur_clk_hz[DUAL_CTX]);
2076 + list_add_tail(&rule_node->link, &input_list);
2077 + }
2078 +
2079 + next_dev = lnode->next_dev;
2080 + curr_idx = lnode->next;
2081 + }
2082 +
2083 + if (rules_registered) {
2084 + msm_rules_update_path(&input_list, &apply_list);
2085 + msm_bus_apply_rules(&apply_list, false);
2086 + }
2087 +
2088 + msm_bus_commit_data(dirty_nodes, ctx, num_dirty);
2089 +
2090 + if (rules_registered) {
2091 + msm_bus_apply_rules(&apply_list, true);
2092 + del_inp_list(&input_list);
2093 + del_op_list(&apply_list);
2094 + }
2095 +exit_update_path:
2096 + return ret;
2097 +}
2098 +
2099 +static int remove_path(int src, int dst, uint64_t cur_ib, uint64_t cur_ab,
2100 + int src_idx, int active_only)
2101 +{
2102 + struct device *src_dev = NULL;
2103 + struct device *next_dev = NULL;
2104 + struct link_node *lnode = NULL;
2105 + struct msm_bus_node_device_type *dev_info = NULL;
2106 + int ret = 0;
2107 + int cur_idx = src_idx;
2108 + int next_idx;
2109 +
2110 + /* Update the current path to zero out all request from
2111 + * this cient on all paths
2112 + */
2113 +
2114 + ret = update_path(src, dst, 0, 0, cur_ib, cur_ab, src_idx,
2115 + active_only);
2116 + if (ret) {
2117 + MSM_BUS_ERR("%s: Error zeroing out path ctx %d",
2118 + __func__, ACTIVE_CTX);
2119 + goto exit_remove_path;
2120 + }
2121 +
2122 + src_dev = bus_find_device(&msm_bus_type, NULL,
2123 + (void *) &src,
2124 + msm_bus_device_match_adhoc);
2125 + if (!src_dev) {
2126 + MSM_BUS_ERR("%s: Can't find source device %d", __func__, src);
2127 + ret = -ENODEV;
2128 + goto exit_remove_path;
2129 + }
2130 +
2131 + next_dev = src_dev;
2132 +
2133 + while (next_dev) {
2134 + dev_info = next_dev->platform_data;
2135 + lnode = &dev_info->lnode_list[cur_idx];
2136 + next_idx = lnode->next;
2137 + next_dev = lnode->next_dev;
2138 + remove_lnode(dev_info, cur_idx);
2139 + cur_idx = next_idx;
2140 + }
2141 +
2142 +exit_remove_path:
2143 + return ret;
2144 +}
2145 +
2146 +static void getpath_debug(int src, int curr, int active_only)
2147 +{
2148 + struct device *dev_node;
2149 + struct device *dev_it;
2150 + unsigned int hop = 1;
2151 + int idx;
2152 + struct msm_bus_node_device_type *devinfo;
2153 + int i;
2154 +
2155 + dev_node = bus_find_device(&msm_bus_type, NULL,
2156 + (void *) &src,
2157 + msm_bus_device_match_adhoc);
2158 +
2159 + if (!dev_node) {
2160 + MSM_BUS_ERR("SRC NOT FOUND %d", src);
2161 + return;
2162 + }
2163 +
2164 + idx = curr;
2165 + devinfo = dev_node->platform_data;
2166 + dev_it = dev_node;
2167 +
2168 + MSM_BUS_ERR("Route list Src %d", src);
2169 + while (dev_it) {
2170 + struct msm_bus_node_device_type *busdev =
2171 + devinfo->node_info->bus_device->platform_data;
2172 +
2173 + MSM_BUS_ERR("Hop[%d] at Device %d ctx %d", hop,
2174 + devinfo->node_info->id, active_only);
2175 +
2176 + for (i = 0; i < NUM_CTX; i++) {
2177 + MSM_BUS_ERR("dev info sel ib %llu",
2178 + devinfo->cur_clk_hz[i]);
2179 + MSM_BUS_ERR("dev info sel ab %llu",
2180 + devinfo->node_ab.ab[i]);
2181 + }
2182 +
2183 + dev_it = devinfo->lnode_list[idx].next_dev;
2184 + idx = devinfo->lnode_list[idx].next;
2185 + if (dev_it)
2186 + devinfo = dev_it->platform_data;
2187 +
2188 + MSM_BUS_ERR("Bus Device %d", busdev->node_info->id);
2189 + MSM_BUS_ERR("Bus Clock %llu", busdev->clk[active_only].rate);
2190 +
2191 + if (idx < 0)
2192 + break;
2193 + hop++;
2194 + }
2195 +}
2196 +
2197 +static void unregister_client_adhoc(uint32_t cl)
2198 +{
2199 + int i;
2200 + struct msm_bus_scale_pdata *pdata;
2201 + int lnode, src, curr, dest;
2202 + uint64_t cur_clk, cur_bw;
2203 + struct msm_bus_client *client;
2204 +
2205 + mutex_lock(&msm_bus_adhoc_lock);
2206 + if (!cl) {
2207 + MSM_BUS_ERR("%s: Null cl handle passed unregister\n",
2208 + __func__);
2209 + goto exit_unregister_client;
2210 + }
2211 + client = handle_list.cl_list[cl];
2212 + pdata = client->pdata;
2213 + if (!pdata) {
2214 + MSM_BUS_ERR("%s: Null pdata passed to unregister\n",
2215 + __func__);
2216 + goto exit_unregister_client;
2217 + }
2218 +
2219 + curr = client->curr;
2220 + if (curr >= pdata->num_usecases) {
2221 + MSM_BUS_ERR("Invalid index Defaulting curr to 0");
2222 + curr = 0;
2223 + }
2224 +
2225 + MSM_BUS_DBG("%s: Unregistering client %p", __func__, client);
2226 +
2227 + for (i = 0; i < pdata->usecase->num_paths; i++) {
2228 + src = client->pdata->usecase[curr].vectors[i].src;
2229 + dest = client->pdata->usecase[curr].vectors[i].dst;
2230 +
2231 + lnode = client->src_pnode[i];
2232 + cur_clk = client->pdata->usecase[curr].vectors[i].ib;
2233 + cur_bw = client->pdata->usecase[curr].vectors[i].ab;
2234 + remove_path(src, dest, cur_clk, cur_bw, lnode,
2235 + pdata->active_only);
2236 + }
2237 + msm_bus_dbg_client_data(client->pdata, MSM_BUS_DBG_UNREGISTER, cl);
2238 + kfree(client->src_pnode);
2239 + kfree(client);
2240 + handle_list.cl_list[cl] = NULL;
2241 +exit_unregister_client:
2242 + mutex_unlock(&msm_bus_adhoc_lock);
2243 + return;
2244 +}
2245 +
2246 +static int alloc_handle_lst(int size)
2247 +{
2248 + int ret = 0;
2249 + struct msm_bus_client **t_cl_list;
2250 +
2251 + if (!handle_list.num_entries) {
2252 + t_cl_list = kzalloc(sizeof(struct msm_bus_client *)
2253 + * NUM_CL_HANDLES, GFP_KERNEL);
2254 + if (ZERO_OR_NULL_PTR(t_cl_list)) {
2255 + ret = -ENOMEM;
2256 + MSM_BUS_ERR("%s: Failed to allocate handles list",
2257 + __func__);
2258 + goto exit_alloc_handle_lst;
2259 + }
2260 + handle_list.cl_list = t_cl_list;
2261 + handle_list.num_entries += NUM_CL_HANDLES;
2262 + } else {
2263 + t_cl_list = krealloc(handle_list.cl_list,
2264 + sizeof(struct msm_bus_client *) *
2265 + handle_list.num_entries + NUM_CL_HANDLES,
2266 + GFP_KERNEL);
2267 + if (ZERO_OR_NULL_PTR(t_cl_list)) {
2268 + ret = -ENOMEM;
2269 + MSM_BUS_ERR("%s: Failed to allocate handles list",
2270 + __func__);
2271 + goto exit_alloc_handle_lst;
2272 + }
2273 +
2274 + memset(&handle_list.cl_list[handle_list.num_entries], 0,
2275 + NUM_CL_HANDLES * sizeof(struct msm_bus_client *));
2276 + handle_list.num_entries += NUM_CL_HANDLES;
2277 + handle_list.cl_list = t_cl_list;
2278 + }
2279 +exit_alloc_handle_lst:
2280 + return ret;
2281 +}
2282 +
2283 +static uint32_t gen_handle(struct msm_bus_client *client)
2284 +{
2285 + uint32_t handle = 0;
2286 + int i;
2287 + int ret = 0;
2288 +
2289 + for (i = 0; i < handle_list.num_entries; i++) {
2290 + if (i && !handle_list.cl_list[i]) {
2291 + handle = i;
2292 + break;
2293 + }
2294 + }
2295 +
2296 + if (!handle) {
2297 + ret = alloc_handle_lst(NUM_CL_HANDLES);
2298 +
2299 + if (ret) {
2300 + MSM_BUS_ERR("%s: Failed to allocate handle list",
2301 + __func__);
2302 + goto exit_gen_handle;
2303 + }
2304 + handle = i + 1;
2305 + }
2306 + handle_list.cl_list[handle] = client;
2307 +exit_gen_handle:
2308 + return handle;
2309 +}
2310 +
2311 +static uint32_t register_client_adhoc(struct msm_bus_scale_pdata *pdata)
2312 +{
2313 + int src, dest;
2314 + int i;
2315 + struct msm_bus_client *client = NULL;
2316 + int *lnode;
2317 + uint32_t handle = 0;
2318 +
2319 + mutex_lock(&msm_bus_adhoc_lock);
2320 + client = kzalloc(sizeof(struct msm_bus_client), GFP_KERNEL);
2321 + if (!client) {
2322 + MSM_BUS_ERR("%s: Error allocating client data", __func__);
2323 + goto exit_register_client;
2324 + }
2325 + client->pdata = pdata;
2326 +
2327 + lnode = kzalloc(pdata->usecase->num_paths * sizeof(int), GFP_KERNEL);
2328 + if (ZERO_OR_NULL_PTR(lnode)) {
2329 + MSM_BUS_ERR("%s: Error allocating pathnode ptr!", __func__);
2330 + goto exit_register_client;
2331 + }
2332 + client->src_pnode = lnode;
2333 +
2334 + for (i = 0; i < pdata->usecase->num_paths; i++) {
2335 + src = pdata->usecase->vectors[i].src;
2336 + dest = pdata->usecase->vectors[i].dst;
2337 +
2338 + if ((src < 0) || (dest < 0)) {
2339 + MSM_BUS_ERR("%s:Invalid src/dst.src %d dest %d",
2340 + __func__, src, dest);
2341 + goto exit_register_client;
2342 + }
2343 +
2344 + lnode[i] = getpath(src, dest);
2345 + if (lnode[i] < 0) {
2346 + MSM_BUS_ERR("%s:Failed to find path.src %d dest %d",
2347 + __func__, src, dest);
2348 + goto exit_register_client;
2349 + }
2350 + }
2351 +
2352 + handle = gen_handle(client);
2353 + msm_bus_dbg_client_data(client->pdata, MSM_BUS_DBG_REGISTER,
2354 + handle);
2355 + MSM_BUS_DBG("%s:Client handle %d %s", __func__, handle,
2356 + client->pdata->name);
2357 +exit_register_client:
2358 + mutex_unlock(&msm_bus_adhoc_lock);
2359 + return handle;
2360 +}
2361 +
2362 +static int update_request_adhoc(uint32_t cl, unsigned int index)
2363 +{
2364 + int i, ret = 0;
2365 + struct msm_bus_scale_pdata *pdata;
2366 + int lnode, src, curr, dest;
2367 + uint64_t req_clk, req_bw, curr_clk, curr_bw;
2368 + struct msm_bus_client *client;
2369 + const char *test_cl = "Null";
2370 + bool log_transaction = false;
2371 +
2372 + mutex_lock(&msm_bus_adhoc_lock);
2373 +
2374 + if (!cl) {
2375 + MSM_BUS_ERR("%s: Invalid client handle %d", __func__, cl);
2376 + ret = -ENXIO;
2377 + goto exit_update_request;
2378 + }
2379 +
2380 + client = handle_list.cl_list[cl];
2381 + pdata = client->pdata;
2382 + if (!pdata) {
2383 + MSM_BUS_ERR("%s: Client data Null.[client didn't register]",
2384 + __func__);
2385 + ret = -ENXIO;
2386 + goto exit_update_request;
2387 + }
2388 +
2389 + if (index >= pdata->num_usecases) {
2390 + MSM_BUS_ERR("Client %u passed invalid index: %d\n",
2391 + cl, index);
2392 + ret = -ENXIO;
2393 + goto exit_update_request;
2394 + }
2395 +
2396 + if (client->curr == index) {
2397 + MSM_BUS_DBG("%s: Not updating client request idx %d unchanged",
2398 + __func__, index);
2399 + goto exit_update_request;
2400 + }
2401 +
2402 + curr = client->curr;
2403 + client->curr = index;
2404 +
2405 + if (!strcmp(test_cl, pdata->name))
2406 + log_transaction = true;
2407 +
2408 + MSM_BUS_DBG("%s: cl: %u index: %d curr: %d num_paths: %d\n", __func__,
2409 + cl, index, client->curr, client->pdata->usecase->num_paths);
2410 +
2411 + for (i = 0; i < pdata->usecase->num_paths; i++) {
2412 + src = client->pdata->usecase[index].vectors[i].src;
2413 + dest = client->pdata->usecase[index].vectors[i].dst;
2414 +
2415 + lnode = client->src_pnode[i];
2416 + req_clk = client->pdata->usecase[index].vectors[i].ib;
2417 + req_bw = client->pdata->usecase[index].vectors[i].ab;
2418 + if (curr < 0) {
2419 + curr_clk = 0;
2420 + curr_bw = 0;
2421 + } else {
2422 + curr_clk = client->pdata->usecase[curr].vectors[i].ib;
2423 + curr_bw = client->pdata->usecase[curr].vectors[i].ab;
2424 + MSM_BUS_DBG("%s:ab: %llu ib: %llu\n", __func__,
2425 + curr_bw, curr_clk);
2426 + }
2427 +
2428 + ret = update_path(src, dest, req_clk, req_bw,
2429 + curr_clk, curr_bw, lnode, pdata->active_only);
2430 +
2431 + if (ret) {
2432 + MSM_BUS_ERR("%s: Update path failed! %d ctx %d\n",
2433 + __func__, ret, ACTIVE_CTX);
2434 + goto exit_update_request;
2435 + }
2436 +
2437 + if (log_transaction)
2438 + getpath_debug(src, lnode, pdata->active_only);
2439 + }
2440 + msm_bus_dbg_client_data(client->pdata, index , cl);
2441 +exit_update_request:
2442 + mutex_unlock(&msm_bus_adhoc_lock);
2443 + return ret;
2444 +}
2445 +
2446 +/**
2447 + * msm_bus_arb_setops_adhoc() : Setup the bus arbitration ops
2448 + * @ arb_ops: pointer to the arb ops.
2449 + */
2450 +void msm_bus_arb_setops_adhoc(struct msm_bus_arb_ops *arb_ops)
2451 +{
2452 + arb_ops->register_client = register_client_adhoc;
2453 + arb_ops->update_request = update_request_adhoc;
2454 + arb_ops->unregister_client = unregister_client_adhoc;
2455 +}
2456 --- /dev/null
2457 +++ b/drivers/bus/msm_bus/msm_bus_bimc.c
2458 @@ -0,0 +1,2112 @@
2459 +/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
2460 + *
2461 + * This program is free software; you can redistribute it and/or modify
2462 + * it under the terms of the GNU General Public License version 2 and
2463 + * only version 2 as published by the Free Software Foundation.
2464 + *
2465 + * This program is distributed in the hope that it will be useful,
2466 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2467 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2468 + * GNU General Public License for more details.
2469 + */
2470 +
2471 +#define pr_fmt(fmt) "AXI: BIMC: %s(): " fmt, __func__
2472 +
2473 +#include <linux/slab.h>
2474 +#include <linux/io.h>
2475 +#include "msm-bus-board.h"
2476 +#include "msm_bus_core.h"
2477 +#include "msm_bus_bimc.h"
2478 +#include "msm_bus_adhoc.h"
2479 +#include <trace/events/trace_msm_bus.h>
2480 +
2481 +enum msm_bus_bimc_slave_block {
2482 + SLAVE_BLOCK_RESERVED = 0,
2483 + SLAVE_BLOCK_SLAVE_WAY,
2484 + SLAVE_BLOCK_XPU,
2485 + SLAVE_BLOCK_ARBITER,
2486 + SLAVE_BLOCK_SCMO,
2487 +};
2488 +
2489 +enum bke_sw {
2490 + BKE_OFF = 0,
2491 + BKE_ON = 1,
2492 +};
2493 +
2494 +/* M_Generic */
2495 +
2496 +#define M_REG_BASE(b) ((b) + 0x00008000)
2497 +
2498 +#define M_COMPONENT_INFO_ADDR(b, n) \
2499 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000000)
2500 +enum bimc_m_component_info {
2501 + M_COMPONENT_INFO_RMSK = 0xffffff,
2502 + M_COMPONENT_INFO_INSTANCE_BMSK = 0xff0000,
2503 + M_COMPONENT_INFO_INSTANCE_SHFT = 0x10,
2504 + M_COMPONENT_INFO_SUB_TYPE_BMSK = 0xff00,
2505 + M_COMPONENT_INFO_SUB_TYPE_SHFT = 0x8,
2506 + M_COMPONENT_INFO_TYPE_BMSK = 0xff,
2507 + M_COMPONENT_INFO_TYPE_SHFT = 0x0,
2508 +};
2509 +
2510 +#define M_CONFIG_INFO_0_ADDR(b, n) \
2511 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000020)
2512 +enum bimc_m_config_info_0 {
2513 + M_CONFIG_INFO_0_RMSK = 0xff00ffff,
2514 + M_CONFIG_INFO_0_SYNC_MODE_BMSK = 0xff000000,
2515 + M_CONFIG_INFO_0_SYNC_MODE_SHFT = 0x18,
2516 + M_CONFIG_INFO_0_CONNECTION_TYPE_BMSK = 0xff00,
2517 + M_CONFIG_INFO_0_CONNECTION_TYPE_SHFT = 0x8,
2518 + M_CONFIG_INFO_0_FUNC_BMSK = 0xff,
2519 + M_CONFIG_INFO_0_FUNC_SHFT = 0x0,
2520 +};
2521 +
2522 +#define M_CONFIG_INFO_1_ADDR(b, n) \
2523 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000030)
2524 +enum bimc_m_config_info_1 {
2525 + M_CONFIG_INFO_1_RMSK = 0xffffffff,
2526 + M_CONFIG_INFO_1_SWAY_CONNECTIVITY_BMSK = 0xffffffff,
2527 + M_CONFIG_INFO_1_SWAY_CONNECTIVITY_SHFT = 0x0,
2528 +};
2529 +
2530 +#define M_CONFIG_INFO_2_ADDR(b, n) \
2531 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000040)
2532 +enum bimc_m_config_info_2 {
2533 + M_CONFIG_INFO_2_RMSK = 0xffffffff,
2534 + M_CONFIG_INFO_2_M_DATA_WIDTH_BMSK = 0xffff0000,
2535 + M_CONFIG_INFO_2_M_DATA_WIDTH_SHFT = 0x10,
2536 + M_CONFIG_INFO_2_M_TID_WIDTH_BMSK = 0xff00,
2537 + M_CONFIG_INFO_2_M_TID_WIDTH_SHFT = 0x8,
2538 + M_CONFIG_INFO_2_M_MID_WIDTH_BMSK = 0xff,
2539 + M_CONFIG_INFO_2_M_MID_WIDTH_SHFT = 0x0,
2540 +};
2541 +
2542 +#define M_CONFIG_INFO_3_ADDR(b, n) \
2543 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000050)
2544 +enum bimc_m_config_info_3 {
2545 + M_CONFIG_INFO_3_RMSK = 0xffffffff,
2546 + M_CONFIG_INFO_3_RCH_DEPTH_BMSK = 0xff000000,
2547 + M_CONFIG_INFO_3_RCH_DEPTH_SHFT = 0x18,
2548 + M_CONFIG_INFO_3_BCH_DEPTH_BMSK = 0xff0000,
2549 + M_CONFIG_INFO_3_BCH_DEPTH_SHFT = 0x10,
2550 + M_CONFIG_INFO_3_WCH_DEPTH_BMSK = 0xff00,
2551 + M_CONFIG_INFO_3_WCH_DEPTH_SHFT = 0x8,
2552 + M_CONFIG_INFO_3_ACH_DEPTH_BMSK = 0xff,
2553 + M_CONFIG_INFO_3_ACH_DEPTH_SHFT = 0x0,
2554 +};
2555 +
2556 +#define M_CONFIG_INFO_4_ADDR(b, n) \
2557 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000060)
2558 +enum bimc_m_config_info_4 {
2559 + M_CONFIG_INFO_4_RMSK = 0xffff,
2560 + M_CONFIG_INFO_4_REORDER_BUF_DEPTH_BMSK = 0xff00,
2561 + M_CONFIG_INFO_4_REORDER_BUF_DEPTH_SHFT = 0x8,
2562 + M_CONFIG_INFO_4_REORDER_TABLE_DEPTH_BMSK = 0xff,
2563 + M_CONFIG_INFO_4_REORDER_TABLE_DEPTH_SHFT = 0x0,
2564 +};
2565 +
2566 +#define M_CONFIG_INFO_5_ADDR(b, n) \
2567 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000070)
2568 +enum bimc_m_config_info_5 {
2569 + M_CONFIG_INFO_5_RMSK = 0x111,
2570 + M_CONFIG_INFO_5_MP2ARB_PIPELINE_EN_BMSK = 0x100,
2571 + M_CONFIG_INFO_5_MP2ARB_PIPELINE_EN_SHFT = 0x8,
2572 + M_CONFIG_INFO_5_MPBUF_PIPELINE_EN_BMSK = 0x10,
2573 + M_CONFIG_INFO_5_MPBUF_PIPELINE_EN_SHFT = 0x4,
2574 + M_CONFIG_INFO_5_M2MP_PIPELINE_EN_BMSK = 0x1,
2575 + M_CONFIG_INFO_5_M2MP_PIPELINE_EN_SHFT = 0x0,
2576 +};
2577 +
2578 +#define M_INT_STATUS_ADDR(b, n) \
2579 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000100)
2580 +enum bimc_m_int_status {
2581 + M_INT_STATUS_RMSK = 0x3,
2582 +};
2583 +
2584 +#define M_INT_CLR_ADDR(b, n) \
2585 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000108)
2586 +enum bimc_m_int_clr {
2587 + M_INT_CLR_RMSK = 0x3,
2588 +};
2589 +
2590 +#define M_INT_EN_ADDR(b, n) \
2591 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x0000010c)
2592 +enum bimc_m_int_en {
2593 + M_INT_EN_RMSK = 0x3,
2594 +};
2595 +
2596 +#define M_CLK_CTRL_ADDR(b, n) \
2597 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000200)
2598 +enum bimc_m_clk_ctrl {
2599 + M_CLK_CTRL_RMSK = 0x3,
2600 + M_CLK_CTRL_MAS_CLK_GATING_EN_BMSK = 0x2,
2601 + M_CLK_CTRL_MAS_CLK_GATING_EN_SHFT = 0x1,
2602 + M_CLK_CTRL_CORE_CLK_GATING_EN_BMSK = 0x1,
2603 + M_CLK_CTRL_CORE_CLK_GATING_EN_SHFT = 0x0,
2604 +};
2605 +
2606 +#define M_MODE_ADDR(b, n) \
2607 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000210)
2608 +enum bimc_m_mode {
2609 + M_MODE_RMSK = 0xf0000011,
2610 + M_MODE_WR_GATHER_BEATS_BMSK = 0xf0000000,
2611 + M_MODE_WR_GATHER_BEATS_SHFT = 0x1c,
2612 + M_MODE_NARROW_WR_BMSK = 0x10,
2613 + M_MODE_NARROW_WR_SHFT = 0x4,
2614 + M_MODE_ORDERING_MODEL_BMSK = 0x1,
2615 + M_MODE_ORDERING_MODEL_SHFT = 0x0,
2616 +};
2617 +
2618 +#define M_PRIOLVL_OVERRIDE_ADDR(b, n) \
2619 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000230)
2620 +enum bimc_m_priolvl_override {
2621 + M_PRIOLVL_OVERRIDE_RMSK = 0x301,
2622 + M_PRIOLVL_OVERRIDE_BMSK = 0x300,
2623 + M_PRIOLVL_OVERRIDE_SHFT = 0x8,
2624 + M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_BMSK = 0x1,
2625 + M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_SHFT = 0x0,
2626 +};
2627 +
2628 +#define M_RD_CMD_OVERRIDE_ADDR(b, n) \
2629 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000240)
2630 +enum bimc_m_read_command_override {
2631 + M_RD_CMD_OVERRIDE_RMSK = 0x3071f7f,
2632 + M_RD_CMD_OVERRIDE_AREQPRIO_BMSK = 0x3000000,
2633 + M_RD_CMD_OVERRIDE_AREQPRIO_SHFT = 0x18,
2634 + M_RD_CMD_OVERRIDE_AMEMTYPE_BMSK = 0x70000,
2635 + M_RD_CMD_OVERRIDE_AMEMTYPE_SHFT = 0x10,
2636 + M_RD_CMD_OVERRIDE_ATRANSIENT_BMSK = 0x1000,
2637 + M_RD_CMD_OVERRIDE_ATRANSIENT_SHFT = 0xc,
2638 + M_RD_CMD_OVERRIDE_ASHARED_BMSK = 0x800,
2639 + M_RD_CMD_OVERRIDE_ASHARED_SHFT = 0xb,
2640 + M_RD_CMD_OVERRIDE_AREDIRECT_BMSK = 0x400,
2641 + M_RD_CMD_OVERRIDE_AREDIRECT_SHFT = 0xa,
2642 + M_RD_CMD_OVERRIDE_AOOO_BMSK = 0x200,
2643 + M_RD_CMD_OVERRIDE_AOOO_SHFT = 0x9,
2644 + M_RD_CMD_OVERRIDE_AINNERSHARED_BMSK = 0x100,
2645 + M_RD_CMD_OVERRIDE_AINNERSHARED_SHFT = 0x8,
2646 + M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK = 0x40,
2647 + M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT = 0x6,
2648 + M_RD_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_BMSK = 0x20,
2649 + M_RD_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_SHFT = 0x5,
2650 + M_RD_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_BMSK = 0x10,
2651 + M_RD_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_SHFT = 0x4,
2652 + M_RD_CMD_OVERRIDE_OVERRIDE_ASHARED_BMSK = 0x8,
2653 + M_RD_CMD_OVERRIDE_OVERRIDE_ASHARED_SHFT = 0x3,
2654 + M_RD_CMD_OVERRIDE_OVERRIDE_AREDIRECT_BMSK = 0x4,
2655 + M_RD_CMD_OVERRIDE_OVERRIDE_AREDIRECT_SHFT = 0x2,
2656 + M_RD_CMD_OVERRIDE_OVERRIDE_AOOO_BMSK = 0x2,
2657 + M_RD_CMD_OVERRIDE_OVERRIDE_AOOO_SHFT = 0x1,
2658 + M_RD_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_BMSK = 0x1,
2659 + M_RD_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_SHFT = 0x0,
2660 +};
2661 +
2662 +#define M_WR_CMD_OVERRIDE_ADDR(b, n) \
2663 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000250)
2664 +enum bimc_m_write_command_override {
2665 + M_WR_CMD_OVERRIDE_RMSK = 0x3071f7f,
2666 + M_WR_CMD_OVERRIDE_AREQPRIO_BMSK = 0x3000000,
2667 + M_WR_CMD_OVERRIDE_AREQPRIO_SHFT = 0x18,
2668 + M_WR_CMD_OVERRIDE_AMEMTYPE_BMSK = 0x70000,
2669 + M_WR_CMD_OVERRIDE_AMEMTYPE_SHFT = 0x10,
2670 + M_WR_CMD_OVERRIDE_ATRANSIENT_BMSK = 0x1000,
2671 + M_WR_CMD_OVERRIDE_ATRANSIENT_SHFT = 0xc,
2672 + M_WR_CMD_OVERRIDE_ASHARED_BMSK = 0x800,
2673 + M_WR_CMD_OVERRIDE_ASHARED_SHFT = 0xb,
2674 + M_WR_CMD_OVERRIDE_AREDIRECT_BMSK = 0x400,
2675 + M_WR_CMD_OVERRIDE_AREDIRECT_SHFT = 0xa,
2676 + M_WR_CMD_OVERRIDE_AOOO_BMSK = 0x200,
2677 + M_WR_CMD_OVERRIDE_AOOO_SHFT = 0x9,
2678 + M_WR_CMD_OVERRIDE_AINNERSHARED_BMSK = 0x100,
2679 + M_WR_CMD_OVERRIDE_AINNERSHARED_SHFT = 0x8,
2680 + M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK = 0x40,
2681 + M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT = 0x6,
2682 + M_WR_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_BMSK = 0x20,
2683 + M_WR_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_SHFT = 0x5,
2684 + M_WR_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_BMSK = 0x10,
2685 + M_WR_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_SHFT = 0x4,
2686 + M_WR_CMD_OVERRIDE_OVERRIDE_ASHARED_BMSK = 0x8,
2687 + M_WR_CMD_OVERRIDE_OVERRIDE_ASHARED_SHFT = 0x3,
2688 + M_WR_CMD_OVERRIDE_OVERRIDE_AREDIRECT_BMSK = 0x4,
2689 + M_WR_CMD_OVERRIDE_OVERRIDE_AREDIRECT_SHFT = 0x2,
2690 + M_WR_CMD_OVERRIDE_OVERRIDE_AOOO_BMSK = 0x2,
2691 + M_WR_CMD_OVERRIDE_OVERRIDE_AOOO_SHFT = 0x1,
2692 + M_WR_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_BMSK = 0x1,
2693 + M_WR_CMD_OVERRIDE_OVERRIDE_AINNERSHARED_SHFT = 0x0,
2694 +};
2695 +
2696 +#define M_BKE_EN_ADDR(b, n) \
2697 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000300)
2698 +enum bimc_m_bke_en {
2699 + M_BKE_EN_RMSK = 0x1,
2700 + M_BKE_EN_EN_BMSK = 0x1,
2701 + M_BKE_EN_EN_SHFT = 0x0,
2702 +};
2703 +
2704 +/* Grant Period registers */
2705 +#define M_BKE_GP_ADDR(b, n) \
2706 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000304)
2707 +enum bimc_m_bke_grant_period {
2708 + M_BKE_GP_RMSK = 0x3ff,
2709 + M_BKE_GP_GP_BMSK = 0x3ff,
2710 + M_BKE_GP_GP_SHFT = 0x0,
2711 +};
2712 +
2713 +/* Grant count register.
2714 + * The Grant count register represents a signed 16 bit
2715 + * value, range 0-0x7fff
2716 + */
2717 +#define M_BKE_GC_ADDR(b, n) \
2718 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000308)
2719 +enum bimc_m_bke_grant_count {
2720 + M_BKE_GC_RMSK = 0xffff,
2721 + M_BKE_GC_GC_BMSK = 0xffff,
2722 + M_BKE_GC_GC_SHFT = 0x0,
2723 +};
2724 +
2725 +/* Threshold High Registers */
2726 +#define M_BKE_THH_ADDR(b, n) \
2727 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000320)
2728 +enum bimc_m_bke_thresh_high {
2729 + M_BKE_THH_RMSK = 0xffff,
2730 + M_BKE_THH_THRESH_BMSK = 0xffff,
2731 + M_BKE_THH_THRESH_SHFT = 0x0,
2732 +};
2733 +
2734 +/* Threshold Medium Registers */
2735 +#define M_BKE_THM_ADDR(b, n) \
2736 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000324)
2737 +enum bimc_m_bke_thresh_medium {
2738 + M_BKE_THM_RMSK = 0xffff,
2739 + M_BKE_THM_THRESH_BMSK = 0xffff,
2740 + M_BKE_THM_THRESH_SHFT = 0x0,
2741 +};
2742 +
2743 +/* Threshold Low Registers */
2744 +#define M_BKE_THL_ADDR(b, n) \
2745 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000328)
2746 +enum bimc_m_bke_thresh_low {
2747 + M_BKE_THL_RMSK = 0xffff,
2748 + M_BKE_THL_THRESH_BMSK = 0xffff,
2749 + M_BKE_THL_THRESH_SHFT = 0x0,
2750 +};
2751 +
2752 +#define M_BKE_HEALTH_0_CONFIG_ADDR(b, n) \
2753 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000340)
2754 +enum bimc_m_bke_health_0 {
2755 + M_BKE_HEALTH_0_CONFIG_RMSK = 0x80000303,
2756 + M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_BMSK = 0x80000000,
2757 + M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_SHFT = 0x1f,
2758 + M_BKE_HEALTH_0_CONFIG_AREQPRIO_BMSK = 0x300,
2759 + M_BKE_HEALTH_0_CONFIG_AREQPRIO_SHFT = 0x8,
2760 + M_BKE_HEALTH_0_CONFIG_PRIOLVL_BMSK = 0x3,
2761 + M_BKE_HEALTH_0_CONFIG_PRIOLVL_SHFT = 0x0,
2762 +};
2763 +
2764 +#define M_BKE_HEALTH_1_CONFIG_ADDR(b, n) \
2765 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000344)
2766 +enum bimc_m_bke_health_1 {
2767 + M_BKE_HEALTH_1_CONFIG_RMSK = 0x80000303,
2768 + M_BKE_HEALTH_1_CONFIG_LIMIT_CMDS_BMSK = 0x80000000,
2769 + M_BKE_HEALTH_1_CONFIG_LIMIT_CMDS_SHFT = 0x1f,
2770 + M_BKE_HEALTH_1_CONFIG_AREQPRIO_BMSK = 0x300,
2771 + M_BKE_HEALTH_1_CONFIG_AREQPRIO_SHFT = 0x8,
2772 + M_BKE_HEALTH_1_CONFIG_PRIOLVL_BMSK = 0x3,
2773 + M_BKE_HEALTH_1_CONFIG_PRIOLVL_SHFT = 0x0,
2774 +};
2775 +
2776 +#define M_BKE_HEALTH_2_CONFIG_ADDR(b, n) \
2777 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000348)
2778 +enum bimc_m_bke_health_2 {
2779 + M_BKE_HEALTH_2_CONFIG_RMSK = 0x80000303,
2780 + M_BKE_HEALTH_2_CONFIG_LIMIT_CMDS_BMSK = 0x80000000,
2781 + M_BKE_HEALTH_2_CONFIG_LIMIT_CMDS_SHFT = 0x1f,
2782 + M_BKE_HEALTH_2_CONFIG_AREQPRIO_BMSK = 0x300,
2783 + M_BKE_HEALTH_2_CONFIG_AREQPRIO_SHFT = 0x8,
2784 + M_BKE_HEALTH_2_CONFIG_PRIOLVL_BMSK = 0x3,
2785 + M_BKE_HEALTH_2_CONFIG_PRIOLVL_SHFT = 0x0,
2786 +};
2787 +
2788 +#define M_BKE_HEALTH_3_CONFIG_ADDR(b, n) \
2789 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x0000034c)
2790 +enum bimc_m_bke_health_3 {
2791 + M_BKE_HEALTH_3_CONFIG_RMSK = 0x303,
2792 + M_BKE_HEALTH_3_CONFIG_AREQPRIO_BMSK = 0x300,
2793 + M_BKE_HEALTH_3_CONFIG_AREQPRIO_SHFT = 0x8,
2794 + M_BKE_HEALTH_3_CONFIG_PRIOLVL_BMSK = 0x3,
2795 + M_BKE_HEALTH_3_CONFIG_PRIOLVL_SHFT = 0x0,
2796 +};
2797 +
2798 +#define M_BUF_STATUS_ADDR(b, n) \
2799 + (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000400)
2800 +enum bimc_m_buf_status {
2801 + M_BUF_STATUS_RMSK = 0xf03f030,
2802 + M_BUF_STATUS_RCH_DATA_WR_FULL_BMSK = 0x8000000,
2803 + M_BUF_STATUS_RCH_DATA_WR_FULL_SHFT = 0x1b,
2804 + M_BUF_STATUS_RCH_DATA_WR_EMPTY_BMSK = 0x4000000,
2805 + M_BUF_STATUS_RCH_DATA_WR_EMPTY_SHFT = 0x1a,
2806 + M_BUF_STATUS_RCH_CTRL_WR_FULL_BMSK = 0x2000000,
2807 + M_BUF_STATUS_RCH_CTRL_WR_FULL_SHFT = 0x19,
2808 + M_BUF_STATUS_RCH_CTRL_WR_EMPTY_BMSK = 0x1000000,
2809 + M_BUF_STATUS_RCH_CTRL_WR_EMPTY_SHFT = 0x18,
2810 + M_BUF_STATUS_BCH_WR_FULL_BMSK = 0x20000,
2811 + M_BUF_STATUS_BCH_WR_FULL_SHFT = 0x11,
2812 + M_BUF_STATUS_BCH_WR_EMPTY_BMSK = 0x10000,
2813 + M_BUF_STATUS_BCH_WR_EMPTY_SHFT = 0x10,
2814 + M_BUF_STATUS_WCH_DATA_RD_FULL_BMSK = 0x8000,
2815 + M_BUF_STATUS_WCH_DATA_RD_FULL_SHFT = 0xf,
2816 + M_BUF_STATUS_WCH_DATA_RD_EMPTY_BMSK = 0x4000,
2817 + M_BUF_STATUS_WCH_DATA_RD_EMPTY_SHFT = 0xe,
2818 + M_BUF_STATUS_WCH_CTRL_RD_FULL_BMSK = 0x2000,
2819 + M_BUF_STATUS_WCH_CTRL_RD_FULL_SHFT = 0xd,
2820 + M_BUF_STATUS_WCH_CTRL_RD_EMPTY_BMSK = 0x1000,
2821 + M_BUF_STATUS_WCH_CTRL_RD_EMPTY_SHFT = 0xc,
2822 + M_BUF_STATUS_ACH_RD_FULL_BMSK = 0x20,
2823 + M_BUF_STATUS_ACH_RD_FULL_SHFT = 0x5,
2824 + M_BUF_STATUS_ACH_RD_EMPTY_BMSK = 0x10,
2825 + M_BUF_STATUS_ACH_RD_EMPTY_SHFT = 0x4,
2826 +};
2827 +/*BIMC Generic */
2828 +
2829 +#define S_REG_BASE(b) ((b) + 0x00048000)
2830 +
2831 +#define S_COMPONENT_INFO_ADDR(b, n) \
2832 + (S_REG_BASE(b) + (0x8000 * (n)) + 0x00000000)
2833 +enum bimc_s_component_info {
2834 + S_COMPONENT_INFO_RMSK = 0xffffff,
2835 + S_COMPONENT_INFO_INSTANCE_BMSK = 0xff0000,
2836 + S_COMPONENT_INFO_INSTANCE_SHFT = 0x10,
2837 + S_COMPONENT_INFO_SUB_TYPE_BMSK = 0xff00,
2838 + S_COMPONENT_INFO_SUB_TYPE_SHFT = 0x8,
2839 + S_COMPONENT_INFO_TYPE_BMSK = 0xff,
2840 + S_COMPONENT_INFO_TYPE_SHFT = 0x0,
2841 +};
2842 +
2843 +#define S_HW_INFO_ADDR(b, n) \
2844 + (S_REG_BASE(b) + (0x80000 * (n)) + 0x00000010)
2845 +enum bimc_s_hw_info {
2846 + S_HW_INFO_RMSK = 0xffffffff,
2847 + S_HW_INFO_MAJOR_BMSK = 0xff000000,
2848 + S_HW_INFO_MAJOR_SHFT = 0x18,
2849 + S_HW_INFO_BRANCH_BMSK = 0xff0000,
2850 + S_HW_INFO_BRANCH_SHFT = 0x10,
2851 + S_HW_INFO_MINOR_BMSK = 0xff00,
2852 + S_HW_INFO_MINOR_SHFT = 0x8,
2853 + S_HW_INFO_ECO_BMSK = 0xff,
2854 + S_HW_INFO_ECO_SHFT = 0x0,
2855 +};
2856 +
2857 +
2858 +/* S_SCMO_GENERIC */
2859 +
2860 +#define S_SCMO_REG_BASE(b) ((b) + 0x00048000)
2861 +
2862 +#define S_SCMO_CONFIG_INFO_0_ADDR(b, n) \
2863 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000020)
2864 +enum bimc_s_scmo_config_info_0 {
2865 + S_SCMO_CONFIG_INFO_0_RMSK = 0xffffffff,
2866 + S_SCMO_CONFIG_INFO_0_DATA_WIDTH_BMSK = 0xffff0000,
2867 + S_SCMO_CONFIG_INFO_0_DATA_WIDTH_SHFT = 0x10,
2868 + S_SCMO_CONFIG_INFO_0_TID_WIDTH_BMSK = 0xff00,
2869 + S_SCMO_CONFIG_INFO_0_TID_WIDTH_SHFT = 0x8,
2870 + S_SCMO_CONFIG_INFO_0_MID_WIDTH_BMSK = 0xff,
2871 + S_SCMO_CONFIG_INFO_0_MID_WIDTH_SHFT = 0x0,
2872 +};
2873 +
2874 +#define S_SCMO_CONFIG_INFO_1_ADDR(b, n) \
2875 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000030)
2876 +enum bimc_s_scmo_config_info_1 {
2877 + S_SCMO_CONFIG_INFO_1_RMSK = 0xffffffff,
2878 + S_SCMO_CONFIG_INFO_1_MPORT_CONNECTIVITY_BMSK = 0xffffffff,
2879 + S_SCMO_CONFIG_INFO_1_MPORT_CONNECTIVITY_SHFT = 0x0,
2880 +};
2881 +
2882 +#define S_SCMO_CONFIG_INFO_2_ADDR(b, n) \
2883 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000040)
2884 +enum bimc_s_scmo_config_info_2 {
2885 + S_SCMO_CONFIG_INFO_2_RMSK = 0xff00ff,
2886 + S_SCMO_CONFIG_INFO_2_NUM_GLOBAL_MONS_BMSK = 0xff0000,
2887 + S_SCMO_CONFIG_INFO_2_NUM_GLOBAL_MONS_SHFT = 0x10,
2888 + S_SCMO_CONFIG_INFO_2_VMID_WIDTH_BMSK = 0xff,
2889 + S_SCMO_CONFIG_INFO_2_VMID_WIDTH_SHFT = 0x0,
2890 +};
2891 +
2892 +#define S_SCMO_CONFIG_INFO_3_ADDR(b, n) \
2893 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000050)
2894 +enum bimc_s_scmo_config_info_3 {
2895 + S_SCMO_CONFIG_INFO_3_RMSK = 0xffffffff,
2896 + S_SCMO_CONFIG_INFO_3_RCH0_CTRL_DEPTH_BMSK = 0xff000000,
2897 + S_SCMO_CONFIG_INFO_3_RCH0_CTRL_DEPTH_SHFT = 0x18,
2898 + S_SCMO_CONFIG_INFO_3_RCH0_DEPTH_BMSK = 0xff0000,
2899 + S_SCMO_CONFIG_INFO_3_RCH0_DEPTH_SHFT = 0x10,
2900 + S_SCMO_CONFIG_INFO_3_BCH_DEPTH_BMSK = 0xff00,
2901 + S_SCMO_CONFIG_INFO_3_BCH_DEPTH_SHFT = 0x8,
2902 + S_SCMO_CONFIG_INFO_3_WCH_DEPTH_BMSK = 0xff,
2903 + S_SCMO_CONFIG_INFO_3_WCH_DEPTH_SHFT = 0x0,
2904 +};
2905 +
2906 +#define S_SCMO_CONFIG_INFO_4_ADDR(b, n) \
2907 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000060)
2908 +enum bimc_s_scmo_config_info_4 {
2909 + S_SCMO_CONFIG_INFO_4_RMSK = 0xffff,
2910 + S_SCMO_CONFIG_INFO_4_RCH1_CTRL_DEPTH_BMSK = 0xff00,
2911 + S_SCMO_CONFIG_INFO_4_RCH1_CTRL_DEPTH_SHFT = 0x8,
2912 + S_SCMO_CONFIG_INFO_4_RCH1_DEPTH_BMSK = 0xff,
2913 + S_SCMO_CONFIG_INFO_4_RCH1_DEPTH_SHFT = 0x0,
2914 +};
2915 +
2916 +#define S_SCMO_CONFIG_INFO_5_ADDR(b, n) \
2917 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000070)
2918 +enum bimc_s_scmo_config_info_5 {
2919 + S_SCMO_CONFIG_INFO_5_RMSK = 0xffff,
2920 + S_SCMO_CONFIG_INFO_5_DPE_CQ_DEPTH_BMSK = 0xff00,
2921 + S_SCMO_CONFIG_INFO_5_DPE_CQ_DEPTH_SHFT = 0x8,
2922 + S_SCMO_CONFIG_INFO_5_DDR_BUS_WIDTH_BMSK = 0xff,
2923 + S_SCMO_CONFIG_INFO_5_DDR_BUS_WIDTH_SHFT = 0x0,
2924 +};
2925 +
2926 +#define S_SCMO_CONFIG_INFO_6_ADDR(b, n) \
2927 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000080)
2928 +enum bimc_s_scmo_config_info_6 {
2929 + S_SCMO_CONFIG_INFO_6_RMSK = 0x1111,
2930 + S_SCMO_CONFIG_INFO_6_WBUFC_PIPE_BMSK = 0x1000,
2931 + S_SCMO_CONFIG_INFO_6_WBUFC_PIPE_SHFT = 0xc,
2932 + S_SCMO_CONFIG_INFO_6_RDOPT_PIPE_BMSK = 0x100,
2933 + S_SCMO_CONFIG_INFO_6_RDOPT_PIPE_SHFT = 0x8,
2934 + S_SCMO_CONFIG_INFO_6_ACHAN_INTF_PIPE_BMSK = 0x10,
2935 + S_SCMO_CONFIG_INFO_6_ACHAN_INTF_PIPE_SHFT = 0x4,
2936 + S_SCMO_CONFIG_INFO_6_ADDR_DECODE_HT_BMSK = 0x1,
2937 + S_SCMO_CONFIG_INFO_6_ADDR_DECODE_HT_SHFT = 0x0,
2938 +};
2939 +
2940 +#define S_SCMO_INT_STATUS_ADDR(b, n) \
2941 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000100)
2942 +enum bimc_s_scmo_int_status {
2943 + S_SCMO_INT_STATUS_RMSK = 0x1,
2944 + S_SCMO_INT_STATUS_ERR_OCCURED_BMSK = 0x1,
2945 + S_SCMO_INT_STATUS_ERR_OCCURED_SHFT = 0x0,
2946 +};
2947 +
2948 +#define S_SCMO_INT_CLR_ADDR(b, n) \
2949 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000108)
2950 +enum bimc_s_scmo_int_clr {
2951 + S_SCMO_INT_CLR_RMSK = 0x1,
2952 + S_SCMO_INT_CLR_IRQ_CLR_BMSK = 0x1,
2953 + S_SCMO_INT_CLR_IRQ_CLR_SHFT = 0x0,
2954 +};
2955 +
2956 +#define S_SCMO_INT_EN_ADDR(b, n) \
2957 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x0000010c)
2958 +enum bimc_s_scmo_int_en {
2959 + S_SCMO_INT_EN_RMSK = 0x1,
2960 + S_SCMO_INT_EN_IRQ_EN_BMSK = 0x1,
2961 + S_SCMO_INT_EN_IRQ_EN_SHFT = 0x0,
2962 +};
2963 +
2964 +#define S_SCMO_ESYN_ADDR_ADDR(b, n) \
2965 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000120)
2966 +enum bimc_s_scmo_esyn_addr {
2967 + S_SCMO_ESYN_ADDR_RMSK = 0xffffffff,
2968 + S_SCMO_ESYN_ADDR_ESYN_ADDR_ERR_ADDR_BMSK = 0xffffffff,
2969 + S_SCMO_ESYN_ADDR_ESYN_ADDR_ERR_ADDR_SHFT = 0x0,
2970 +};
2971 +
2972 +#define S_SCMO_ESYN_APACKET_0_ADDR(b, n) \
2973 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000128)
2974 +enum bimc_s_scmo_esyn_apacket_0 {
2975 + S_SCMO_ESYN_APACKET_0_RMSK = 0xff1fffff,
2976 + S_SCMO_ESYN_APACKET_0_ERR_ATID_BMSK = 0xff000000,
2977 + S_SCMO_ESYN_APACKET_0_ERR_ATID_SHFT = 0x18,
2978 + S_SCMO_ESYN_APACKET_0_ERR_AVMID_BMSK = 0x1f0000,
2979 + S_SCMO_ESYN_APACKET_0_ERR_AVMID_SHFT = 0x10,
2980 + S_SCMO_ESYN_APACKET_0_ERR_AMID_BMSK = 0xffff,
2981 + S_SCMO_ESYN_APACKET_0_ERR_AMID_SHFT = 0x0,
2982 +};
2983 +
2984 +#define S_SCMO_ESYN_APACKET_1_ADDR(b, n) \
2985 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x0000012c)
2986 +enum bimc_s_scmo_esyn_apacket_1 {
2987 + S_SCMO_ESYN_APACKET_1_RMSK = 0x10ff117,
2988 + S_SCMO_ESYN_APACKET_1_ERR_CODE_BMSK = 0x1000000,
2989 + S_SCMO_ESYN_APACKET_1_ERR_CODE_SHFT = 0x18,
2990 + S_SCMO_ESYN_APACKET_1_ERR_ALEN_BMSK = 0xf0000,
2991 + S_SCMO_ESYN_APACKET_1_ERR_ALEN_SHFT = 0x10,
2992 + S_SCMO_ESYN_APACKET_1_ERR_ASIZE_BMSK = 0xe000,
2993 + S_SCMO_ESYN_APACKET_1_ERR_ASIZE_SHFT = 0xd,
2994 + S_SCMO_ESYN_APACKET_1_ERR_ABURST_BMSK = 0x1000,
2995 + S_SCMO_ESYN_APACKET_1_ERR_ABURST_SHFT = 0xc,
2996 + S_SCMO_ESYN_APACKET_1_ERR_AEXCLUSIVE_BMSK = 0x100,
2997 + S_SCMO_ESYN_APACKET_1_ERR_AEXCLUSIVE_SHFT = 0x8,
2998 + S_SCMO_ESYN_APACKET_1_ERR_APRONTS_BMSK = 0x10,
2999 + S_SCMO_ESYN_APACKET_1_ERR_APRONTS_SHFT = 0x4,
3000 + S_SCMO_ESYN_APACKET_1_ERR_AOOORD_BMSK = 0x4,
3001 + S_SCMO_ESYN_APACKET_1_ERR_AOOORD_SHFT = 0x2,
3002 + S_SCMO_ESYN_APACKET_1_ERR_AOOOWR_BMSK = 0x2,
3003 + S_SCMO_ESYN_APACKET_1_ERR_AOOOWR_SHFT = 0x1,
3004 + S_SCMO_ESYN_APACKET_1_ERR_AWRITE_BMSK = 0x1,
3005 + S_SCMO_ESYN_APACKET_1_ERR_AWRITE_SHFT = 0x0,
3006 +};
3007 +
3008 +#define S_SCMO_CLK_CTRL_ADDR(b, n) \
3009 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000200)
3010 +enum bimc_s_scmo_clk_ctrl {
3011 + S_SCMO_CLK_CTRL_RMSK = 0xffff1111,
3012 + S_SCMO_CLK_CTRL_PEN_CMD_CG_EN_BMSK = 0x10000,
3013 + S_SCMO_CLK_CTRL_PEN_CMD_CG_EN_SHFT = 0x10,
3014 + S_SCMO_CLK_CTRL_RCH_CG_EN_BMSK = 0x1000,
3015 + S_SCMO_CLK_CTRL_RCH_CG_EN_SHFT = 0xc,
3016 + S_SCMO_CLK_CTRL_FLUSH_CG_EN_BMSK = 0x100,
3017 + S_SCMO_CLK_CTRL_FLUSH_CG_EN_SHFT = 0x8,
3018 + S_SCMO_CLK_CTRL_WCH_CG_EN_BMSK = 0x10,
3019 + S_SCMO_CLK_CTRL_WCH_CG_EN_SHFT = 0x4,
3020 + S_SCMO_CLK_CTRL_ACH_CG_EN_BMSK = 0x1,
3021 + S_SCMO_CLK_CTRL_ACH_CG_EN_SHFT = 0x0,
3022 +};
3023 +
3024 +#define S_SCMO_SLV_INTERLEAVE_CFG_ADDR(b, n) \
3025 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000400)
3026 +enum bimc_s_scmo_slv_interleave_cfg {
3027 + S_SCMO_SLV_INTERLEAVE_CFG_RMSK = 0xff,
3028 + S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS1_BMSK = 0x10,
3029 + S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS1_SHFT = 0x4,
3030 + S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS0_BMSK = 0x1,
3031 + S_SCMO_SLV_INTERLEAVE_CFG_INTERLEAVE_CS0_SHFT = 0x0,
3032 +};
3033 +
3034 +#define S_SCMO_ADDR_BASE_CSn_ADDR(b, n, o) \
3035 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000410 + 0x4 * (o))
3036 +enum bimc_s_scmo_addr_base_csn {
3037 + S_SCMO_ADDR_BASE_CSn_RMSK = 0xffff,
3038 + S_SCMO_ADDR_BASE_CSn_MAXn = 1,
3039 + S_SCMO_ADDR_BASE_CSn_ADDR_BASE_BMSK = 0xfc,
3040 + S_SCMO_ADDR_BASE_CSn_ADDR_BASE_SHFT = 0x2,
3041 +};
3042 +
3043 +#define S_SCMO_ADDR_MAP_CSn_ADDR(b, n, o) \
3044 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000420 + 0x4 * (o))
3045 +enum bimc_s_scmo_addr_map_csn {
3046 + S_SCMO_ADDR_MAP_CSn_RMSK = 0xffff,
3047 + S_SCMO_ADDR_MAP_CSn_MAXn = 1,
3048 + S_SCMO_ADDR_MAP_CSn_RANK_EN_BMSK = 0x8000,
3049 + S_SCMO_ADDR_MAP_CSn_RANK_EN_SHFT = 0xf,
3050 + S_SCMO_ADDR_MAP_CSn_ADDR_MODE_BMSK = 0x1000,
3051 + S_SCMO_ADDR_MAP_CSn_ADDR_MODE_SHFT = 0xc,
3052 + S_SCMO_ADDR_MAP_CSn_BANK_SIZE_BMSK = 0x100,
3053 + S_SCMO_ADDR_MAP_CSn_BANK_SIZE_SHFT = 0x8,
3054 + S_SCMO_ADDR_MAP_CSn_ROW_SIZE_BMSK = 0x30,
3055 + S_SCMO_ADDR_MAP_CSn_ROW_SIZE_SHFT = 0x4,
3056 + S_SCMO_ADDR_MAP_CSn_COL_SIZE_BMSK = 0x3,
3057 + S_SCMO_ADDR_MAP_CSn_COL_SIZE_SHFT = 0x0,
3058 +};
3059 +
3060 +#define S_SCMO_ADDR_MASK_CSn_ADDR(b, n, o) \
3061 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000430 + 0x4 * (0))
3062 +enum bimc_s_scmo_addr_mask_csn {
3063 + S_SCMO_ADDR_MASK_CSn_RMSK = 0xffff,
3064 + S_SCMO_ADDR_MASK_CSn_MAXn = 1,
3065 + S_SCMO_ADDR_MASK_CSn_ADDR_MASK_BMSK = 0xfc,
3066 + S_SCMO_ADDR_MASK_CSn_ADDR_MASK_SHFT = 0x2,
3067 +};
3068 +
3069 +#define S_SCMO_SLV_STATUS_ADDR(b, n) \
3070 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000450)
3071 +enum bimc_s_scmo_slv_status {
3072 + S_SCMO_SLV_STATUS_RMSK = 0xff3,
3073 + S_SCMO_SLV_STATUS_GLOBAL_MONS_IN_USE_BMSK = 0xff0,
3074 + S_SCMO_SLV_STATUS_GLOBAL_MONS_IN_USE_SHFT = 0x4,
3075 + S_SCMO_SLV_STATUS_SLAVE_IDLE_BMSK = 0x3,
3076 + S_SCMO_SLV_STATUS_SLAVE_IDLE_SHFT = 0x0,
3077 +};
3078 +
3079 +#define S_SCMO_CMD_BUF_CFG_ADDR(b, n) \
3080 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000500)
3081 +enum bimc_s_scmo_cmd_buf_cfg {
3082 + S_SCMO_CMD_BUF_CFG_RMSK = 0xf1f,
3083 + S_SCMO_CMD_BUF_CFG_CMD_ORDERING_BMSK = 0x300,
3084 + S_SCMO_CMD_BUF_CFG_CMD_ORDERING_SHFT = 0x8,
3085 + S_SCMO_CMD_BUF_CFG_HP_CMD_AREQPRIO_MAP_BMSK = 0x10,
3086 + S_SCMO_CMD_BUF_CFG_HP_CMD_AREQPRIO_MAP_SHFT = 0x4,
3087 + S_SCMO_CMD_BUF_CFG_HP_CMD_Q_DEPTH_BMSK = 0x7,
3088 + S_SCMO_CMD_BUF_CFG_HP_CMD_Q_DEPTH_SHFT = 0x0,
3089 +};
3090 +
3091 +#define S_SCM_CMD_BUF_STATUS_ADDR(b, n) \
3092 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000520)
3093 +enum bimc_s_scm_cmd_buf_status {
3094 + S_SCMO_CMD_BUF_STATUS_RMSK = 0x77,
3095 + S_SCMO_CMD_BUF_STATUS_HP_CMD_BUF_ENTRIES_IN_USE_BMSK = 0x70,
3096 + S_SCMO_CMD_BUF_STATUS_HP_CMD_BUF_ENTRIES_IN_USE_SHFT = 0x4,
3097 + S_SCMO_CMD_BUF_STATUS_LP_CMD_BUF_ENTRIES_IN_USE_BMSK = 0x7,
3098 + S_SCMO_CMD_BUF_STATUS_LP_CMD_BUF_ENTRIES_IN_USE_SHFT = 0x0,
3099 +};
3100 +
3101 +#define S_SCMO_RCH_SEL_ADDR(b, n) \
3102 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000540)
3103 +enum bimc_s_scmo_rch_sel {
3104 + S_SCMO_RCH_SEL_RMSK = 0xffffffff,
3105 + S_SCMO_CMD_BUF_STATUS_RCH_PORTS_BMSK = 0xffffffff,
3106 + S_SCMO_CMD_BUF_STATUS_RCH_PORTS_SHFT = 0x0,
3107 +};
3108 +
3109 +#define S_SCMO_RCH_BKPR_CFG_ADDR(b, n) \
3110 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000544)
3111 +enum bimc_s_scmo_rch_bkpr_cfg {
3112 + S_SCMO_RCH_BKPR_CFG_RMSK = 0xffffffff,
3113 + S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_HI_TH_BMSK = 0x3f000000,
3114 + S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_HI_TH_SHFT = 0x18,
3115 + S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_LO_TH_BMSK = 0x3f0000,
3116 + S_SCMO_RCH_BKPR_CFG_RCH1_FIFO_BKPR_LO_TH_SHFT = 0x10,
3117 + S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_HI_TH_BMSK = 0x3f00,
3118 + S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_HI_TH_SHFT = 0x8,
3119 + S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_LO_TH_BMSK = 0x3f,
3120 + S_SCMO_RCH_BKPR_CFG_RCH0_FIFO_BKPR_LO_TH_SHFT = 0x0,
3121 +};
3122 +
3123 +#define S_SCMO_RCH_STATUS_ADDR(b, n) \
3124 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000560)
3125 +enum bimc_s_scmo_rch_status {
3126 + S_SCMO_RCH_STATUS_RMSK = 0x33333,
3127 + S_SCMO_RCH_STATUS_PRQ_FIFO_FULL_BMSK = 0x20000,
3128 + S_SCMO_RCH_STATUS_PRQ_FIFO_FULL_SHFT = 0x11,
3129 + S_SCMO_RCH_STATUS_PRQ_FIFO_EMPTY_BMSK = 0x10000,
3130 + S_SCMO_RCH_STATUS_PRQ_FIFO_EMPTY_SHFT = 0x10,
3131 + S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_FULL_BMSK = 0x2000,
3132 + S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_FULL_SHFT = 0xd,
3133 + S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_EMPTY_BMSK = 0x1000,
3134 + S_SCMO_RCH_STATUS_RCH1_QUAL_FIFO_EMPTY_SHFT = 0xc,
3135 + S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_FULL_BMSK = 0x200,
3136 + S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_FULL_SHFT = 0x9,
3137 + S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_EMPTY_BMSK = 0x100,
3138 + S_SCMO_RCH_STATUS_RCH1_DATA_FIFO_EMPTY_SHFT = 0x8,
3139 + S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_FULL_BMSK = 0x20,
3140 + S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_FULL_SHFT = 0x5,
3141 + S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_EMPTY_BMSK = 0x10,
3142 + S_SCMO_RCH_STATUS_RCH0_QUAL_FIFO_EMPTY_SHFT = 0x4,
3143 + S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_FULL_BMSK = 0x2,
3144 + S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_FULL_SHFT = 0x1,
3145 + S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_EMPTY_BMSK = 0x1,
3146 + S_SCMO_RCH_STATUS_RCH0_DATA_FIFO_EMPTY_SHFT = 0x0,
3147 +};
3148 +
3149 +#define S_SCMO_WCH_BUF_CFG_ADDR(b, n) \
3150 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000580)
3151 +enum bimc_s_scmo_wch_buf_cfg {
3152 + S_SCMO_WCH_BUF_CFG_RMSK = 0xff,
3153 + S_SCMO_WCH_BUF_CFG_WRITE_BLOCK_READ_BMSK = 0x10,
3154 + S_SCMO_WCH_BUF_CFG_WRITE_BLOCK_READ_SHFT = 0x4,
3155 + S_SCMO_WCH_BUF_CFG_COALESCE_EN_BMSK = 0x1,
3156 + S_SCMO_WCH_BUF_CFG_COALESCE_EN_SHFT = 0x0,
3157 +};
3158 +
3159 +#define S_SCMO_WCH_STATUS_ADDR(b, n) \
3160 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x000005a0)
3161 +enum bimc_s_scmo_wch_status {
3162 + S_SCMO_WCH_STATUS_RMSK = 0x333,
3163 + S_SCMO_WCH_STATUS_BRESP_FIFO_FULL_BMSK = 0x200,
3164 + S_SCMO_WCH_STATUS_BRESP_FIFO_FULL_SHFT = 0x9,
3165 + S_SCMO_WCH_STATUS_BRESP_FIFO_EMPTY_BMSK = 0x100,
3166 + S_SCMO_WCH_STATUS_BRESP_FIFO_EMPTY_SHFT = 0x8,
3167 + S_SCMO_WCH_STATUS_WDATA_FIFO_FULL_BMSK = 0x20,
3168 + S_SCMO_WCH_STATUS_WDATA_FIFO_FULL_SHFT = 0x5,
3169 + S_SCMO_WCH_STATUS_WDATA_FIFO_EMPTY_BMSK = 0x10,
3170 + S_SCMO_WCH_STATUS_WDATA_FIFO_EMPTY_SHFT = 0x4,
3171 + S_SCMO_WCH_STATUS_WBUF_FULL_BMSK = 0x2,
3172 + S_SCMO_WCH_STATUS_WBUF_FULL_SHFT = 0x1,
3173 + S_SCMO_WCH_STATUS_WBUF_EMPTY_BMSK = 0x1,
3174 + S_SCMO_WCH_STATUS_WBUF_EMPTY_SHFT = 0x0,
3175 +};
3176 +
3177 +#define S_SCMO_FLUSH_CFG_ADDR(b, n) \
3178 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x000005c0)
3179 +enum bimc_s_scmo_flush_cfg {
3180 + S_SCMO_FLUSH_CFG_RMSK = 0xffffffff,
3181 + S_SCMO_FLUSH_CFG_FLUSH_IN_ORDER_BMSK = 0x10000000,
3182 + S_SCMO_FLUSH_CFG_FLUSH_IN_ORDER_SHFT = 0x1c,
3183 + S_SCMO_FLUSH_CFG_FLUSH_IDLE_DELAY_BMSK = 0x3ff0000,
3184 + S_SCMO_FLUSH_CFG_FLUSH_IDLE_DELAY_SHFT = 0x10,
3185 + S_SCMO_FLUSH_CFG_FLUSH_UPPER_LIMIT_BMSK = 0xf00,
3186 + S_SCMO_FLUSH_CFG_FLUSH_UPPER_LIMIT_SHFT = 0x8,
3187 + S_SCMO_FLUSH_CFG_FLUSH_LOWER_LIMIT_BMSK = 0xf,
3188 + S_SCMO_FLUSH_CFG_FLUSH_LOWER_LIMIT_SHFT = 0x0,
3189 +};
3190 +
3191 +#define S_SCMO_FLUSH_CMD_ADDR(b, n) \
3192 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x000005c4)
3193 +enum bimc_s_scmo_flush_cmd {
3194 + S_SCMO_FLUSH_CMD_RMSK = 0xf,
3195 + S_SCMO_FLUSH_CMD_FLUSH_ALL_BUF_BMSK = 0x3,
3196 + S_SCMO_FLUSH_CMD_FLUSH_ALL_BUF_SHFT = 0x0,
3197 +};
3198 +
3199 +#define S_SCMO_CMD_OPT_CFG0_ADDR(b, n) \
3200 + (S_SCM0_REG_BASE(b) + (0x8000 * (n)) + 0x00000700)
3201 +enum bimc_s_scmo_cmd_opt_cfg0 {
3202 + S_SCMO_CMD_OPT_CFG0_RMSK = 0xffffff,
3203 + S_SCMO_CMD_OPT_CFG0_IGNORE_BANK_UNAVL_BMSK = 0x100000,
3204 + S_SCMO_CMD_OPT_CFG0_IGNORE_BANK_UNAVL_SHFT = 0x14,
3205 + S_SCMO_CMD_OPT_CFG0_MASK_CMDOUT_PRI_BMSK = 0x10000,
3206 + S_SCMO_CMD_OPT_CFG0_MASK_CMDOUT_PRI_SHFT = 0x10,
3207 + S_SCMO_CMD_OPT_CFG0_DPE_CMD_REORDERING_BMSK = 0x1000,
3208 + S_SCMO_CMD_OPT_CFG0_DPE_CMD_REORDERING_SHFT = 0xc,
3209 + S_SCMO_CMD_OPT_CFG0_WR_OPT_EN_BMSK = 0x100,
3210 + S_SCMO_CMD_OPT_CFG0_WR_OPT_EN_SHFT = 0x8,
3211 + S_SCMO_CMD_OPT_CFG0_RD_OPT_EN_BMSK = 0x10,
3212 + S_SCMO_CMD_OPT_CFG0_RD_OPT_EN_SHFT = 0x4,
3213 + S_SCMO_CMD_OPT_CFG0_PAGE_MGMT_POLICY_BMSK = 0x1,
3214 + S_SCMO_CMD_OPT_CFG0_PAGE_MGMT_POLICY_SHFT = 0x0,
3215 +};
3216 +
3217 +#define S_SCMO_CMD_OPT_CFG1_ADDR(b, n) \
3218 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000704)
3219 +enum bimc_s_scmo_cmd_opt_cfg1 {
3220 + S_SCMO_CMD_OPT_CFG1_RMSK = 0xffffffff,
3221 + S_SCMO_CMD_OPT_CFG1_HSTP_CMD_TIMEOUT_BMSK = 0x1f000000,
3222 + S_SCMO_CMD_OPT_CFG1_HSTP_CMD_TIMEOUT_SHFT = 0x18,
3223 + S_SCMO_CMD_OPT_CFG1_HP_CMD_TIMEOUT_BMSK = 0x1f0000,
3224 + S_SCMO_CMD_OPT_CFG1_HP_CMD_TIMEOUT_SHFT = 0x10,
3225 + S_SCMO_CMD_OPT_CFG1_MP_CMD_TIMEOUT_BMSK = 0x1f00,
3226 + S_SCMO_CMD_OPT_CFG1_MP_CMD_TIMEOUT_SHFT = 0x8,
3227 + S_SCMO_CMD_OPT_CFG1_LP_CMD_TIMEOUT_BMSK = 0x1f,
3228 + S_SCMO_CMD_OPT_CFG1_LP_CMD_TIMEOUT_SHFT = 0x0,
3229 +};
3230 +
3231 +#define S_SCMO_CMD_OPT_CFG2_ADDR(b, n) \
3232 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x00000708)
3233 +enum bimc_s_scmo_cmd_opt_cfg2 {
3234 + S_SCMO_CMD_OPT_CFG2_RMSK = 0xff,
3235 + S_SCMO_CMD_OPT_CFG2_RWOPT_CMD_TIMEOUT_BMSK = 0xf,
3236 + S_SCMO_CMD_OPT_CFG2_RWOPT_CMD_TIMEOUT_SHFT = 0x0,
3237 +};
3238 +
3239 +#define S_SCMO_CMD_OPT_CFG3_ADDR(b, n) \
3240 + (S_SCMO_REG_BASE(b) + (0x8000 * (n)) + 0x0000070c)
3241 +enum bimc_s_scmo_cmd_opt_cfg3 {
3242 + S_SCMO_CMD_OPT_CFG3_RMSK = 0xff,
3243 + S_SCMO_CMD_OPT_CFG3_FLUSH_CMD_TIMEOUT_BMSK = 0xf,
3244 + S_SCMO_CMD_OPT_CFG3_FLUSH_CMD_TIMEOUT_SHFT = 0x0,
3245 +};
3246 +
3247 +/* S_SWAY_GENERIC */
3248 +#define S_SWAY_REG_BASE(b) ((b) + 0x00048000)
3249 +
3250 +#define S_SWAY_CONFIG_INFO_0_ADDR(b, n) \
3251 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000020)
3252 +enum bimc_s_sway_config_info_0 {
3253 + S_SWAY_CONFIG_INFO_0_RMSK = 0xff0000ff,
3254 + S_SWAY_CONFIG_INFO_0_SYNC_MODE_BMSK = 0xff000000,
3255 + S_SWAY_CONFIG_INFO_0_SYNC_MODE_SHFT = 0x18,
3256 + S_SWAY_CONFIG_INFO_0_FUNC_BMSK = 0xff,
3257 + S_SWAY_CONFIG_INFO_0_FUNC_SHFT = 0x0,
3258 +};
3259 +
3260 +#define S_SWAY_CONFIG_INFO_1_ADDR(b, n) \
3261 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000030)
3262 +enum bimc_s_sway_config_info_1 {
3263 + S_SWAY_CONFIG_INFO_1_RMSK = 0xffffffff,
3264 + S_SWAY_CONFIG_INFO_1_MPORT_CONNECTIVITY_BMSK = 0xffffffff,
3265 + S_SWAY_CONFIG_INFO_1_MPORT_CONNECTIVITY_SHFT = 0x0,
3266 +};
3267 +
3268 +#define S_SWAY_CONFIG_INFO_2_ADDR(b, n) \
3269 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000040)
3270 +enum bimc_s_sway_config_info_2 {
3271 + S_SWAY_CONFIG_INFO_2_RMSK = 0xffff0000,
3272 + S_SWAY_CONFIG_INFO_2_MPORT_CONNECTIVITY_BMSK = 0xffff0000,
3273 + S_SWAY_CONFIG_INFO_2_MPORT_CONNECTIVITY_SHFT = 0x10,
3274 +};
3275 +
3276 +#define S_SWAY_CONFIG_INFO_3_ADDR(b, n) \
3277 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000050)
3278 +enum bimc_s_sway_config_info_3 {
3279 + S_SWAY_CONFIG_INFO_3_RMSK = 0xffffffff,
3280 + S_SWAY_CONFIG_INFO_3_RCH0_DEPTH_BMSK = 0xff000000,
3281 + S_SWAY_CONFIG_INFO_3_RCH0_DEPTH_SHFT = 0x18,
3282 + S_SWAY_CONFIG_INFO_3_BCH_DEPTH_BMSK = 0xff0000,
3283 + S_SWAY_CONFIG_INFO_3_BCH_DEPTH_SHFT = 0x10,
3284 + S_SWAY_CONFIG_INFO_3_WCH_DEPTH_BMSK = 0xff,
3285 + S_SWAY_CONFIG_INFO_3_WCH_DEPTH_SHFT = 0x0,
3286 +};
3287 +
3288 +#define S_SWAY_CONFIG_INFO_4_ADDR(b, n) \
3289 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000060)
3290 +enum bimc_s_sway_config_info_4 {
3291 + S_SWAY_CONFIG_INFO_4_RMSK = 0x800000ff,
3292 + S_SWAY_CONFIG_INFO_4_DUAL_RCH_EN_BMSK = 0x80000000,
3293 + S_SWAY_CONFIG_INFO_4_DUAL_RCH_EN_SHFT = 0x1f,
3294 + S_SWAY_CONFIG_INFO_4_RCH1_DEPTH_BMSK = 0xff,
3295 + S_SWAY_CONFIG_INFO_4_RCH1_DEPTH_SHFT = 0x0,
3296 +};
3297 +
3298 +#define S_SWAY_CONFIG_INFO_5_ADDR(b, n) \
3299 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000070)
3300 +enum bimc_s_sway_config_info_5 {
3301 + S_SWAY_CONFIG_INFO_5_RMSK = 0x800000ff,
3302 + S_SWAY_CONFIG_INFO_5_QCH_EN_BMSK = 0x80000000,
3303 + S_SWAY_CONFIG_INFO_5_QCH_EN_SHFT = 0x1f,
3304 + S_SWAY_CONFIG_INFO_5_QCH_DEPTH_BMSK = 0xff,
3305 + S_SWAY_CONFIG_INFO_5_QCH_DEPTH_SHFT = 0x0,
3306 +};
3307 +
3308 +#define S_SWAY_CONFIG_INFO_6_ADDR(b, n) \
3309 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000080)
3310 +enum bimc_s_sway_config_info_6 {
3311 + S_SWAY_CONFIG_INFO_6_RMSK = 0x1,
3312 + S_SWAY_CONFIG_INFO_6_S2SW_PIPELINE_EN_BMSK = 0x1,
3313 + S_SWAY_CONFIG_INFO_6_S2SW_PIPELINE_EN_SHFT = 0x0,
3314 +};
3315 +
3316 +#define S_SWAY_INT_STATUS_ADDR(b, n) \
3317 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000100)
3318 +enum bimc_s_sway_int_status {
3319 + S_SWAY_INT_STATUS_RMSK = 0x3,
3320 + S_SWAY_INT_STATUS_RFU_BMSK = 0x3,
3321 + S_SWAY_INT_STATUS_RFU_SHFT = 0x0,
3322 +};
3323 +
3324 +#define S_SWAY_INT_CLR_ADDR(b, n) \
3325 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000108)
3326 +enum bimc_s_sway_int_clr {
3327 + S_SWAY_INT_CLR_RMSK = 0x3,
3328 + S_SWAY_INT_CLR_RFU_BMSK = 0x3,
3329 + S_SWAY_INT_CLR_RFU_SHFT = 0x0,
3330 +};
3331 +
3332 +
3333 +#define S_SWAY_INT_EN_ADDR(b, n) \
3334 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x0000010c)
3335 +enum bimc_s_sway_int_en {
3336 + S_SWAY_INT_EN_RMSK = 0x3,
3337 + S_SWAY_INT_EN_RFU_BMSK = 0x3,
3338 + S_SWAY_INT_EN_RFU_SHFT = 0x0,
3339 +};
3340 +
3341 +#define S_SWAY_CLK_CTRL_ADDR(b, n) \
3342 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000200)
3343 +enum bimc_s_sway_clk_ctrl {
3344 + S_SWAY_CLK_CTRL_RMSK = 0x3,
3345 + S_SWAY_CLK_CTRL_SLAVE_CLK_GATING_EN_BMSK = 0x2,
3346 + S_SWAY_CLK_CTRL_SLAVE_CLK_GATING_EN_SHFT = 0x1,
3347 + S_SWAY_CLK_CTRL_CORE_CLK_GATING_EN_BMSK = 0x1,
3348 + S_SWAY_CLK_CTRL_CORE_CLK_GATING_EN_SHFT = 0x0,
3349 +};
3350 +
3351 +#define S_SWAY_RCH_SEL_ADDR(b, n) \
3352 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000210)
3353 +enum bimc_s_sway_rch_sel {
3354 + S_SWAY_RCH_SEL_RMSK = 0x7f,
3355 + S_SWAY_RCH_SEL_UNUSED_BMSK = 0x7f,
3356 + S_SWAY_RCH_SEL_UNUSED_SHFT = 0x0,
3357 +};
3358 +
3359 +
3360 +#define S_SWAY_MAX_OUTSTANDING_REQS_ADDR(b, n) \
3361 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000220)
3362 +enum bimc_s_sway_max_outstanding_reqs {
3363 + S_SWAY_MAX_OUTSTANDING_REQS_RMSK = 0xffff,
3364 + S_SWAY_MAX_OUTSTANDING_REQS_WRITE_BMSK = 0xff00,
3365 + S_SWAY_MAX_OUTSTANDING_REQS_WRITE_SHFT = 0x8,
3366 + S_SWAY_MAX_OUTSTANDING_REQS_READ_BMSK = 0xff,
3367 + S_SWAY_MAX_OUTSTANDING_REQS_READ_SHFT = 0x0,
3368 +};
3369 +
3370 +
3371 +#define S_SWAY_BUF_STATUS_0_ADDR(b, n) \
3372 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000400)
3373 +enum bimc_s_sway_buf_status_0 {
3374 + S_SWAY_BUF_STATUS_0_RMSK = 0xf0300f03,
3375 + S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_FULL_BMSK = 0x80000000,
3376 + S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_FULL_SHFT = 0x1f,
3377 + S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_EMPTY_BMSK = 0x40000000,
3378 + S_SWAY_BUF_STATUS_0_RCH0_DATA_RD_EMPTY_SHFT = 0x1e,
3379 + S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_FULL_BMSK = 0x20000000,
3380 + S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_FULL_SHFT = 0x1d,
3381 + S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_EMPTY_BMSK = 0x10000000,
3382 + S_SWAY_BUF_STATUS_0_RCH0_CTRL_RD_EMPTY_SHFT = 0x1c,
3383 + S_SWAY_BUF_STATUS_0_BCH_RD_FULL_BMSK = 0x200000,
3384 + S_SWAY_BUF_STATUS_0_BCH_RD_FULL_SHFT = 0x15,
3385 + S_SWAY_BUF_STATUS_0_BCH_RD_EMPTY_BMSK = 0x100000,
3386 + S_SWAY_BUF_STATUS_0_BCH_RD_EMPTY_SHFT = 0x14,
3387 + S_SWAY_BUF_STATUS_0_WCH_DATA_WR_FULL_BMSK = 0x800,
3388 + S_SWAY_BUF_STATUS_0_WCH_DATA_WR_FULL_SHFT = 0xb,
3389 + S_SWAY_BUF_STATUS_0_WCH_DATA_WR_EMPTY_BMSK = 0x400,
3390 + S_SWAY_BUF_STATUS_0_WCH_DATA_WR_EMPTY_SHFT = 0xa,
3391 + S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_FULL_BMSK = 0x200,
3392 + S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_FULL_SHFT = 0x9,
3393 + S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_EMPTY_BMSK = 0x100,
3394 + S_SWAY_BUF_STATUS_0_WCH_CTRL_WR_EMPTY_SHFT = 0x8,
3395 + S_SWAY_BUF_STATUS_0_ACH_WR_FULL_BMSK = 0x2,
3396 + S_SWAY_BUF_STATUS_0_ACH_WR_FULL_SHFT = 0x1,
3397 + S_SWAY_BUF_STATUS_0_ACH_WR_EMPTY_BMSK = 0x1,
3398 + S_SWAY_BUF_STATUS_0_ACH_WR_EMPTY_SHFT = 0x0,
3399 +};
3400 +
3401 +#define S_SWAY_BUF_STATUS_1_ADDR(b, n) \
3402 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000410)
3403 +enum bimc_s_sway_buf_status_1 {
3404 + S_SWAY_BUF_STATUS_1_RMSK = 0xf0,
3405 + S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_FULL_BMSK = 0x80,
3406 + S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_FULL_SHFT = 0x7,
3407 + S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_EMPTY_BMSK = 0x40,
3408 + S_SWAY_BUF_STATUS_1_RCH1_DATA_RD_EMPTY_SHFT = 0x6,
3409 + S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_FULL_BMSK = 0x20,
3410 + S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_FULL_SHFT = 0x5,
3411 + S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_EMPTY_BMSK = 0x10,
3412 + S_SWAY_BUF_STATUS_1_RCH1_CTRL_RD_EMPTY_SHFT = 0x4,
3413 +};
3414 +
3415 +#define S_SWAY_BUF_STATUS_2_ADDR(b, n) \
3416 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000420)
3417 +enum bimc_s_sway_buf_status_2 {
3418 + S_SWAY_BUF_STATUS_2_RMSK = 0x30,
3419 + S_SWAY_BUF_STATUS_2_QCH_RD_FULL_BMSK = 0x20,
3420 + S_SWAY_BUF_STATUS_2_QCH_RD_FULL_SHFT = 0x5,
3421 + S_SWAY_BUF_STATUS_2_QCH_RD_EMPTY_BMSK = 0x10,
3422 + S_SWAY_BUF_STATUS_2_QCH_RD_EMPTY_SHFT = 0x4,
3423 +};
3424 +
3425 +/* S_ARB_GENERIC */
3426 +
3427 +#define S_ARB_REG_BASE(b) ((b) + 0x00049000)
3428 +
3429 +#define S_ARB_COMPONENT_INFO_ADDR(b, n) \
3430 + (S_SWAY_REG_BASE(b) + (0x8000 * (n)) + 0x00000000)
3431 +enum bimc_s_arb_component_info {
3432 + S_ARB_COMPONENT_INFO_RMSK = 0xffffff,
3433 + S_ARB_COMPONENT_INFO_INSTANCE_BMSK = 0xff0000,
3434 + S_ARB_COMPONENT_INFO_INSTANCE_SHFT = 0x10,
3435 + S_ARB_COMPONENT_INFO_SUB_TYPE_BMSK = 0xff00,
3436 + S_ARB_COMPONENT_INFO_SUB_TYPE_SHFT = 0x8,
3437 + S_ARB_COMPONENT_INFO_TYPE_BMSK = 0xff,
3438 + S_ARB_COMPONENT_INFO_TYPE_SHFT = 0x0,
3439 +};
3440 +
3441 +#define S_ARB_CONFIG_INFO_0_ADDR(b, n) \
3442 + (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000020)
3443 +enum bimc_s_arb_config_info_0 {
3444 + S_ARB_CONFIG_INFO_0_RMSK = 0x800000ff,
3445 + S_ARB_CONFIG_INFO_0_ARB2SW_PIPELINE_EN_BMSK = 0x80000000,
3446 + S_ARB_CONFIG_INFO_0_ARB2SW_PIPELINE_EN_SHFT = 0x1f,
3447 + S_ARB_CONFIG_INFO_0_FUNC_BMSK = 0xff,
3448 + S_ARB_CONFIG_INFO_0_FUNC_SHFT = 0x0,
3449 +};
3450 +
3451 +#define S_ARB_CONFIG_INFO_1_ADDR(b, n) \
3452 + (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000030)
3453 +enum bimc_s_arb_config_info_1 {
3454 + S_ARB_CONFIG_INFO_1_RMSK = 0xffffffff,
3455 + S_ARB_CONFIG_INFO_1_MPORT_CONNECTIVITY_BMSK = 0xffffffff,
3456 + S_ARB_CONFIG_INFO_1_MPORT_CONNECTIVITY_SHFT = 0x0,
3457 +};
3458 +
3459 +#define S_ARB_CLK_CTRL_ADDR(b) \
3460 + (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000200)
3461 +enum bimc_s_arb_clk_ctrl {
3462 + S_ARB_CLK_CTRL_RMSK = 0x1,
3463 + S_ARB_CLK_CTRL_SLAVE_CLK_GATING_EN_BMSK = 0x2,
3464 + S_ARB_CLK_CTRL_SLAVE_CLK_GATING_EN_SHFT = 0x1,
3465 + S_ARB_CLK_CTRL_CORE_CLK_GATING_EN_BMSK = 0x1,
3466 + S_ARB_CLK_CTRL_CORE_CLK_GATING_EN_SHFT = 0x0,
3467 + S_ARB_CLK_CTRL_CLK_GATING_EN_BMSK = 0x1,
3468 + S_ARB_CLK_CTRL_CLK_GATING_EN_SHFT = 0x0,
3469 +};
3470 +
3471 +#define S_ARB_MODE_ADDR(b, n) \
3472 + (S_ARB_REG_BASE(b) + (0x8000 * (n)) + 0x00000210)
3473 +enum bimc_s_arb_mode {
3474 + S_ARB_MODE_RMSK = 0xf0000001,
3475 + S_ARB_MODE_WR_GRANTS_AHEAD_BMSK = 0xf0000000,
3476 + S_ARB_MODE_WR_GRANTS_AHEAD_SHFT = 0x1c,
3477 + S_ARB_MODE_PRIO_RR_EN_BMSK = 0x1,
3478 + S_ARB_MODE_PRIO_RR_EN_SHFT = 0x0,
3479 +};
3480 +
3481 +#define BKE_HEALTH_MASK \
3482 + (M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_BMSK |\
3483 + M_BKE_HEALTH_0_CONFIG_AREQPRIO_BMSK |\
3484 + M_BKE_HEALTH_0_CONFIG_PRIOLVL_BMSK)
3485 +
3486 +#define BKE_HEALTH_VAL(limit, areq, plvl) \
3487 + ((((limit) << M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_SHFT) & \
3488 + M_BKE_HEALTH_0_CONFIG_LIMIT_CMDS_BMSK) | \
3489 + (((areq) << M_BKE_HEALTH_0_CONFIG_AREQPRIO_SHFT) & \
3490 + M_BKE_HEALTH_0_CONFIG_AREQPRIO_BMSK) | \
3491 + (((plvl) << M_BKE_HEALTH_0_CONFIG_PRIOLVL_SHFT) & \
3492 + M_BKE_HEALTH_0_CONFIG_PRIOLVL_BMSK))
3493 +
3494 +#define MAX_GRANT_PERIOD \
3495 + (M_BKE_GP_GP_BMSK >> \
3496 + M_BKE_GP_GP_SHFT)
3497 +
3498 +#define MAX_GC \
3499 + (M_BKE_GC_GC_BMSK >> \
3500 + (M_BKE_GC_GC_SHFT + 1))
3501 +
3502 +static int bimc_div(int64_t *a, uint32_t b)
3503 +{
3504 + if ((*a > 0) && (*a < b)) {
3505 + *a = 0;
3506 + return 1;
3507 + } else {
3508 + return do_div(*a, b);
3509 + }
3510 +}
3511 +
3512 +#define ENABLE(val) ((val) == 1 ? 1 : 0)
3513 +void msm_bus_bimc_set_mas_clk_gate(struct msm_bus_bimc_info *binfo,
3514 + uint32_t mas_index, struct msm_bus_bimc_clk_gate *bgate)
3515 +{
3516 + uint32_t val, mask, reg_val;
3517 + void __iomem *addr;
3518 +
3519 + reg_val = readl_relaxed(M_CLK_CTRL_ADDR(binfo->base,
3520 + mas_index)) & M_CLK_CTRL_RMSK;
3521 + addr = M_CLK_CTRL_ADDR(binfo->base, mas_index);
3522 + mask = (M_CLK_CTRL_MAS_CLK_GATING_EN_BMSK |
3523 + M_CLK_CTRL_CORE_CLK_GATING_EN_BMSK);
3524 + val = (bgate->core_clk_gate_en <<
3525 + M_CLK_CTRL_MAS_CLK_GATING_EN_SHFT) |
3526 + bgate->port_clk_gate_en;
3527 + writel_relaxed(((reg_val & (~mask)) | (val & mask)), addr);
3528 + /* Ensure clock gating enable mask is set before exiting */
3529 + wmb();
3530 +}
3531 +
3532 +void msm_bus_bimc_arb_en(struct msm_bus_bimc_info *binfo,
3533 + uint32_t slv_index, bool en)
3534 +{
3535 + uint32_t reg_val, reg_mask_val, enable, val;
3536 +
3537 + reg_mask_val = (readl_relaxed(S_ARB_CONFIG_INFO_0_ADDR(binfo->
3538 + base, slv_index)) & S_ARB_CONFIG_INFO_0_FUNC_BMSK)
3539 + >> S_ARB_CONFIG_INFO_0_FUNC_SHFT;
3540 + enable = ENABLE(en);
3541 + val = enable << S_ARB_MODE_PRIO_RR_EN_SHFT;
3542 + if (reg_mask_val == BIMC_ARB_MODE_PRIORITY_RR) {
3543 + reg_val = readl_relaxed(S_ARB_CONFIG_INFO_0_ADDR(binfo->
3544 + base, slv_index)) & S_ARB_MODE_RMSK;
3545 + writel_relaxed(((reg_val & (~(S_ARB_MODE_PRIO_RR_EN_BMSK))) |
3546 + (val & S_ARB_MODE_PRIO_RR_EN_BMSK)),
3547 + S_ARB_MODE_ADDR(binfo->base, slv_index));
3548 + /* Ensure arbitration mode is set before returning */
3549 + wmb();
3550 + }
3551 +}
3552 +
3553 +static void set_qos_mode(void __iomem *baddr, uint32_t index, uint32_t val0,
3554 + uint32_t val1, uint32_t val2)
3555 +{
3556 + uint32_t reg_val, val;
3557 +
3558 + reg_val = readl_relaxed(M_PRIOLVL_OVERRIDE_ADDR(baddr,
3559 + index)) & M_PRIOLVL_OVERRIDE_RMSK;
3560 + val = val0 << M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_SHFT;
3561 + writel_relaxed(((reg_val & ~(M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_BMSK))
3562 + | (val & M_PRIOLVL_OVERRIDE_OVERRIDE_PRIOLVL_BMSK)),
3563 + M_PRIOLVL_OVERRIDE_ADDR(baddr, index));
3564 + reg_val = readl_relaxed(M_RD_CMD_OVERRIDE_ADDR(baddr, index)) &
3565 + M_RD_CMD_OVERRIDE_RMSK;
3566 + val = val1 << M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT;
3567 + writel_relaxed(((reg_val & ~(M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK
3568 + )) | (val & M_RD_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK)),
3569 + M_RD_CMD_OVERRIDE_ADDR(baddr, index));
3570 + reg_val = readl_relaxed(M_WR_CMD_OVERRIDE_ADDR(baddr, index)) &
3571 + M_WR_CMD_OVERRIDE_RMSK;
3572 + val = val2 << M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT;
3573 + writel_relaxed(((reg_val & ~(M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK
3574 + )) | (val & M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK)),
3575 + M_WR_CMD_OVERRIDE_ADDR(baddr, index));
3576 + /* Ensure the priority register writes go through */
3577 + wmb();
3578 +}
3579 +
3580 +static void msm_bus_bimc_set_qos_mode(void __iomem *base,
3581 + uint32_t mas_index, uint8_t qmode_sel)
3582 +{
3583 + uint32_t reg_val, val;
3584 +
3585 + switch (qmode_sel) {
3586 + case BIMC_QOS_MODE_FIXED:
3587 + reg_val = readl_relaxed(M_BKE_EN_ADDR(base,
3588 + mas_index));
3589 + writel_relaxed((reg_val & (~M_BKE_EN_EN_BMSK)),
3590 + M_BKE_EN_ADDR(base, mas_index));
3591 + /* Ensure that the book-keeping register writes
3592 + * go through before setting QoS mode.
3593 + * QoS mode registers might write beyond 1K
3594 + * boundary in future
3595 + */
3596 + wmb();
3597 + set_qos_mode(base, mas_index, 1, 1, 1);
3598 + break;
3599 +
3600 + case BIMC_QOS_MODE_BYPASS:
3601 + reg_val = readl_relaxed(M_BKE_EN_ADDR(base,
3602 + mas_index));
3603 + writel_relaxed((reg_val & (~M_BKE_EN_EN_BMSK)),
3604 + M_BKE_EN_ADDR(base, mas_index));
3605 + /* Ensure that the book-keeping register writes
3606 + * go through before setting QoS mode.
3607 + * QoS mode registers might write beyond 1K
3608 + * boundary in future
3609 + */
3610 + wmb();
3611 + set_qos_mode(base, mas_index, 0, 0, 0);
3612 + break;
3613 +
3614 + case BIMC_QOS_MODE_REGULATOR:
3615 + case BIMC_QOS_MODE_LIMITER:
3616 + set_qos_mode(base, mas_index, 0, 0, 0);
3617 + reg_val = readl_relaxed(M_BKE_EN_ADDR(base,
3618 + mas_index));
3619 + val = 1 << M_BKE_EN_EN_SHFT;
3620 + /* Ensure that the book-keeping register writes
3621 + * go through before setting QoS mode.
3622 + * QoS mode registers might write beyond 1K
3623 + * boundary in future
3624 + */
3625 + wmb();
3626 + writel_relaxed(((reg_val & (~M_BKE_EN_EN_BMSK)) | (val &
3627 + M_BKE_EN_EN_BMSK)), M_BKE_EN_ADDR(base,
3628 + mas_index));
3629 + break;
3630 + default:
3631 + break;
3632 + }
3633 +}
3634 +
3635 +static void set_qos_prio_rl(void __iomem *addr, uint32_t rmsk,
3636 + uint8_t index, struct msm_bus_bimc_qos_mode *qmode)
3637 +{
3638 + uint32_t reg_val, val0, val;
3639 +
3640 + /* Note, addr is already passed with right mas_index */
3641 + reg_val = readl_relaxed(addr) & rmsk;
3642 + val0 = BKE_HEALTH_VAL(qmode->rl.qhealth[index].limit_commands,
3643 + qmode->rl.qhealth[index].areq_prio,
3644 + qmode->rl.qhealth[index].prio_level);
3645 + val = ((reg_val & (~(BKE_HEALTH_MASK))) | (val0 & BKE_HEALTH_MASK));
3646 + writel_relaxed(val, addr);
3647 + /* Ensure that priority for regulator/limiter modes are
3648 + * set before returning
3649 + */
3650 + wmb();
3651 +
3652 +}
3653 +
3654 +static void msm_bus_bimc_set_qos_prio(void __iomem *base,
3655 + uint32_t mas_index, uint8_t qmode_sel,
3656 + struct msm_bus_bimc_qos_mode *qmode)
3657 +{
3658 + uint32_t reg_val, val;
3659 +
3660 + switch (qmode_sel) {
3661 + case BIMC_QOS_MODE_FIXED:
3662 + reg_val = readl_relaxed(M_PRIOLVL_OVERRIDE_ADDR(
3663 + base, mas_index)) & M_PRIOLVL_OVERRIDE_RMSK;
3664 + val = qmode->fixed.prio_level <<
3665 + M_PRIOLVL_OVERRIDE_SHFT;
3666 + writel_relaxed(((reg_val &
3667 + ~(M_PRIOLVL_OVERRIDE_BMSK)) | (val
3668 + & M_PRIOLVL_OVERRIDE_BMSK)),
3669 + M_PRIOLVL_OVERRIDE_ADDR(base, mas_index));
3670 +
3671 + reg_val = readl_relaxed(M_RD_CMD_OVERRIDE_ADDR(
3672 + base, mas_index)) & M_RD_CMD_OVERRIDE_RMSK;
3673 + val = qmode->fixed.areq_prio_rd <<
3674 + M_RD_CMD_OVERRIDE_AREQPRIO_SHFT;
3675 + writel_relaxed(((reg_val & ~(M_RD_CMD_OVERRIDE_AREQPRIO_BMSK))
3676 + | (val & M_RD_CMD_OVERRIDE_AREQPRIO_BMSK)),
3677 + M_RD_CMD_OVERRIDE_ADDR(base, mas_index));
3678 +
3679 + reg_val = readl_relaxed(M_WR_CMD_OVERRIDE_ADDR(
3680 + base, mas_index)) & M_WR_CMD_OVERRIDE_RMSK;
3681 + val = qmode->fixed.areq_prio_wr <<
3682 + M_WR_CMD_OVERRIDE_AREQPRIO_SHFT;
3683 + writel_relaxed(((reg_val & ~(M_WR_CMD_OVERRIDE_AREQPRIO_BMSK))
3684 + | (val & M_WR_CMD_OVERRIDE_AREQPRIO_BMSK)),
3685 + M_WR_CMD_OVERRIDE_ADDR(base, mas_index));
3686 + /* Ensure that fixed mode register writes go through
3687 + * before returning
3688 + */
3689 + wmb();
3690 + break;
3691 +
3692 + case BIMC_QOS_MODE_REGULATOR:
3693 + case BIMC_QOS_MODE_LIMITER:
3694 + set_qos_prio_rl(M_BKE_HEALTH_3_CONFIG_ADDR(base,
3695 + mas_index), M_BKE_HEALTH_3_CONFIG_RMSK, 3, qmode);
3696 + set_qos_prio_rl(M_BKE_HEALTH_2_CONFIG_ADDR(base,
3697 + mas_index), M_BKE_HEALTH_2_CONFIG_RMSK, 2, qmode);
3698 + set_qos_prio_rl(M_BKE_HEALTH_1_CONFIG_ADDR(base,
3699 + mas_index), M_BKE_HEALTH_1_CONFIG_RMSK, 1, qmode);
3700 + set_qos_prio_rl(M_BKE_HEALTH_0_CONFIG_ADDR(base,
3701 + mas_index), M_BKE_HEALTH_0_CONFIG_RMSK, 0 , qmode);
3702 + break;
3703 + case BIMC_QOS_MODE_BYPASS:
3704 + default:
3705 + break;
3706 + }
3707 +}
3708 +
3709 +static void set_qos_bw_regs(void __iomem *baddr, uint32_t mas_index,
3710 + int32_t th, int32_t tm, int32_t tl, uint32_t gp,
3711 + uint32_t gc)
3712 +{
3713 + int32_t reg_val, val;
3714 + int32_t bke_reg_val;
3715 + int16_t val2;
3716 +
3717 + /* Disable BKE before writing to registers as per spec */
3718 + bke_reg_val = readl_relaxed(M_BKE_EN_ADDR(baddr, mas_index));
3719 + writel_relaxed((bke_reg_val & ~(M_BKE_EN_EN_BMSK)),
3720 + M_BKE_EN_ADDR(baddr, mas_index));
3721 +
3722 + /* Write values of registers calculated */
3723 + reg_val = readl_relaxed(M_BKE_GP_ADDR(baddr, mas_index))
3724 + & M_BKE_GP_RMSK;
3725 + val = gp << M_BKE_GP_GP_SHFT;
3726 + writel_relaxed(((reg_val & ~(M_BKE_GP_GP_BMSK)) | (val &
3727 + M_BKE_GP_GP_BMSK)), M_BKE_GP_ADDR(baddr, mas_index));
3728 +
3729 + reg_val = readl_relaxed(M_BKE_GC_ADDR(baddr, mas_index)) &
3730 + M_BKE_GC_RMSK;
3731 + val = gc << M_BKE_GC_GC_SHFT;
3732 + writel_relaxed(((reg_val & ~(M_BKE_GC_GC_BMSK)) | (val &
3733 + M_BKE_GC_GC_BMSK)), M_BKE_GC_ADDR(baddr, mas_index));
3734 +
3735 + reg_val = readl_relaxed(M_BKE_THH_ADDR(baddr, mas_index)) &
3736 + M_BKE_THH_RMSK;
3737 + val = th << M_BKE_THH_THRESH_SHFT;
3738 + writel_relaxed(((reg_val & ~(M_BKE_THH_THRESH_BMSK)) | (val &
3739 + M_BKE_THH_THRESH_BMSK)), M_BKE_THH_ADDR(baddr, mas_index));
3740 +
3741 + reg_val = readl_relaxed(M_BKE_THM_ADDR(baddr, mas_index)) &
3742 + M_BKE_THM_RMSK;
3743 + val2 = tm << M_BKE_THM_THRESH_SHFT;
3744 + writel_relaxed(((reg_val & ~(M_BKE_THM_THRESH_BMSK)) | (val2 &
3745 + M_BKE_THM_THRESH_BMSK)), M_BKE_THM_ADDR(baddr, mas_index));
3746 +
3747 + reg_val = readl_relaxed(M_BKE_THL_ADDR(baddr, mas_index)) &
3748 + M_BKE_THL_RMSK;
3749 + val2 = tl << M_BKE_THL_THRESH_SHFT;
3750 + writel_relaxed(((reg_val & ~(M_BKE_THL_THRESH_BMSK)) |
3751 + (val2 & M_BKE_THL_THRESH_BMSK)), M_BKE_THL_ADDR(baddr,
3752 + mas_index));
3753 +
3754 + /* Ensure that all bandwidth register writes have completed
3755 + * before returning
3756 + */
3757 + wmb();
3758 +}
3759 +
3760 +static void msm_bus_bimc_set_qos_bw(void __iomem *base, uint32_t qos_freq,
3761 + uint32_t mas_index, struct msm_bus_bimc_qos_bw *qbw)
3762 +{
3763 + uint32_t bke_en;
3764 +
3765 + /* Validate QOS Frequency */
3766 + if (qos_freq == 0) {
3767 + MSM_BUS_DBG("Zero frequency\n");
3768 + return;
3769 + }
3770 +
3771 + /* Get enable bit for BKE before programming the period */
3772 + bke_en = (readl_relaxed(M_BKE_EN_ADDR(base, mas_index)) &
3773 + M_BKE_EN_EN_BMSK) >> M_BKE_EN_EN_SHFT;
3774 +
3775 + /* Only calculate if there's a requested bandwidth and window */
3776 + if (qbw->bw && qbw->ws) {
3777 + int64_t th, tm, tl;
3778 + uint32_t gp, gc;
3779 + int64_t gp_nominal, gp_required, gp_calc, data, temp;
3780 + int64_t win = qbw->ws * qos_freq;
3781 + temp = win;
3782 + /*
3783 + * Calculate nominal grant period defined by requested
3784 + * window size.
3785 + * Ceil this value to max grant period.
3786 + */
3787 + bimc_div(&temp, 1000000);
3788 + gp_nominal = min_t(uint64_t, MAX_GRANT_PERIOD, temp);
3789 + /*
3790 + * Calculate max window size, defined by bw request.
3791 + * Units: (KHz, MB/s)
3792 + */
3793 + gp_calc = MAX_GC * qos_freq * 1000;
3794 + gp_required = gp_calc;
3795 + bimc_div(&gp_required, qbw->bw);
3796 +
3797 + /* User min of two grant periods */
3798 + gp = min_t(int64_t, gp_nominal, gp_required);
3799 +
3800 + /* Calculate bandwith in grants and ceil. */
3801 + temp = qbw->bw * gp;
3802 + data = qos_freq * 1000;
3803 + bimc_div(&temp, data);
3804 + gc = min_t(int64_t, MAX_GC, temp);
3805 +
3806 + /* Calculate thresholds */
3807 + th = qbw->bw - qbw->thh;
3808 + tm = qbw->bw - qbw->thm;
3809 + tl = qbw->bw - qbw->thl;
3810 +
3811 + th = th * gp;
3812 + bimc_div(&th, data);
3813 + tm = tm * gp;
3814 + bimc_div(&tm, data);
3815 + tl = tl * gp;
3816 + bimc_div(&tl, data);
3817 +
3818 + MSM_BUS_DBG("BIMC: BW: mas_index: %d, th: %llu tm: %llu\n",
3819 + mas_index, th, tm);
3820 + MSM_BUS_DBG("BIMC: tl: %llu gp:%u gc: %u bke_en: %u\n",
3821 + tl, gp, gc, bke_en);
3822 + set_qos_bw_regs(base, mas_index, th, tm, tl, gp, gc);
3823 + } else
3824 + /* Clear bandwidth registers */
3825 + set_qos_bw_regs(base, mas_index, 0, 0, 0, 0, 0);
3826 +}
3827 +
3828 +static int msm_bus_bimc_allocate_commit_data(struct msm_bus_fabric_registration
3829 + *fab_pdata, void **cdata, int ctx)
3830 +{
3831 + struct msm_bus_bimc_commit **cd = (struct msm_bus_bimc_commit **)cdata;
3832 + struct msm_bus_bimc_info *binfo =
3833 + (struct msm_bus_bimc_info *)fab_pdata->hw_data;
3834 +
3835 + MSM_BUS_DBG("Allocating BIMC commit data\n");
3836 + *cd = kzalloc(sizeof(struct msm_bus_bimc_commit), GFP_KERNEL);
3837 + if (!*cd) {
3838 + MSM_BUS_DBG("Couldn't alloc mem for cdata\n");
3839 + return -ENOMEM;
3840 + }
3841 +
3842 + (*cd)->mas = binfo->cdata[ctx].mas;
3843 + (*cd)->slv = binfo->cdata[ctx].slv;
3844 +
3845 + return 0;
3846 +}
3847 +
3848 +static void *msm_bus_bimc_allocate_bimc_data(struct platform_device *pdev,
3849 + struct msm_bus_fabric_registration *fab_pdata)
3850 +{
3851 + struct resource *bimc_mem;
3852 + struct resource *bimc_io;
3853 + struct msm_bus_bimc_info *binfo;
3854 + int i;
3855 +
3856 + MSM_BUS_DBG("Allocating BIMC data\n");
3857 + binfo = kzalloc(sizeof(struct msm_bus_bimc_info), GFP_KERNEL);
3858 + if (!binfo) {
3859 + WARN(!binfo, "Couldn't alloc mem for bimc_info\n");
3860 + return NULL;
3861 + }
3862 +
3863 + binfo->qos_freq = fab_pdata->qos_freq;
3864 +
3865 + binfo->params.nmasters = fab_pdata->nmasters;
3866 + binfo->params.nslaves = fab_pdata->nslaves;
3867 + binfo->params.bus_id = fab_pdata->id;
3868 +
3869 + for (i = 0; i < NUM_CTX; i++) {
3870 + binfo->cdata[i].mas = kzalloc(sizeof(struct
3871 + msm_bus_node_hw_info) * fab_pdata->nmasters * 2,
3872 + GFP_KERNEL);
3873 + if (!binfo->cdata[i].mas) {
3874 + MSM_BUS_ERR("Couldn't alloc mem for bimc master hw\n");
3875 + kfree(binfo);
3876 + return NULL;
3877 + }
3878 +
3879 + binfo->cdata[i].slv = kzalloc(sizeof(struct
3880 + msm_bus_node_hw_info) * fab_pdata->nslaves * 2,
3881 + GFP_KERNEL);
3882 + if (!binfo->cdata[i].slv) {
3883 + MSM_BUS_DBG("Couldn't alloc mem for bimc slave hw\n");
3884 + kfree(binfo->cdata[i].mas);
3885 + kfree(binfo);
3886 + return NULL;
3887 + }
3888 + }
3889 +
3890 + if (fab_pdata->virt) {
3891 + MSM_BUS_DBG("Don't get memory regions for virtual fabric\n");
3892 + goto skip_mem;
3893 + }
3894 +
3895 + bimc_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3896 + if (!bimc_mem) {
3897 + MSM_BUS_ERR("Cannot get BIMC Base address\n");
3898 + kfree(binfo);
3899 + return NULL;
3900 + }
3901 +
3902 + bimc_io = request_mem_region(bimc_mem->start,
3903 + resource_size(bimc_mem), pdev->name);
3904 + if (!bimc_io) {
3905 + MSM_BUS_ERR("BIMC memory unavailable\n");
3906 + kfree(binfo);
3907 + return NULL;
3908 + }
3909 +
3910 + binfo->base = ioremap(bimc_mem->start, resource_size(bimc_mem));
3911 + if (!binfo->base) {
3912 + MSM_BUS_ERR("IOremap failed for BIMC!\n");
3913 + release_mem_region(bimc_mem->start, resource_size(bimc_mem));
3914 + kfree(binfo);
3915 + return NULL;
3916 + }
3917 +
3918 +skip_mem:
3919 + fab_pdata->hw_data = (void *)binfo;
3920 + return (void *)binfo;
3921 +}
3922 +
3923 +static void free_commit_data(void *cdata)
3924 +{
3925 + struct msm_bus_bimc_commit *cd = (struct msm_bus_bimc_commit *)cdata;
3926 +
3927 + kfree(cd->mas);
3928 + kfree(cd->slv);
3929 + kfree(cd);
3930 +}
3931 +
3932 +static void bke_switch(
3933 + void __iomem *baddr, uint32_t mas_index, bool req, int mode)
3934 +{
3935 + uint32_t reg_val, val, cur_val;
3936 +
3937 + val = req << M_BKE_EN_EN_SHFT;
3938 + reg_val = readl_relaxed(M_BKE_EN_ADDR(baddr, mas_index));
3939 + cur_val = reg_val & M_BKE_EN_RMSK;
3940 + if (val == cur_val)
3941 + return;
3942 +
3943 + if (!req && mode == BIMC_QOS_MODE_FIXED)
3944 + set_qos_mode(baddr, mas_index, 1, 1, 1);
3945 +
3946 + writel_relaxed(((reg_val & ~(M_BKE_EN_EN_BMSK)) | (val &
3947 + M_BKE_EN_EN_BMSK)), M_BKE_EN_ADDR(baddr, mas_index));
3948 + /* Make sure BKE on/off goes through before changing priorities */
3949 + wmb();
3950 +
3951 + if (req)
3952 + set_qos_mode(baddr, mas_index, 0, 0, 0);
3953 +}
3954 +
3955 +static void bimc_set_static_qos_bw(void __iomem *base, unsigned int qos_freq,
3956 + int mport, struct msm_bus_bimc_qos_bw *qbw)
3957 +{
3958 + int32_t bw_mbps, thh = 0, thm, thl, gc;
3959 + int32_t gp;
3960 + u64 temp;
3961 +
3962 + if (qos_freq == 0) {
3963 + MSM_BUS_DBG("No QoS Frequency.\n");
3964 + return;
3965 + }
3966 +
3967 + if (!(qbw->bw && qbw->gp)) {
3968 + MSM_BUS_DBG("No QoS Bandwidth or Window size\n");
3969 + return;
3970 + }
3971 +
3972 + /* Convert bandwidth to MBPS */
3973 + temp = qbw->bw;
3974 + bimc_div(&temp, 1000000);
3975 + bw_mbps = temp;
3976 +
3977 + /* Grant period in clock cycles
3978 + * Grant period from bandwidth structure
3979 + * is in nano seconds, QoS freq is in KHz.
3980 + * Divide by 1000 to get clock cycles.
3981 + */
3982 + gp = (qos_freq * qbw->gp) / (1000 * NSEC_PER_USEC);
3983 +
3984 + /* Grant count = BW in MBps * Grant period
3985 + * in micro seconds
3986 + */
3987 + gc = bw_mbps * (qbw->gp / NSEC_PER_USEC);
3988 + gc = min(gc, MAX_GC);
3989 +
3990 + /* Medium threshold = -((Medium Threshold percentage *
3991 + * Grant count) / 100)
3992 + */
3993 + thm = -((qbw->thmp * gc) / 100);
3994 + qbw->thm = thm;
3995 +
3996 + /* Low threshold = -(Grant count) */
3997 + thl = -gc;
3998 + qbw->thl = thl;
3999 +
4000 + MSM_BUS_DBG("%s: BKE parameters: gp %d, gc %d, thm %d thl %d thh %d",
4001 + __func__, gp, gc, thm, thl, thh);
4002 +
4003 + trace_bus_bke_params(gc, gp, thl, thm, thl);
4004 + set_qos_bw_regs(base, mport, thh, thm, thl, gp, gc);
4005 +}
4006 +
4007 +static void msm_bus_bimc_config_master(
4008 + struct msm_bus_fabric_registration *fab_pdata,
4009 + struct msm_bus_inode_info *info,
4010 + uint64_t req_clk, uint64_t req_bw)
4011 +{
4012 + int mode, i, ports;
4013 + struct msm_bus_bimc_info *binfo;
4014 + uint64_t bw = 0;
4015 +
4016 + binfo = (struct msm_bus_bimc_info *)fab_pdata->hw_data;
4017 + ports = info->node_info->num_mports;
4018 +
4019 + /**
4020 + * Here check the details of dual configuration.
4021 + * Take actions based on different modes.
4022 + * Check for threshold if limiter mode, etc.
4023 + */
4024 +
4025 + if (req_clk <= info->node_info->th[0]) {
4026 + mode = info->node_info->mode;
4027 + bw = info->node_info->bimc_bw[0];
4028 + } else if ((info->node_info->num_thresh > 1) &&
4029 + (req_clk <= info->node_info->th[1])) {
4030 + mode = info->node_info->mode;
4031 + bw = info->node_info->bimc_bw[1];
4032 + } else
4033 + mode = info->node_info->mode_thresh;
4034 +
4035 + switch (mode) {
4036 + case BIMC_QOS_MODE_BYPASS:
4037 + case BIMC_QOS_MODE_FIXED:
4038 + for (i = 0; i < ports; i++)
4039 + bke_switch(binfo->base, info->node_info->qport[i],
4040 + BKE_OFF, mode);
4041 + break;
4042 + case BIMC_QOS_MODE_REGULATOR:
4043 + case BIMC_QOS_MODE_LIMITER:
4044 + for (i = 0; i < ports; i++) {
4045 + /* If not in fixed mode, update bandwidth */
4046 + if ((info->node_info->cur_lim_bw != bw)
4047 + && (mode != BIMC_QOS_MODE_FIXED)) {
4048 + struct msm_bus_bimc_qos_bw qbw;
4049 + qbw.ws = info->node_info->ws;
4050 + qbw.bw = bw;
4051 + qbw.gp = info->node_info->bimc_gp;
4052 + qbw.thmp = info->node_info->bimc_thmp;
4053 + bimc_set_static_qos_bw(binfo->base,
4054 + binfo->qos_freq,
4055 + info->node_info->qport[i], &qbw);
4056 + info->node_info->cur_lim_bw = bw;
4057 + MSM_BUS_DBG("%s: Qos is %d reqclk %llu bw %llu",
4058 + __func__, mode, req_clk, bw);
4059 + }
4060 + bke_switch(binfo->base, info->node_info->qport[i],
4061 + BKE_ON, mode);
4062 + }
4063 + break;
4064 + default:
4065 + break;
4066 + }
4067 +}
4068 +
4069 +static void msm_bus_bimc_update_bw(struct msm_bus_inode_info *hop,
4070 + struct msm_bus_inode_info *info,
4071 + struct msm_bus_fabric_registration *fab_pdata,
4072 + void *sel_cdata, int *master_tiers,
4073 + int64_t add_bw)
4074 +{
4075 + struct msm_bus_bimc_info *binfo;
4076 + struct msm_bus_bimc_qos_bw qbw;
4077 + int i;
4078 + int64_t bw;
4079 + int ports = info->node_info->num_mports;
4080 + struct msm_bus_bimc_commit *sel_cd =