ipq40xx: fix apss cpu overclocking spam
[openwrt/openwrt.git] / target / linux / ipq40xx / patches-4.14 / 900-clk-fix.patch
1 From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
2 From: Christian Lamparter <chunkeey@googlemail.com>
3 Date: Thu, 11 Mar 2018 14:41:31 +0100
4 Subject: [PATCH] clk: fix apss cpu overclocking
5
6 There's an interaction issue between the clk changes:"
7 clk: qcom: ipq4019: Add the apss cpu pll divider clock node
8 clk: qcom: ipq4019: remove fixed clocks and add pll clocks
9 " and the cpufreq-dt.
10
11 cpufreq-dt is now spamming the kernel-log with the following:
12
13 [ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
14 for freq 761142857 (-34)
15
16 This only happens on certain devices like the Compex WPJ428
17 and AVM FritzBox!4040. However, other devices like the Asus
18 RT-AC58U and Meraki MR33 work just fine.
19
20 The issue stem from the fact that all higher CPU-Clocks
21 are achieved by switching the clock-parent to the P_DDRPLLAPSS
22 (ddrpllapss). Which is set by Qualcomm's proprietary bootcode
23 as part of the DDR calibration.
24
25 For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
26 at round 533 MHz (ddrpllsdcc = 190285714 Hz).
27
28 whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
29 clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
30
31 This patch attempts to fix the issue by modifying
32 clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
33 to use a new qcom_find_freq_close() function, which returns the closest
34 matching frequency, instead of the next higher. This way, the SoC in
35 the FB4040 (with its max clock speed of 710.4 MHz) will no longer
36 try to overclock to 761 MHz.
37
38 Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
39 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
40 ---
41 --- a/drivers/clk/qcom/gcc-ipq4019.c
42 +++ b/drivers/clk/qcom/gcc-ipq4019.c
43 @@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fe
44 .reg = 0x2f020,
45 };
46
47 +
48 +const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
49 + unsigned long rate)
50 +{
51 + const struct freq_tbl *last = NULL;
52 +
53 + for ( ; f->freq; f++) {
54 + if (rate == f->freq)
55 + return f;
56 +
57 + if (f->freq > rate) {
58 + if (!last ||
59 + (f->freq - rate) < (rate - last->freq))
60 + return f;
61 + else
62 + return last;
63 + }
64 + last = f;
65 + }
66 +
67 + return last;
68 +}
69 +
70 /*
71 * Round rate function for APSS CPU PLL Clock divider.
72 * It looks up the frequency table and returns the next higher frequency
73 @@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struc
74 struct clk_hw *p_hw;
75 const struct freq_tbl *f;
76
77 - f = qcom_find_freq(pll->freq_tbl, rate);
78 + f = qcom_find_freq_close(pll->freq_tbl, rate);
79 if (!f)
80 return -EINVAL;
81
82 @@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct c
83 u32 mask;
84 int ret;
85
86 - f = qcom_find_freq(pll->freq_tbl, rate);
87 + f = qcom_find_freq_close(pll->freq_tbl, rate);
88 if (!f)
89 return -EINVAL;
90
91 @@ -1315,6 +1338,7 @@ static unsigned long
92 clk_cpu_div_recalc_rate(struct clk_hw *hw,
93 unsigned long parent_rate)
94 {
95 + const struct freq_tbl *f;
96 struct clk_fepll *pll = to_clk_fepll(hw);
97 u32 cdiv, pre_div;
98 u64 rate;
99 @@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
100 rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
101 do_div(rate, pre_div);
102
103 - return rate;
104 + f = qcom_find_freq_close(pll->freq_tbl, rate);
105 + if (!f)
106 + return rate;
107 +
108 + return f->freq;
109 };
110
111 static const struct clk_ops clk_regmap_cpu_div_ops = {