projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ipq40xx: merge all ar40xx patches into one single patch
[openwrt/openwrt.git] / target / linux / ipq40xx / patches-5.4 / 705-net-add-qualcomm-ar40xx-phy.patch
1 Index: linux-5.4.51/drivers/net/phy/Kconfig
2 ===================================================================
3 --- linux-5.4.51.orig/drivers/net/phy/Kconfig
4 +++ linux-5.4.51/drivers/net/phy/Kconfig
5 @@ -587,6 +587,13 @@ config MDIO_IPQ40XX
6 This driver supports the MDIO interface found in Qualcomm
7 Atheros ipq40xx Soc chip.
8
9 +config AR40XX_PHY
10 + tristate "Driver for Qualcomm Atheros IPQ40XX switches"
11 + depends on HAS_IOMEM && OF
12 + select SWCONFIG
13 + ---help---
14 + This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
15 +
16 endif # PHYLIB
17
18 config MICREL_KS8995MA
19 Index: linux-5.4.51/drivers/net/phy/Makefile
20 ===================================================================
21 --- linux-5.4.51.orig/drivers/net/phy/Makefile
22 +++ linux-5.4.51/drivers/net/phy/Makefile
23 @@ -70,6 +70,7 @@ ifdef CONFIG_HWMON
24 aquantia-objs += aquantia_hwmon.o
25 endif
26 obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
27 +obj-$(CONFIG_AR40XX_PHY) += ar40xx.o
28 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
29 obj-$(CONFIG_AT803X_PHY) += at803x.o
30 obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o
31 Index: linux-5.4.51/drivers/net/phy/ar40xx.c
32 ===================================================================
33 --- /dev/null
34 +++ linux-5.4.51/drivers/net/phy/ar40xx.c
35 @@ -0,0 +1,2097 @@
36 +/*
37 + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
38 + *
39 + * Permission to use, copy, modify, and/or distribute this software for
40 + * any purpose with or without fee is hereby granted, provided that the
41 + * above copyright notice and this permission notice appear in all copies.
42 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
43 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
44 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
45 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
46 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
47 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
48 + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
49 + */
50 +
51 +#include <linux/module.h>
52 +#include <linux/list.h>
53 +#include <linux/bitops.h>
54 +#include <linux/switch.h>
55 +#include <linux/delay.h>
56 +#include <linux/phy.h>
57 +#include <linux/clk.h>
58 +#include <linux/reset.h>
59 +#include <linux/lockdep.h>
60 +#include <linux/workqueue.h>
61 +#include <linux/of_device.h>
62 +#include <linux/of_address.h>
63 +#include <linux/mdio.h>
64 +#include <linux/gpio.h>
65 +
66 +#include "ar40xx.h"
67 +
68 +static struct ar40xx_priv *ar40xx_priv;
69 +
70 +#define MIB_DESC(_s , _o, _n) \
71 + { \
72 + .size = (_s), \
73 + .offset = (_o), \
74 + .name = (_n), \
75 + }
76 +
77 +static const struct ar40xx_mib_desc ar40xx_mibs[] = {
78 + MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"),
79 + MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"),
80 + MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"),
81 + MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"),
82 + MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"),
83 + MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"),
84 + MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"),
85 + MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"),
86 + MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"),
87 + MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"),
88 + MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"),
89 + MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"),
90 + MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"),
91 + MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"),
92 + MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"),
93 + MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"),
94 + MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"),
95 + MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"),
96 + MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"),
97 + MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"),
98 + MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"),
99 + MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"),
100 + MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"),
101 + MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"),
102 + MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"),
103 + MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"),
104 + MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"),
105 + MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"),
106 + MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"),
107 + MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"),
108 + MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"),
109 + MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"),
110 + MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"),
111 + MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"),
112 + MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"),
113 + MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"),
114 + MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"),
115 + MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"),
116 + MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"),
117 +};
118 +
119 +static u32
120 +ar40xx_read(struct ar40xx_priv *priv, int reg)
121 +{
122 + return readl(priv->hw_addr + reg);
123 +}
124 +
125 +static u32
126 +ar40xx_psgmii_read(struct ar40xx_priv *priv, int reg)
127 +{
128 + return readl(priv->psgmii_hw_addr + reg);
129 +}
130 +
131 +static void
132 +ar40xx_write(struct ar40xx_priv *priv, int reg, u32 val)
133 +{
134 + writel(val, priv->hw_addr + reg);
135 +}
136 +
137 +static u32
138 +ar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
139 +{
140 + u32 ret;
141 +
142 + ret = ar40xx_read(priv, reg);
143 + ret &= ~mask;
144 + ret |= val;
145 + ar40xx_write(priv, reg, ret);
146 + return ret;
147 +}
148 +
149 +static void
150 +ar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val)
151 +{
152 + writel(val, priv->psgmii_hw_addr + reg);
153 +}
154 +
155 +static void
156 +ar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr,
157 + u16 dbg_addr, u16 dbg_data)
158 +{
159 + struct mii_bus *bus = priv->mii_bus;
160 +
161 + mutex_lock(&bus->mdio_lock);
162 + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
163 + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data);
164 + mutex_unlock(&bus->mdio_lock);
165 +}
166 +
167 +static void
168 +ar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr,
169 + u16 dbg_addr, u16 *dbg_data)
170 +{
171 + struct mii_bus *bus = priv->mii_bus;
172 +
173 + mutex_lock(&bus->mdio_lock);
174 + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
175 + *dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA);
176 + mutex_unlock(&bus->mdio_lock);
177 +}
178 +
179 +static void
180 +ar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id,
181 + u16 mmd_num, u16 reg_id, u16 reg_val)
182 +{
183 + struct mii_bus *bus = priv->mii_bus;
184 +
185 + mutex_lock(&bus->mdio_lock);
186 + bus->write(bus, phy_id,
187 + AR40XX_MII_ATH_MMD_ADDR, mmd_num);
188 + bus->write(bus, phy_id,
189 + AR40XX_MII_ATH_MMD_DATA, reg_id);
190 + bus->write(bus, phy_id,
191 + AR40XX_MII_ATH_MMD_ADDR,
192 + 0x4000 | mmd_num);
193 + bus->write(bus, phy_id,
194 + AR40XX_MII_ATH_MMD_DATA, reg_val);
195 + mutex_unlock(&bus->mdio_lock);
196 +}
197 +
198 +static u16
199 +ar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id,
200 + u16 mmd_num, u16 reg_id)
201 +{
202 + u16 value;
203 + struct mii_bus *bus = priv->mii_bus;
204 +
205 + mutex_lock(&bus->mdio_lock);
206 + bus->write(bus, phy_id,
207 + AR40XX_MII_ATH_MMD_ADDR, mmd_num);
208 + bus->write(bus, phy_id,
209 + AR40XX_MII_ATH_MMD_DATA, reg_id);
210 + bus->write(bus, phy_id,
211 + AR40XX_MII_ATH_MMD_ADDR,
212 + 0x4000 | mmd_num);
213 + value = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA);
214 + mutex_unlock(&bus->mdio_lock);
215 + return value;
216 +}
217 +
218 +/* Start of swconfig support */
219 +
220 +static void
221 +ar40xx_phy_poll_reset(struct ar40xx_priv *priv)
222 +{
223 + u32 i, in_reset, retries = 500;
224 + struct mii_bus *bus = priv->mii_bus;
225 +
226 + /* Assume RESET was recently issued to some or all of the phys */
227 + in_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0);
228 +
229 + while (retries--) {
230 + /* 1ms should be plenty of time.
231 + * 802.3 spec allows for a max wait time of 500ms
232 + */
233 + usleep_range(1000, 2000);
234 +
235 + for (i = 0; i < AR40XX_NUM_PHYS; i++) {
236 + int val;
237 +
238 + /* skip devices which have completed reset */
239 + if (!(in_reset & BIT(i)))
240 + continue;
241 +
242 + val = mdiobus_read(bus, i, MII_BMCR);
243 + if (val < 0)
244 + continue;
245 +
246 + /* mark when phy is no longer in reset state */
247 + if (!(val & BMCR_RESET))
248 + in_reset &= ~BIT(i);
249 + }
250 +
251 + if (!in_reset)
252 + return;
253 + }
254 +
255 + dev_warn(&bus->dev, "Failed to reset all phys! (in_reset: 0x%x)\n",
256 + in_reset);
257 +}
258 +
259 +static void
260 +ar40xx_phy_init(struct ar40xx_priv *priv)
261 +{
262 + int i;
263 + struct mii_bus *bus;
264 + u16 val;
265 +
266 + bus = priv->mii_bus;
267 + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
268 + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
269 + val &= ~AR40XX_PHY_MANU_CTRL_EN;
270 + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
271 + mdiobus_write(bus, i,
272 + MII_ADVERTISE, ADVERTISE_ALL |
273 + ADVERTISE_PAUSE_CAP |
274 + ADVERTISE_PAUSE_ASYM);
275 + mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
276 + mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
277 + }
278 +
279 + ar40xx_phy_poll_reset(priv);
280 +}
281 +
282 +static void
283 +ar40xx_port_phy_linkdown(struct ar40xx_priv *priv)
284 +{
285 + struct mii_bus *bus;
286 + int i;
287 + u16 val;
288 +
289 + bus = priv->mii_bus;
290 + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
291 + mdiobus_write(bus, i, MII_CTRL1000, 0);
292 + mdiobus_write(bus, i, MII_ADVERTISE, 0);
293 + mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
294 + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
295 + val |= AR40XX_PHY_MANU_CTRL_EN;
296 + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
297 + /* disable transmit */
298 + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val);
299 + val &= 0xf00f;
300 + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val);
301 + }
302 +}
303 +
304 +static void
305 +ar40xx_set_mirror_regs(struct ar40xx_priv *priv)
306 +{
307 + int port;
308 +
309 + /* reset all mirror registers */
310 + ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
311 + AR40XX_FWD_CTRL0_MIRROR_PORT,
312 + (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
313 + for (port = 0; port < AR40XX_NUM_PORTS; port++) {
314 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port),
315 + AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0);
316 +
317 + ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port),
318 + AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0);
319 + }
320 +
321 + /* now enable mirroring if necessary */
322 + if (priv->source_port >= AR40XX_NUM_PORTS ||
323 + priv->monitor_port >= AR40XX_NUM_PORTS ||
324 + priv->source_port == priv->monitor_port) {
325 + return;
326 + }
327 +
328 + ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
329 + AR40XX_FWD_CTRL0_MIRROR_PORT,
330 + (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
331 +
332 + if (priv->mirror_rx)
333 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0,
334 + AR40XX_PORT_LOOKUP_ING_MIRROR_EN);
335 +
336 + if (priv->mirror_tx)
337 + ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port),
338 + 0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN);
339 +}
340 +
341 +static int
342 +ar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
343 +{
344 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
345 + u8 ports = priv->vlan_table[val->port_vlan];
346 + int i;
347 +
348 + val->len = 0;
349 + for (i = 0; i < dev->ports; i++) {
350 + struct switch_port *p;
351 +
352 + if (!(ports & BIT(i)))
353 + continue;
354 +
355 + p = &val->value.ports[val->len++];
356 + p->id = i;
357 + if ((priv->vlan_tagged & BIT(i)) ||
358 + (priv->pvid[i] != val->port_vlan))
359 + p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
360 + else
361 + p->flags = 0;
362 + }
363 + return 0;
364 +}
365 +
366 +static int
367 +ar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
368 +{
369 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
370 + u8 *vt = &priv->vlan_table[val->port_vlan];
371 + int i;
372 +
373 + *vt = 0;
374 + for (i = 0; i < val->len; i++) {
375 + struct switch_port *p = &val->value.ports[i];
376 +
377 + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
378 + if (val->port_vlan == priv->pvid[p->id])
379 + priv->vlan_tagged |= BIT(p->id);
380 + } else {
381 + priv->vlan_tagged &= ~BIT(p->id);
382 + priv->pvid[p->id] = val->port_vlan;
383 + }
384 +
385 + *vt |= BIT(p->id);
386 + }
387 + return 0;
388 +}
389 +
390 +static int
391 +ar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val,
392 + unsigned timeout)
393 +{
394 + int i;
395 +
396 + for (i = 0; i < timeout; i++) {
397 + u32 t;
398 +
399 + t = ar40xx_read(priv, reg);
400 + if ((t & mask) == val)
401 + return 0;
402 +
403 + usleep_range(1000, 2000);
404 + }
405 +
406 + return -ETIMEDOUT;
407 +}
408 +
409 +static int
410 +ar40xx_mib_op(struct ar40xx_priv *priv, u32 op)
411 +{
412 + int ret;
413 +
414 + lockdep_assert_held(&priv->mib_lock);
415 +
416 + /* Capture the hardware statistics for all ports */
417 + ar40xx_rmw(priv, AR40XX_REG_MIB_FUNC,
418 + AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S));
419 +
420 + /* Wait for the capturing to complete. */
421 + ret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC,
422 + AR40XX_MIB_BUSY, 0, 10);
423 +
424 + return ret;
425 +}
426 +
427 +static void
428 +ar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush)
429 +{
430 + unsigned int base;
431 + u64 *mib_stats;
432 + int i;
433 + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
434 +
435 + WARN_ON(port >= priv->dev.ports);
436 +
437 + lockdep_assert_held(&priv->mib_lock);
438 +
439 + base = AR40XX_REG_PORT_STATS_START +
440 + AR40XX_REG_PORT_STATS_LEN * port;
441 +
442 + mib_stats = &priv->mib_stats[port * num_mibs];
443 + if (flush) {
444 + u32 len;
445 +
446 + len = num_mibs * sizeof(*mib_stats);
447 + memset(mib_stats, 0, len);
448 + return;
449 + }
450 + for (i = 0; i < num_mibs; i++) {
451 + const struct ar40xx_mib_desc *mib;
452 + u64 t;
453 +
454 + mib = &ar40xx_mibs[i];
455 + t = ar40xx_read(priv, base + mib->offset);
456 + if (mib->size == 2) {
457 + u64 hi;
458 +
459 + hi = ar40xx_read(priv, base + mib->offset + 4);
460 + t |= hi << 32;
461 + }
462 +
463 + mib_stats[i] += t;
464 + }
465 +}
466 +
467 +static int
468 +ar40xx_mib_capture(struct ar40xx_priv *priv)
469 +{
470 + return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE);
471 +}
472 +
473 +static int
474 +ar40xx_mib_flush(struct ar40xx_priv *priv)
475 +{
476 + return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH);
477 +}
478 +
479 +static int
480 +ar40xx_sw_set_reset_mibs(struct switch_dev *dev,
481 + const struct switch_attr *attr,
482 + struct switch_val *val)
483 +{
484 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
485 + unsigned int len;
486 + int ret;
487 + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
488 +
489 + mutex_lock(&priv->mib_lock);
490 +
491 + len = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats);
492 + memset(priv->mib_stats, 0, len);
493 + ret = ar40xx_mib_flush(priv);
494 +
495 + mutex_unlock(&priv->mib_lock);
496 + return ret;
497 +}
498 +
499 +static int
500 +ar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
501 + struct switch_val *val)
502 +{
503 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
504 +
505 + priv->vlan = !!val->value.i;
506 + return 0;
507 +}
508 +
509 +static int
510 +ar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
511 + struct switch_val *val)
512 +{
513 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
514 +
515 + val->value.i = priv->vlan;
516 + return 0;
517 +}
518 +
519 +static int
520 +ar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev,
521 + const struct switch_attr *attr,
522 + struct switch_val *val)
523 +{
524 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
525 +
526 + mutex_lock(&priv->reg_mutex);
527 + priv->mirror_rx = !!val->value.i;
528 + ar40xx_set_mirror_regs(priv);
529 + mutex_unlock(&priv->reg_mutex);
530 +
531 + return 0;
532 +}
533 +
534 +static int
535 +ar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev,
536 + const struct switch_attr *attr,
537 + struct switch_val *val)
538 +{
539 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
540 +
541 + mutex_lock(&priv->reg_mutex);
542 + val->value.i = priv->mirror_rx;
543 + mutex_unlock(&priv->reg_mutex);
544 + return 0;
545 +}
546 +
547 +static int
548 +ar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev,
549 + const struct switch_attr *attr,
550 + struct switch_val *val)
551 +{
552 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
553 +
554 + mutex_lock(&priv->reg_mutex);
555 + priv->mirror_tx = !!val->value.i;
556 + ar40xx_set_mirror_regs(priv);
557 + mutex_unlock(&priv->reg_mutex);
558 +
559 + return 0;
560 +}
561 +
562 +static int
563 +ar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev,
564 + const struct switch_attr *attr,
565 + struct switch_val *val)
566 +{
567 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
568 +
569 + mutex_lock(&priv->reg_mutex);
570 + val->value.i = priv->mirror_tx;
571 + mutex_unlock(&priv->reg_mutex);
572 + return 0;
573 +}
574 +
575 +static int
576 +ar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev,
577 + const struct switch_attr *attr,
578 + struct switch_val *val)
579 +{
580 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
581 +
582 + mutex_lock(&priv->reg_mutex);
583 + priv->monitor_port = val->value.i;
584 + ar40xx_set_mirror_regs(priv);
585 + mutex_unlock(&priv->reg_mutex);
586 +
587 + return 0;
588 +}
589 +
590 +static int
591 +ar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev,
592 + const struct switch_attr *attr,
593 + struct switch_val *val)
594 +{
595 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
596 +
597 + mutex_lock(&priv->reg_mutex);
598 + val->value.i = priv->monitor_port;
599 + mutex_unlock(&priv->reg_mutex);
600 + return 0;
601 +}
602 +
603 +static int
604 +ar40xx_sw_set_mirror_source_port(struct switch_dev *dev,
605 + const struct switch_attr *attr,
606 + struct switch_val *val)
607 +{
608 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
609 +
610 + mutex_lock(&priv->reg_mutex);
611 + priv->source_port = val->value.i;
612 + ar40xx_set_mirror_regs(priv);
613 + mutex_unlock(&priv->reg_mutex);
614 +
615 + return 0;
616 +}
617 +
618 +static int
619 +ar40xx_sw_get_mirror_source_port(struct switch_dev *dev,
620 + const struct switch_attr *attr,
621 + struct switch_val *val)
622 +{
623 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
624 +
625 + mutex_lock(&priv->reg_mutex);
626 + val->value.i = priv->source_port;
627 + mutex_unlock(&priv->reg_mutex);
628 + return 0;
629 +}
630 +
631 +static int
632 +ar40xx_sw_set_linkdown(struct switch_dev *dev,
633 + const struct switch_attr *attr,
634 + struct switch_val *val)
635 +{
636 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
637 +
638 + if (val->value.i == 1)
639 + ar40xx_port_phy_linkdown(priv);
640 + else
641 + ar40xx_phy_init(priv);
642 +
643 + return 0;
644 +}
645 +
646 +static int
647 +ar40xx_sw_set_port_reset_mib(struct switch_dev *dev,
648 + const struct switch_attr *attr,
649 + struct switch_val *val)
650 +{
651 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
652 + int port;
653 + int ret;
654 +
655 + port = val->port_vlan;
656 + if (port >= dev->ports)
657 + return -EINVAL;
658 +
659 + mutex_lock(&priv->mib_lock);
660 + ret = ar40xx_mib_capture(priv);
661 + if (ret)
662 + goto unlock;
663 +
664 + ar40xx_mib_fetch_port_stat(priv, port, true);
665 +
666 +unlock:
667 + mutex_unlock(&priv->mib_lock);
668 + return ret;
669 +}
670 +
671 +static int
672 +ar40xx_sw_get_port_mib(struct switch_dev *dev,
673 + const struct switch_attr *attr,
674 + struct switch_val *val)
675 +{
676 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
677 + u64 *mib_stats;
678 + int port;
679 + int ret;
680 + char *buf = priv->buf;
681 + int i, len = 0;
682 + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
683 +
684 + port = val->port_vlan;
685 + if (port >= dev->ports)
686 + return -EINVAL;
687 +
688 + mutex_lock(&priv->mib_lock);
689 + ret = ar40xx_mib_capture(priv);
690 + if (ret)
691 + goto unlock;
692 +
693 + ar40xx_mib_fetch_port_stat(priv, port, false);
694 +
695 + len += snprintf(buf + len, sizeof(priv->buf) - len,
696 + "Port %d MIB counters\n",
697 + port);
698 +
699 + mib_stats = &priv->mib_stats[port * num_mibs];
700 + for (i = 0; i < num_mibs; i++)
701 + len += snprintf(buf + len, sizeof(priv->buf) - len,
702 + "%-12s: %llu\n",
703 + ar40xx_mibs[i].name,
704 + mib_stats[i]);
705 +
706 + val->value.s = buf;
707 + val->len = len;
708 +
709 +unlock:
710 + mutex_unlock(&priv->mib_lock);
711 + return ret;
712 +}
713 +
714 +static int
715 +ar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
716 + struct switch_val *val)
717 +{
718 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
719 +
720 + priv->vlan_id[val->port_vlan] = val->value.i;
721 + return 0;
722 +}
723 +
724 +static int
725 +ar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
726 + struct switch_val *val)
727 +{
728 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
729 +
730 + val->value.i = priv->vlan_id[val->port_vlan];
731 + return 0;
732 +}
733 +
734 +static int
735 +ar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
736 +{
737 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
738 + *vlan = priv->pvid[port];
739 + return 0;
740 +}
741 +
742 +static int
743 +ar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
744 +{
745 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
746 +
747 + /* make sure no invalid PVIDs get set */
748 + if (vlan >= dev->vlans)
749 + return -EINVAL;
750 +
751 + priv->pvid[port] = vlan;
752 + return 0;
753 +}
754 +
755 +static void
756 +ar40xx_read_port_link(struct ar40xx_priv *priv, int port,
757 + struct switch_port_link *link)
758 +{
759 + u32 status;
760 + u32 speed;
761 +
762 + memset(link, 0, sizeof(*link));
763 +
764 + status = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port));
765 +
766 + link->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN);
767 + if (link->aneg || (port != AR40XX_PORT_CPU))
768 + link->link = !!(status & AR40XX_PORT_STATUS_LINK_UP);
769 + else
770 + link->link = true;
771 +
772 + if (!link->link)
773 + return;
774 +
775 + link->duplex = !!(status & AR40XX_PORT_DUPLEX);
776 + link->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW);
777 + link->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW);
778 +
779 + speed = (status & AR40XX_PORT_SPEED) >>
780 + AR40XX_PORT_STATUS_SPEED_S;
781 +
782 + switch (speed) {
783 + case AR40XX_PORT_SPEED_10M:
784 + link->speed = SWITCH_PORT_SPEED_10;
785 + break;
786 + case AR40XX_PORT_SPEED_100M:
787 + link->speed = SWITCH_PORT_SPEED_100;
788 + break;
789 + case AR40XX_PORT_SPEED_1000M:
790 + link->speed = SWITCH_PORT_SPEED_1000;
791 + break;
792 + default:
793 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
794 + break;
795 + }
796 +}
797 +
798 +static int
799 +ar40xx_sw_get_port_link(struct switch_dev *dev, int port,
800 + struct switch_port_link *link)
801 +{
802 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
803 +
804 + ar40xx_read_port_link(priv, port, link);
805 + return 0;
806 +}
807 +
808 +static const struct switch_attr ar40xx_sw_attr_globals[] = {
809 + {
810 + .type = SWITCH_TYPE_INT,
811 + .name = "enable_vlan",
812 + .description = "Enable VLAN mode",
813 + .set = ar40xx_sw_set_vlan,
814 + .get = ar40xx_sw_get_vlan,
815 + .max = 1
816 + },
817 + {
818 + .type = SWITCH_TYPE_NOVAL,
819 + .name = "reset_mibs",
820 + .description = "Reset all MIB counters",
821 + .set = ar40xx_sw_set_reset_mibs,
822 + },
823 + {
824 + .type = SWITCH_TYPE_INT,
825 + .name = "enable_mirror_rx",
826 + .description = "Enable mirroring of RX packets",
827 + .set = ar40xx_sw_set_mirror_rx_enable,
828 + .get = ar40xx_sw_get_mirror_rx_enable,
829 + .max = 1
830 + },
831 + {
832 + .type = SWITCH_TYPE_INT,
833 + .name = "enable_mirror_tx",
834 + .description = "Enable mirroring of TX packets",
835 + .set = ar40xx_sw_set_mirror_tx_enable,
836 + .get = ar40xx_sw_get_mirror_tx_enable,
837 + .max = 1
838 + },
839 + {
840 + .type = SWITCH_TYPE_INT,
841 + .name = "mirror_monitor_port",
842 + .description = "Mirror monitor port",
843 + .set = ar40xx_sw_set_mirror_monitor_port,
844 + .get = ar40xx_sw_get_mirror_monitor_port,
845 + .max = AR40XX_NUM_PORTS - 1
846 + },
847 + {
848 + .type = SWITCH_TYPE_INT,
849 + .name = "mirror_source_port",
850 + .description = "Mirror source port",
851 + .set = ar40xx_sw_set_mirror_source_port,
852 + .get = ar40xx_sw_get_mirror_source_port,
853 + .max = AR40XX_NUM_PORTS - 1
854 + },
855 + {
856 + .type = SWITCH_TYPE_INT,
857 + .name = "linkdown",
858 + .description = "Link down all the PHYs",
859 + .set = ar40xx_sw_set_linkdown,
860 + .max = 1
861 + },
862 +};
863 +
864 +static const struct switch_attr ar40xx_sw_attr_port[] = {
865 + {
866 + .type = SWITCH_TYPE_NOVAL,
867 + .name = "reset_mib",
868 + .description = "Reset single port MIB counters",
869 + .set = ar40xx_sw_set_port_reset_mib,
870 + },
871 + {
872 + .type = SWITCH_TYPE_STRING,
873 + .name = "mib",
874 + .description = "Get port's MIB counters",
875 + .set = NULL,
876 + .get = ar40xx_sw_get_port_mib,
877 + },
878 +};
879 +
880 +const struct switch_attr ar40xx_sw_attr_vlan[] = {
881 + {
882 + .type = SWITCH_TYPE_INT,
883 + .name = "vid",
884 + .description = "VLAN ID (0-4094)",
885 + .set = ar40xx_sw_set_vid,
886 + .get = ar40xx_sw_get_vid,
887 + .max = 4094,
888 + },
889 +};
890 +
891 +/* End of swconfig support */
892 +
893 +static int
894 +ar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
895 +{
896 + int timeout = 20;
897 + u32 t;
898 +
899 + while (1) {
900 + t = ar40xx_read(priv, reg);
901 + if ((t & mask) == val)
902 + return 0;
903 +
904 + if (timeout-- <= 0)
905 + break;
906 +
907 + usleep_range(10, 20);
908 + }
909 +
910 + pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n",
911 + (unsigned int)reg, t, mask, val);
912 + return -ETIMEDOUT;
913 +}
914 +
915 +static int
916 +ar40xx_atu_flush(struct ar40xx_priv *priv)
917 +{
918 + int ret;
919 +
920 + ret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC,
921 + AR40XX_ATU_FUNC_BUSY, 0);
922 + if (!ret)
923 + ar40xx_write(priv, AR40XX_REG_ATU_FUNC,
924 + AR40XX_ATU_FUNC_OP_FLUSH |
925 + AR40XX_ATU_FUNC_BUSY);
926 +
927 + return ret;
928 +}
929 +
930 +static void
931 +ar40xx_ess_reset(struct ar40xx_priv *priv)
932 +{
933 + reset_control_assert(priv->ess_rst);
934 + mdelay(10);
935 + reset_control_deassert(priv->ess_rst);
936 + /* Waiting for all inner tables init done.
937 + * It cost 5~10ms.
938 + */
939 + mdelay(10);
940 +
941 + pr_info("ESS reset ok!\n");
942 +}
943 +
944 +/* Start of psgmii self test */
945 +
946 +static void
947 +ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv)
948 +{
949 + u32 n;
950 + struct mii_bus *bus = priv->mii_bus;
951 + /* reset phy psgmii */
952 + /* fix phy psgmii RX 20bit */
953 + mdiobus_write(bus, 5, 0x0, 0x005b);
954 + /* reset phy psgmii */
955 + mdiobus_write(bus, 5, 0x0, 0x001b);
956 + /* release reset phy psgmii */
957 + mdiobus_write(bus, 5, 0x0, 0x005b);
958 +
959 + for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
960 + u16 status;
961 +
962 + status = ar40xx_phy_mmd_read(priv, 5, 1, 0x28);
963 + if (status & BIT(0))
964 + break;
965 + /* Polling interval to check PSGMII PLL in malibu is ready
966 + * the worst time is 8.67ms
967 + * for 25MHz reference clock
968 + * [512+(128+2048)*49]*80ns+100us
969 + */
970 + mdelay(2);
971 + }
972 +
973 + /*check malibu psgmii calibration done end..*/
974 +
975 + /*freeze phy psgmii RX CDR*/
976 + mdiobus_write(bus, 5, 0x1a, 0x2230);
977 +
978 + ar40xx_ess_reset(priv);
979 +
980 + /*check psgmii calibration done start*/
981 + for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
982 + u32 status;
983 +
984 + status = ar40xx_psgmii_read(priv, 0xa0);
985 + if (status & BIT(0))
986 + break;
987 + /* Polling interval to check PSGMII PLL in ESS is ready */
988 + mdelay(2);
989 + }
990 +
991 + /* check dakota psgmii calibration done end..*/
992 +
993 + /* relesae phy psgmii RX CDR */
994 + mdiobus_write(bus, 5, 0x1a, 0x3230);
995 + /* release phy psgmii RX 20bit */
996 + mdiobus_write(bus, 5, 0x0, 0x005f);
997 +}
998 +
999 +static void
1000 +ar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy)
1001 +{
1002 + int j;
1003 + u32 tx_ok, tx_error;
1004 + u32 rx_ok, rx_error;
1005 + u32 tx_ok_high16;
1006 + u32 rx_ok_high16;
1007 + u32 tx_all_ok, rx_all_ok;
1008 + struct mii_bus *bus = priv->mii_bus;
1009 +
1010 + mdiobus_write(bus, phy, 0x0, 0x9000);
1011 + mdiobus_write(bus, phy, 0x0, 0x4140);
1012 +
1013 + for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
1014 + u16 status;
1015 +
1016 + status = mdiobus_read(bus, phy, 0x11);
1017 + if (status & AR40XX_PHY_SPEC_STATUS_LINK)
1018 + break;
1019 + /* the polling interval to check if the PHY link up or not
1020 + * maxwait_timer: 750 ms +/-10 ms
1021 + * minwait_timer : 1 us +/- 0.1us
1022 + * time resides in minwait_timer ~ maxwait_timer
1023 + * see IEEE 802.3 section 40.4.5.2
1024 + */
1025 + mdelay(8);
1026 + }
1027 +
1028 + /* enable check */
1029 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000);
1030 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003);
1031 +
1032 + /* start traffic */
1033 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000);
1034 + /* wait for all traffic end
1035 + * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
1036 + */
1037 + mdelay(50);
1038 +
1039 + /* check counter */
1040 + tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
1041 + tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
1042 + tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
1043 + rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
1044 + rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
1045 + rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
1046 + tx_all_ok = tx_ok + (tx_ok_high16 << 16);
1047 + rx_all_ok = rx_ok + (rx_ok_high16 << 16);
1048 + if (tx_all_ok == 0x1000 && tx_error == 0) {
1049 + /* success */
1050 + priv->phy_t_status &= (~BIT(phy));
1051 + } else {
1052 + pr_info("PHY %d single test PSGMII issue happen!\n", phy);
1053 + priv->phy_t_status |= BIT(phy);
1054 + }
1055 +
1056 + mdiobus_write(bus, phy, 0x0, 0x1840);
1057 +}
1058 +
1059 +static void
1060 +ar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv)
1061 +{
1062 + int phy, j;
1063 + struct mii_bus *bus = priv->mii_bus;
1064 +
1065 + mdiobus_write(bus, 0x1f, 0x0, 0x9000);
1066 + mdiobus_write(bus, 0x1f, 0x0, 0x4140);
1067 +
1068 + for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
1069 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1070 + u16 status;
1071 +
1072 + status = mdiobus_read(bus, phy, 0x11);
1073 + if (!(status & BIT(10)))
1074 + break;
1075 + }
1076 +
1077 + if (phy >= (AR40XX_NUM_PORTS - 1))
1078 + break;
1079 + /* The polling interva to check if the PHY link up or not */
1080 + mdelay(8);
1081 + }
1082 + /* enable check */
1083 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000);
1084 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003);
1085 +
1086 + /* start traffic */
1087 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000);
1088 + /* wait for all traffic end
1089 + * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
1090 + */
1091 + mdelay(50);
1092 +
1093 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1094 + u32 tx_ok, tx_error;
1095 + u32 rx_ok, rx_error;
1096 + u32 tx_ok_high16;
1097 + u32 rx_ok_high16;
1098 + u32 tx_all_ok, rx_all_ok;
1099 +
1100 + /* check counter */
1101 + tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
1102 + tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
1103 + tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
1104 + rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
1105 + rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
1106 + rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
1107 + tx_all_ok = tx_ok + (tx_ok_high16<<16);
1108 + rx_all_ok = rx_ok + (rx_ok_high16<<16);
1109 + if (tx_all_ok == 0x1000 && tx_error == 0) {
1110 + /* success */
1111 + priv->phy_t_status &= ~BIT(phy + 8);
1112 + } else {
1113 + pr_info("PHY%d test see issue!\n", phy);
1114 + priv->phy_t_status |= BIT(phy + 8);
1115 + }
1116 + }
1117 +
1118 + pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status);
1119 +}
1120 +
1121 +void
1122 +ar40xx_psgmii_self_test(struct ar40xx_priv *priv)
1123 +{
1124 + u32 i, phy;
1125 + struct mii_bus *bus = priv->mii_bus;
1126 +
1127 + ar40xx_malibu_psgmii_ess_reset(priv);
1128 +
1129 + /* switch to access MII reg for copper */
1130 + mdiobus_write(bus, 4, 0x1f, 0x8500);
1131 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1132 + /*enable phy mdio broadcast write*/
1133 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f);
1134 + }
1135 + /* force no link by power down */
1136 + mdiobus_write(bus, 0x1f, 0x0, 0x1840);
1137 + /*packet number*/
1138 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000);
1139 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0);
1140 +
1141 + /*fix mdi status */
1142 + mdiobus_write(bus, 0x1f, 0x10, 0x6800);
1143 + for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
1144 + priv->phy_t_status = 0;
1145 +
1146 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1147 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
1148 + AR40XX_PORT_LOOKUP_LOOPBACK,
1149 + AR40XX_PORT_LOOKUP_LOOPBACK);
1150 + }
1151 +
1152 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)
1153 + ar40xx_psgmii_single_phy_testing(priv, phy);
1154 +
1155 + ar40xx_psgmii_all_phy_testing(priv);
1156 +
1157 + if (priv->phy_t_status)
1158 + ar40xx_malibu_psgmii_ess_reset(priv);
1159 + else
1160 + break;
1161 + }
1162 +
1163 + if (i >= AR40XX_PSGMII_CALB_NUM)
1164 + pr_info("PSGMII cannot recover\n");
1165 + else
1166 + pr_debug("PSGMII recovered after %d times reset\n", i);
1167 +
1168 + /* configuration recover */
1169 + /* packet number */
1170 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0);
1171 + /* disable check */
1172 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0);
1173 + /* disable traffic */
1174 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0);
1175 +}
1176 +
1177 +void
1178 +ar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv)
1179 +{
1180 + int phy;
1181 + struct mii_bus *bus = priv->mii_bus;
1182 +
1183 + /* disable phy internal loopback */
1184 + mdiobus_write(bus, 0x1f, 0x10, 0x6860);
1185 + mdiobus_write(bus, 0x1f, 0x0, 0x9040);
1186 +
1187 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1188 + /* disable mac loop back */
1189 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
1190 + AR40XX_PORT_LOOKUP_LOOPBACK, 0);
1191 + /* disable phy mdio broadcast write */
1192 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f);
1193 + }
1194 +
1195 + /* clear fdb entry */
1196 + ar40xx_atu_flush(priv);
1197 +}
1198 +
1199 +/* End of psgmii self test */
1200 +
1201 +static void
1202 +ar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode)
1203 +{
1204 + if (mode == PORT_WRAPPER_PSGMII) {
1205 + ar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200);
1206 + ar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380);
1207 + }
1208 +}
1209 +
1210 +static
1211 +int ar40xx_cpuport_setup(struct ar40xx_priv *priv)
1212 +{
1213 + u32 t;
1214 +
1215 + t = AR40XX_PORT_STATUS_TXFLOW |
1216 + AR40XX_PORT_STATUS_RXFLOW |
1217 + AR40XX_PORT_TXHALF_FLOW |
1218 + AR40XX_PORT_DUPLEX |
1219 + AR40XX_PORT_SPEED_1000M;
1220 + ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
1221 + usleep_range(10, 20);
1222 +
1223 + t |= AR40XX_PORT_TX_EN |
1224 + AR40XX_PORT_RX_EN;
1225 + ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
1226 +
1227 + return 0;
1228 +}
1229 +
1230 +static void
1231 +ar40xx_init_port(struct ar40xx_priv *priv, int port)
1232 +{
1233 + u32 t;
1234 +
1235 + ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port),
1236 + AR40XX_PORT_AUTO_LINK_EN, 0);
1237 +
1238 + ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
1239 +
1240 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
1241 +
1242 + t = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S;
1243 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
1244 +
1245 + t = AR40XX_PORT_LOOKUP_LEARN;
1246 + t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
1247 + ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
1248 +}
1249 +
1250 +void
1251 +ar40xx_init_globals(struct ar40xx_priv *priv)
1252 +{
1253 + u32 t;
1254 +
1255 + /* enable CPU port and disable mirror port */
1256 + t = AR40XX_FWD_CTRL0_CPU_PORT_EN |
1257 + AR40XX_FWD_CTRL0_MIRROR_PORT;
1258 + ar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t);
1259 +
1260 + /* forward multicast and broadcast frames to CPU */
1261 + t = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) |
1262 + (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) |
1263 + (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S);
1264 + ar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t);
1265 +
1266 + /* enable jumbo frames */
1267 + ar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE,
1268 + AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1269 +
1270 + /* Enable MIB counters */
1271 + ar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0,
1272 + AR40XX_MODULE_EN_MIB);
1273 +
1274 + /* Disable AZ */
1275 + ar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0);
1276 +
1277 + /* set flowctrl thershold for cpu port */
1278 + t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
1279 + AR40XX_PORT0_FC_THRESH_OFF_DFLT;
1280 + ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
1281 +}
1282 +
1283 +static void
1284 +ar40xx_malibu_init(struct ar40xx_priv *priv)
1285 +{
1286 + int i;
1287 + struct mii_bus *bus;
1288 + u16 val;
1289 +
1290 + bus = priv->mii_bus;
1291 +
1292 + /* war to enable AZ transmitting ability */
1293 + ar40xx_phy_mmd_write(priv, AR40XX_PSGMII_ID, 1,
1294 + AR40XX_MALIBU_PSGMII_MODE_CTRL,
1295 + AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL);
1296 + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
1297 + /* change malibu control_dac */
1298 + val = ar40xx_phy_mmd_read(priv, i, 7,
1299 + AR40XX_MALIBU_PHY_MMD7_DAC_CTRL);
1300 + val &= ~AR40XX_MALIBU_DAC_CTRL_MASK;
1301 + val |= AR40XX_MALIBU_DAC_CTRL_VALUE;
1302 + ar40xx_phy_mmd_write(priv, i, 7,
1303 + AR40XX_MALIBU_PHY_MMD7_DAC_CTRL, val);
1304 + if (i == AR40XX_MALIBU_PHY_LAST_ADDR) {
1305 + /* to avoid goes into hibernation */
1306 + val = ar40xx_phy_mmd_read(priv, i, 3,
1307 + AR40XX_MALIBU_PHY_RLP_CTRL);
1308 + val &= (~(1<<1));
1309 + ar40xx_phy_mmd_write(priv, i, 3,
1310 + AR40XX_MALIBU_PHY_RLP_CTRL, val);
1311 + }
1312 + }
1313 +
1314 + /* adjust psgmii serdes tx amp */
1315 + mdiobus_write(bus, AR40XX_PSGMII_ID, AR40XX_PSGMII_TX_DRIVER_1_CTRL,
1316 + AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
1317 +}
1318 +
1319 +static int
1320 +ar40xx_hw_init(struct ar40xx_priv *priv)
1321 +{
1322 + u32 i;
1323 +
1324 + ar40xx_ess_reset(priv);
1325 +
1326 + if (priv->mii_bus)
1327 + ar40xx_malibu_init(priv);
1328 + else
1329 + return -1;
1330 +
1331 + ar40xx_psgmii_self_test(priv);
1332 + ar40xx_psgmii_self_test_clean(priv);
1333 +
1334 + ar40xx_mac_mode_init(priv, priv->mac_mode);
1335 +
1336 + for (i = 0; i < priv->dev.ports; i++)
1337 + ar40xx_init_port(priv, i);
1338 +
1339 + ar40xx_init_globals(priv);
1340 +
1341 + return 0;
1342 +}
1343 +
1344 +/* Start of qm error WAR */
1345 +
1346 +static
1347 +int ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id)
1348 +{
1349 + u32 reg;
1350 +
1351 + if (port_id < 0 || port_id > 6)
1352 + return -1;
1353 +
1354 + reg = AR40XX_REG_PORT_STATUS(port_id);
1355 + return ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED,
1356 + (AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX));
1357 +}
1358 +
1359 +static
1360 +int ar40xx_get_qm_status(struct ar40xx_priv *priv,
1361 + u32 port_id, u32 *qm_buffer_err)
1362 +{
1363 + u32 reg;
1364 + u32 qm_val;
1365 +
1366 + if (port_id < 1 || port_id > 5) {
1367 + *qm_buffer_err = 0;
1368 + return -1;
1369 + }
1370 +
1371 + if (port_id < 4) {
1372 + reg = AR40XX_REG_QM_PORT0_3_QNUM;
1373 + ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
1374 + qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
1375 + /* every 8 bits for each port */
1376 + *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
1377 + } else {
1378 + reg = AR40XX_REG_QM_PORT4_6_QNUM;
1379 + ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
1380 + qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
1381 + /* every 8 bits for each port */
1382 + *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
1383 + }
1384 +
1385 + return 0;
1386 +}
1387 +
1388 +static void
1389 +ar40xx_sw_mac_polling_task(struct ar40xx_priv *priv)
1390 +{
1391 + static int task_count;
1392 + u32 i;
1393 + u32 reg, value;
1394 + u32 link, speed, duplex;
1395 + u32 qm_buffer_err;
1396 + u16 port_phy_status[AR40XX_NUM_PORTS];
1397 + static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
1398 + static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
1399 + struct mii_bus *bus = NULL;
1400 +
1401 + if (!priv || !priv->mii_bus)
1402 + return;
1403 +
1404 + bus = priv->mii_bus;
1405 +
1406 + ++task_count;
1407 +
1408 + for (i = 1; i < AR40XX_NUM_PORTS; ++i) {
1409 + port_phy_status[i] =
1410 + mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS);
1411 + speed = link = duplex = port_phy_status[i];
1412 + speed &= AR40XX_PHY_SPEC_STATUS_SPEED;
1413 + speed >>= 14;
1414 + link &= AR40XX_PHY_SPEC_STATUS_LINK;
1415 + link >>= 10;
1416 + duplex &= AR40XX_PHY_SPEC_STATUS_DUPLEX;
1417 + duplex >>= 13;
1418 +
1419 + if (link != priv->ar40xx_port_old_link[i]) {
1420 + ++link_cnt[i];
1421 + /* Up --> Down */
1422 + if ((priv->ar40xx_port_old_link[i] ==
1423 + AR40XX_PORT_LINK_UP) &&
1424 + (link == AR40XX_PORT_LINK_DOWN)) {
1425 + /* LINK_EN disable(MAC force mode)*/
1426 + reg = AR40XX_REG_PORT_STATUS(i);
1427 + ar40xx_rmw(priv, reg,
1428 + AR40XX_PORT_AUTO_LINK_EN, 0);
1429 +
1430 + /* Check queue buffer */
1431 + qm_err_cnt[i] = 0;
1432 + ar40xx_get_qm_status(priv, i, &qm_buffer_err);
1433 + if (qm_buffer_err) {
1434 + priv->ar40xx_port_qm_buf[i] =
1435 + AR40XX_QM_NOT_EMPTY;
1436 + } else {
1437 + u16 phy_val = 0;
1438 +
1439 + priv->ar40xx_port_qm_buf[i] =
1440 + AR40XX_QM_EMPTY;
1441 + ar40xx_force_1g_full(priv, i);
1442 + /* Ref:QCA8337 Datasheet,Clearing
1443 + * MENU_CTRL_EN prevents phy to
1444 + * stuck in 100BT mode when
1445 + * bringing up the link
1446 + */
1447 + ar40xx_phy_dbg_read(priv, i-1,
1448 + AR40XX_PHY_DEBUG_0,
1449 + &phy_val);
1450 + phy_val &= (~AR40XX_PHY_MANU_CTRL_EN);
1451 + ar40xx_phy_dbg_write(priv, i-1,
1452 + AR40XX_PHY_DEBUG_0,
1453 + phy_val);
1454 + }
1455 + priv->ar40xx_port_old_link[i] = link;
1456 + } else if ((priv->ar40xx_port_old_link[i] ==
1457 + AR40XX_PORT_LINK_DOWN) &&
1458 + (link == AR40XX_PORT_LINK_UP)) {
1459 + /* Down --> Up */
1460 + if (priv->port_link_up[i] < 1) {
1461 + ++priv->port_link_up[i];
1462 + } else {
1463 + /* Change port status */
1464 + reg = AR40XX_REG_PORT_STATUS(i);
1465 + value = ar40xx_read(priv, reg);
1466 + priv->port_link_up[i] = 0;
1467 +
1468 + value &= ~(AR40XX_PORT_DUPLEX |
1469 + AR40XX_PORT_SPEED);
1470 + value |= speed | (duplex ? BIT(6) : 0);
1471 + ar40xx_write(priv, reg, value);
1472 + /* clock switch need such time
1473 + * to avoid glitch
1474 + */
1475 + usleep_range(100, 200);
1476 +
1477 + value |= AR40XX_PORT_AUTO_LINK_EN;
1478 + ar40xx_write(priv, reg, value);
1479 + /* HW need such time to make sure link
1480 + * stable before enable MAC
1481 + */
1482 + usleep_range(100, 200);
1483 +
1484 + if (speed == AR40XX_PORT_SPEED_100M) {
1485 + u16 phy_val = 0;
1486 + /* Enable @100M, if down to 10M
1487 + * clock will change smoothly
1488 + */
1489 + ar40xx_phy_dbg_read(priv, i-1,
1490 + 0,
1491 + &phy_val);
1492 + phy_val |=
1493 + AR40XX_PHY_MANU_CTRL_EN;
1494 + ar40xx_phy_dbg_write(priv, i-1,
1495 + 0,
1496 + phy_val);
1497 + }
1498 + priv->ar40xx_port_old_link[i] = link;
1499 + }
1500 + }
1501 + }
1502 +
1503 + if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) {
1504 + /* Check QM */
1505 + ar40xx_get_qm_status(priv, i, &qm_buffer_err);
1506 + if (qm_buffer_err) {
1507 + ++qm_err_cnt[i];
1508 + } else {
1509 + priv->ar40xx_port_qm_buf[i] =
1510 + AR40XX_QM_EMPTY;
1511 + qm_err_cnt[i] = 0;
1512 + ar40xx_force_1g_full(priv, i);
1513 + }
1514 + }
1515 + }
1516 +}
1517 +
1518 +static void
1519 +ar40xx_qm_err_check_work_task(struct work_struct *work)
1520 +{
1521 + struct ar40xx_priv *priv = container_of(work, struct ar40xx_priv,
1522 + qm_dwork.work);
1523 +
1524 + mutex_lock(&priv->qm_lock);
1525 +
1526 + ar40xx_sw_mac_polling_task(priv);
1527 +
1528 + mutex_unlock(&priv->qm_lock);
1529 +
1530 + schedule_delayed_work(&priv->qm_dwork,
1531 + msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
1532 +}
1533 +
1534 +static int
1535 +ar40xx_qm_err_check_work_start(struct ar40xx_priv *priv)
1536 +{
1537 + mutex_init(&priv->qm_lock);
1538 +
1539 + INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task);
1540 +
1541 + schedule_delayed_work(&priv->qm_dwork,
1542 + msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
1543 +
1544 + return 0;
1545 +}
1546 +
1547 +/* End of qm error WAR */
1548 +
1549 +static int
1550 +ar40xx_vlan_init(struct ar40xx_priv *priv)
1551 +{
1552 + int port;
1553 + unsigned long bmp;
1554 +
1555 + /* By default Enable VLAN */
1556 + priv->vlan = 1;
1557 + priv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp;
1558 + priv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp;
1559 + priv->vlan_tagged = priv->cpu_bmp;
1560 + bmp = priv->lan_bmp;
1561 + for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
1562 + priv->pvid[port] = AR40XX_LAN_VLAN;
1563 +
1564 + bmp = priv->wan_bmp;
1565 + for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
1566 + priv->pvid[port] = AR40XX_WAN_VLAN;
1567 +
1568 + return 0;
1569 +}
1570 +
1571 +static void
1572 +ar40xx_mib_work_func(struct work_struct *work)
1573 +{
1574 + struct ar40xx_priv *priv;
1575 + int err;
1576 +
1577 + priv = container_of(work, struct ar40xx_priv, mib_work.work);
1578 +
1579 + mutex_lock(&priv->mib_lock);
1580 +
1581 + err = ar40xx_mib_capture(priv);
1582 + if (err)
1583 + goto next_port;
1584 +
1585 + ar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1586 +
1587 +next_port:
1588 + priv->mib_next_port++;
1589 + if (priv->mib_next_port >= priv->dev.ports)
1590 + priv->mib_next_port = 0;
1591 +
1592 + mutex_unlock(&priv->mib_lock);
1593 +
1594 + schedule_delayed_work(&priv->mib_work,
1595 + msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
1596 +}
1597 +
1598 +static void
1599 +ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)
1600 +{
1601 + u32 t;
1602 + u32 egress, ingress;
1603 + u32 pvid = priv->vlan_id[priv->pvid[port]];
1604 +
1605 + if (priv->vlan) {
1606 + egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
1607 + ingress = AR40XX_IN_SECURE;
1608 + } else {
1609 + egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
1610 + ingress = AR40XX_IN_PORT_ONLY;
1611 + }
1612 +
1613 + t = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;
1614 + t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
1615 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
1616 +
1617 + t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
1618 + t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
1619 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
1620 +
1621 + t = members;
1622 + t |= AR40XX_PORT_LOOKUP_LEARN;
1623 + t |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;
1624 + t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
1625 + ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
1626 +}
1627 +
1628 +static void
1629 +ar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val)
1630 +{
1631 + if (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1,
1632 + AR40XX_VTU_FUNC1_BUSY, 0))
1633 + return;
1634 +
1635 + if ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD)
1636 + ar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val);
1637 +
1638 + op |= AR40XX_VTU_FUNC1_BUSY;
1639 + ar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op);
1640 +}
1641 +
1642 +static void
1643 +ar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask)
1644 +{
1645 + u32 op;
1646 + u32 val;
1647 + int i;
1648 +
1649 + op = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S);
1650 + val = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL;
1651 + for (i = 0; i < AR40XX_NUM_PORTS; i++) {
1652 + u32 mode;
1653 +
1654 + if ((port_mask & BIT(i)) == 0)
1655 + mode = AR40XX_VTU_FUNC0_EG_MODE_NOT;
1656 + else if (priv->vlan == 0)
1657 + mode = AR40XX_VTU_FUNC0_EG_MODE_KEEP;
1658 + else if ((priv->vlan_tagged & BIT(i)) ||
1659 + (priv->vlan_id[priv->pvid[i]] != vid))
1660 + mode = AR40XX_VTU_FUNC0_EG_MODE_TAG;
1661 + else
1662 + mode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG;
1663 +
1664 + val |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i);
1665 + }
1666 + ar40xx_vtu_op(priv, op, val);
1667 +}
1668 +
1669 +static void
1670 +ar40xx_vtu_flush(struct ar40xx_priv *priv)
1671 +{
1672 + ar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0);
1673 +}
1674 +
1675 +static int
1676 +ar40xx_sw_hw_apply(struct switch_dev *dev)
1677 +{
1678 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
1679 + u8 portmask[AR40XX_NUM_PORTS];
1680 + int i, j;
1681 +
1682 + mutex_lock(&priv->reg_mutex);
1683 + /* flush all vlan entries */
1684 + ar40xx_vtu_flush(priv);
1685 +
1686 + memset(portmask, 0, sizeof(portmask));
1687 + if (priv->vlan) {
1688 + for (j = 0; j < AR40XX_MAX_VLANS; j++) {
1689 + u8 vp = priv->vlan_table[j];
1690 +
1691 + if (!vp)
1692 + continue;
1693 +
1694 + for (i = 0; i < dev->ports; i++) {
1695 + u8 mask = BIT(i);
1696 +
1697 + if (vp & mask)
1698 + portmask[i] |= vp & ~mask;
1699 + }
1700 +
1701 + ar40xx_vtu_load_vlan(priv, priv->vlan_id[j],
1702 + priv->vlan_table[j]);
1703 + }
1704 + } else {
1705 + /* 8021q vlan disabled */
1706 + for (i = 0; i < dev->ports; i++) {
1707 + if (i == AR40XX_PORT_CPU)
1708 + continue;
1709 +
1710 + portmask[i] = BIT(AR40XX_PORT_CPU);
1711 + portmask[AR40XX_PORT_CPU] |= BIT(i);
1712 + }
1713 + }
1714 +
1715 + /* update the port destination mask registers and tag settings */
1716 + for (i = 0; i < dev->ports; i++)
1717 + ar40xx_setup_port(priv, i, portmask[i]);
1718 +
1719 + ar40xx_set_mirror_regs(priv);
1720 +
1721 + mutex_unlock(&priv->reg_mutex);
1722 + return 0;
1723 +}
1724 +
1725 +static int
1726 +ar40xx_sw_reset_switch(struct switch_dev *dev)
1727 +{
1728 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
1729 + int i, rv;
1730 +
1731 + mutex_lock(&priv->reg_mutex);
1732 + memset(&priv->vlan, 0, sizeof(struct ar40xx_priv) -
1733 + offsetof(struct ar40xx_priv, vlan));
1734 +
1735 + for (i = 0; i < AR40XX_MAX_VLANS; i++)
1736 + priv->vlan_id[i] = i;
1737 +
1738 + ar40xx_vlan_init(priv);
1739 +
1740 + priv->mirror_rx = false;
1741 + priv->mirror_tx = false;
1742 + priv->source_port = 0;
1743 + priv->monitor_port = 0;
1744 +
1745 + mutex_unlock(&priv->reg_mutex);
1746 +
1747 + rv = ar40xx_sw_hw_apply(dev);
1748 + return rv;
1749 +}
1750 +
1751 +static int
1752 +ar40xx_start(struct ar40xx_priv *priv)
1753 +{
1754 + int ret;
1755 +
1756 + ret = ar40xx_hw_init(priv);
1757 + if (ret)
1758 + return ret;
1759 +
1760 + ret = ar40xx_sw_reset_switch(&priv->dev);
1761 + if (ret)
1762 + return ret;
1763 +
1764 + /* at last, setup cpu port */
1765 + ret = ar40xx_cpuport_setup(priv);
1766 + if (ret)
1767 + return ret;
1768 +
1769 + schedule_delayed_work(&priv->mib_work,
1770 + msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
1771 +
1772 + ar40xx_qm_err_check_work_start(priv);
1773 +
1774 + return 0;
1775 +}
1776 +
1777 +static const struct switch_dev_ops ar40xx_sw_ops = {
1778 + .attr_global = {
1779 + .attr = ar40xx_sw_attr_globals,
1780 + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals),
1781 + },
1782 + .attr_port = {
1783 + .attr = ar40xx_sw_attr_port,
1784 + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_port),
1785 + },
1786 + .attr_vlan = {
1787 + .attr = ar40xx_sw_attr_vlan,
1788 + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan),
1789 + },
1790 + .get_port_pvid = ar40xx_sw_get_pvid,
1791 + .set_port_pvid = ar40xx_sw_set_pvid,
1792 + .get_vlan_ports = ar40xx_sw_get_ports,
1793 + .set_vlan_ports = ar40xx_sw_set_ports,
1794 + .apply_config = ar40xx_sw_hw_apply,
1795 + .reset_switch = ar40xx_sw_reset_switch,
1796 + .get_port_link = ar40xx_sw_get_port_link,
1797 +};
1798 +
1799 +/* Start of phy driver support */
1800 +
1801 +static const u32 ar40xx_phy_ids[] = {
1802 + 0x004dd0b1,
1803 + 0x004dd0b2, /* AR40xx */
1804 +};
1805 +
1806 +static bool
1807 +ar40xx_phy_match(u32 phy_id)
1808 +{
1809 + int i;
1810 +
1811 + for (i = 0; i < ARRAY_SIZE(ar40xx_phy_ids); i++)
1812 + if (phy_id == ar40xx_phy_ids[i])
1813 + return true;
1814 +
1815 + return false;
1816 +}
1817 +
1818 +static bool
1819 +is_ar40xx_phy(struct mii_bus *bus)
1820 +{
1821 + unsigned i;
1822 +
1823 + for (i = 0; i < 4; i++) {
1824 + u32 phy_id;
1825 +
1826 + phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1827 + phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1828 + if (!ar40xx_phy_match(phy_id))
1829 + return false;
1830 + }
1831 +
1832 + return true;
1833 +}
1834 +
1835 +static int
1836 +ar40xx_phy_probe(struct phy_device *phydev)
1837 +{
1838 + if (!is_ar40xx_phy(phydev->mdio.bus))
1839 + return -ENODEV;
1840 +
1841 + ar40xx_priv->mii_bus = phydev->mdio.bus;
1842 + phydev->priv = ar40xx_priv;
1843 + if (phydev->mdio.addr == 0)
1844 + ar40xx_priv->phy = phydev;
1845 +
1846 + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
1847 + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->advertising);
1848 + return 0;
1849 +}
1850 +
1851 +static void
1852 +ar40xx_phy_remove(struct phy_device *phydev)
1853 +{
1854 + ar40xx_priv->mii_bus = NULL;
1855 + phydev->priv = NULL;
1856 +}
1857 +
1858 +static int
1859 +ar40xx_phy_config_init(struct phy_device *phydev)
1860 +{
1861 + return 0;
1862 +}
1863 +
1864 +static int
1865 +ar40xx_phy_read_status(struct phy_device *phydev)
1866 +{
1867 + if (phydev->mdio.addr != 0)
1868 + return genphy_read_status(phydev);
1869 +
1870 + return 0;
1871 +}
1872 +
1873 +static int
1874 +ar40xx_phy_config_aneg(struct phy_device *phydev)
1875 +{
1876 + if (phydev->mdio.addr == 0)
1877 + return 0;
1878 +
1879 + return genphy_config_aneg(phydev);
1880 +}
1881 +
1882 +static struct phy_driver ar40xx_phy_driver = {
1883 + .phy_id = 0x004d0000,
1884 + .name = "QCA Malibu",
1885 + .phy_id_mask = 0xffff0000,
1886 + .features = PHY_GBIT_FEATURES,
1887 + .probe = ar40xx_phy_probe,
1888 + .remove = ar40xx_phy_remove,
1889 + .config_init = ar40xx_phy_config_init,
1890 + .config_aneg = ar40xx_phy_config_aneg,
1891 + .read_status = ar40xx_phy_read_status,
1892 +};
1893 +
1894 +static uint16_t ar40xx_gpio_get_phy(unsigned int offset)
1895 +{
1896 + return offset / 4;
1897 +}
1898 +
1899 +static uint16_t ar40xx_gpio_get_reg(unsigned int offset)
1900 +{
1901 + return 0x8074 + offset % 4;
1902 +}
1903 +
1904 +static void ar40xx_gpio_set(struct gpio_chip *gc, unsigned int offset,
1905 + int value)
1906 +{
1907 + struct ar40xx_priv *priv = gpiochip_get_data(gc);
1908 +
1909 + ar40xx_phy_mmd_write(priv, ar40xx_gpio_get_phy(offset), 0x7,
1910 + ar40xx_gpio_get_reg(offset),
1911 + value ? 0xA000 : 0x8000);
1912 +}
1913 +
1914 +static int ar40xx_gpio_get(struct gpio_chip *gc, unsigned offset)
1915 +{
1916 + struct ar40xx_priv *priv = gpiochip_get_data(gc);
1917 +
1918 + return ar40xx_phy_mmd_read(priv, ar40xx_gpio_get_phy(offset), 0x7,
1919 + ar40xx_gpio_get_reg(offset)) == 0xA000;
1920 +}
1921 +
1922 +static int ar40xx_gpio_get_dir(struct gpio_chip *gc, unsigned offset)
1923 +{
1924 + return 0; /* only out direction */
1925 +}
1926 +
1927 +static int ar40xx_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
1928 + int value)
1929 +{
1930 + /*
1931 + * the direction out value is used to set the initial value.
1932 + * support of this function is required by leds-gpio.c
1933 + */
1934 + ar40xx_gpio_set(gc, offset, value);
1935 + return 0;
1936 +}
1937 +
1938 +static void ar40xx_register_gpio(struct device *pdev,
1939 + struct ar40xx_priv *priv,
1940 + struct device_node *switch_node)
1941 +{
1942 + struct gpio_chip *gc;
1943 + int err;
1944 +
1945 + gc = devm_kzalloc(pdev, sizeof(*gc), GFP_KERNEL);
1946 + if (!gc)
1947 + return;
1948 +
1949 + gc->label = "ar40xx_gpio",
1950 + gc->base = -1,
1951 + gc->ngpio = 5 /* mmd 0 - 4 */ * 4 /* 0x8074 - 0x8077 */,
1952 + gc->parent = pdev;
1953 + gc->owner = THIS_MODULE;
1954 +
1955 + gc->get_direction = ar40xx_gpio_get_dir;
1956 + gc->direction_output = ar40xx_gpio_dir_out;
1957 + gc->get = ar40xx_gpio_get;
1958 + gc->set = ar40xx_gpio_set;
1959 + gc->can_sleep = true;
1960 + gc->label = priv->dev.name;
1961 + gc->of_node = switch_node;
1962 +
1963 + err = devm_gpiochip_add_data(pdev, gc, priv);
1964 + if (err != 0)
1965 + dev_err(pdev, "Failed to register gpio %d.\n", err);
1966 +}
1967 +
1968 +/* End of phy driver support */
1969 +
1970 +/* Platform driver probe function */
1971 +
1972 +static int ar40xx_probe(struct platform_device *pdev)
1973 +{
1974 + struct device_node *switch_node;
1975 + struct device_node *psgmii_node;
1976 + const __be32 *mac_mode;
1977 + struct clk *ess_clk;
1978 + struct switch_dev *swdev;
1979 + struct ar40xx_priv *priv;
1980 + u32 len;
1981 + u32 num_mibs;
1982 + struct resource psgmii_base = {0};
1983 + struct resource switch_base = {0};
1984 + int ret;
1985 +
1986 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1987 + if (!priv)
1988 + return -ENOMEM;
1989 +
1990 + platform_set_drvdata(pdev, priv);
1991 + ar40xx_priv = priv;
1992 +
1993 + switch_node = of_node_get(pdev->dev.of_node);
1994 + if (of_address_to_resource(switch_node, 0, &switch_base) != 0)
1995 + return -EIO;
1996 +
1997 + priv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base);
1998 + if (IS_ERR(priv->hw_addr)) {
1999 + dev_err(&pdev->dev, "Failed to ioremap switch_base!\n");
2000 + return PTR_ERR(priv->hw_addr);
2001 + }
2002 +
2003 + /*psgmii dts get*/
2004 + psgmii_node = of_find_node_by_name(NULL, "ess-psgmii");
2005 + if (!psgmii_node) {
2006 + dev_err(&pdev->dev, "Failed to find ess-psgmii node!\n");
2007 + return -EINVAL;
2008 + }
2009 +
2010 + if (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0)
2011 + return -EIO;
2012 +
2013 + priv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base);
2014 + if (IS_ERR(priv->psgmii_hw_addr)) {
2015 + dev_err(&pdev->dev, "psgmii ioremap fail!\n");
2016 + return PTR_ERR(priv->psgmii_hw_addr);
2017 + }
2018 +
2019 + mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
2020 + if (!mac_mode) {
2021 + dev_err(&pdev->dev, "Failed to read switch_mac_mode\n");
2022 + return -EINVAL;
2023 + }
2024 + priv->mac_mode = be32_to_cpup(mac_mode);
2025 +
2026 + ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
2027 + if (ess_clk)
2028 + clk_prepare_enable(ess_clk);
2029 +
2030 + priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst");
2031 + if (IS_ERR(priv->ess_rst)) {
2032 + dev_err(&pdev->dev, "Failed to get ess_rst control!\n");
2033 + return PTR_ERR(priv->ess_rst);
2034 + }
2035 +
2036 + if (of_property_read_u32(switch_node, "switch_cpu_bmp",
2037 + &priv->cpu_bmp) ||
2038 + of_property_read_u32(switch_node, "switch_lan_bmp",
2039 + &priv->lan_bmp) ||
2040 + of_property_read_u32(switch_node, "switch_wan_bmp",
2041 + &priv->wan_bmp)) {
2042 + dev_err(&pdev->dev, "Failed to read port properties\n");
2043 + return -EIO;
2044 + }
2045 +
2046 + ret = phy_driver_register(&ar40xx_phy_driver, THIS_MODULE);
2047 + if (ret) {
2048 + dev_err(&pdev->dev, "Failed to register ar40xx phy driver!\n");
2049 + return -EIO;
2050 + }
2051 +
2052 + mutex_init(&priv->reg_mutex);
2053 + mutex_init(&priv->mib_lock);
2054 + INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func);
2055 +
2056 + /* register switch */
2057 + swdev = &priv->dev;
2058 +
2059 + if (priv->mii_bus == NULL) {
2060 + dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n");
2061 + ret = -ENODEV;
2062 + goto err_missing_phy;
2063 + }
2064 +
2065 + swdev->alias = dev_name(&priv->mii_bus->dev);
2066 +
2067 + swdev->cpu_port = AR40XX_PORT_CPU;
2068 + swdev->name = "QCA AR40xx";
2069 + swdev->vlans = AR40XX_MAX_VLANS;
2070 + swdev->ports = AR40XX_NUM_PORTS;
2071 + swdev->ops = &ar40xx_sw_ops;
2072 + ret = register_switch(swdev, NULL);
2073 + if (ret)
2074 + goto err_unregister_phy;
2075 +
2076 + num_mibs = ARRAY_SIZE(ar40xx_mibs);
2077 + len = priv->dev.ports * num_mibs *
2078 + sizeof(*priv->mib_stats);
2079 + priv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
2080 + if (!priv->mib_stats) {
2081 + ret = -ENOMEM;
2082 + goto err_unregister_switch;
2083 + }
2084 +
2085 + ar40xx_start(priv);
2086 +
2087 + if (of_property_read_bool(switch_node, "gpio-controller"))
2088 + ar40xx_register_gpio(&pdev->dev, ar40xx_priv, switch_node);
2089 +
2090 + return 0;
2091 +
2092 +err_unregister_switch:
2093 + unregister_switch(&priv->dev);
2094 +err_unregister_phy:
2095 + phy_driver_unregister(&ar40xx_phy_driver);
2096 +err_missing_phy:
2097 + platform_set_drvdata(pdev, NULL);
2098 + return ret;
2099 +}
2100 +
2101 +static int ar40xx_remove(struct platform_device *pdev)
2102 +{
2103 + struct ar40xx_priv *priv = platform_get_drvdata(pdev);
2104 +
2105 + cancel_delayed_work_sync(&priv->qm_dwork);
2106 + cancel_delayed_work_sync(&priv->mib_work);
2107 +
2108 + unregister_switch(&priv->dev);
2109 +
2110 + phy_driver_unregister(&ar40xx_phy_driver);
2111 +
2112 + return 0;
2113 +}
2114 +
2115 +static const struct of_device_id ar40xx_of_mtable[] = {
2116 + {.compatible = "qcom,ess-switch" },
2117 + {}
2118 +};
2119 +
2120 +struct platform_driver ar40xx_drv = {
2121 + .probe = ar40xx_probe,
2122 + .remove = ar40xx_remove,
2123 + .driver = {
2124 + .name = "ar40xx",
2125 + .of_match_table = ar40xx_of_mtable,
2126 + },
2127 +};
2128 +
2129 +module_platform_driver(ar40xx_drv);
2130 +
2131 +MODULE_DESCRIPTION("IPQ40XX ESS driver");
2132 +MODULE_LICENSE("Dual BSD/GPL");
2133 Index: linux-5.4.51/drivers/net/phy/ar40xx.h
2134 ===================================================================
2135 --- /dev/null
2136 +++ linux-5.4.51/drivers/net/phy/ar40xx.h
2137 @@ -0,0 +1,337 @@
2138 +/*
2139 + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
2140 + *
2141 + * Permission to use, copy, modify, and/or distribute this software for
2142 + * any purpose with or without fee is hereby granted, provided that the
2143 + * above copyright notice and this permission notice appear in all copies.
2144 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
2145 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
2146 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
2147 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
2148 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
2149 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
2150 + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2151 + */
2152 +
2153 + #ifndef __AR40XX_H
2154 +#define __AR40XX_H
2155 +
2156 +#define AR40XX_MAX_VLANS 128
2157 +#define AR40XX_NUM_PORTS 6
2158 +#define AR40XX_NUM_PHYS 5
2159 +
2160 +#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
2161 +
2162 +struct ar40xx_priv {
2163 + struct switch_dev dev;
2164 +
2165 + u8 __iomem *hw_addr;
2166 + u8 __iomem *psgmii_hw_addr;
2167 + u32 mac_mode;
2168 + struct reset_control *ess_rst;
2169 + u32 cpu_bmp;
2170 + u32 lan_bmp;
2171 + u32 wan_bmp;
2172 +
2173 + struct mii_bus *mii_bus;
2174 + struct phy_device *phy;
2175 +
2176 + /* mutex for qm task */
2177 + struct mutex qm_lock;
2178 + struct delayed_work qm_dwork;
2179 + u32 port_link_up[AR40XX_NUM_PORTS];
2180 + u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
2181 + u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
2182 +
2183 + u32 phy_t_status;
2184 +
2185 + /* mutex for switch reg access */
2186 + struct mutex reg_mutex;
2187 +
2188 + /* mutex for mib task */
2189 + struct mutex mib_lock;
2190 + struct delayed_work mib_work;
2191 + int mib_next_port;
2192 + u64 *mib_stats;
2193 +
2194 + char buf[2048];
2195 +
2196 + /* all fields below will be cleared on reset */
2197 + bool vlan;
2198 + u16 vlan_id[AR40XX_MAX_VLANS];
2199 + u8 vlan_table[AR40XX_MAX_VLANS];
2200 + u8 vlan_tagged;
2201 + u16 pvid[AR40XX_NUM_PORTS];
2202 +
2203 + /* mirror */
2204 + bool mirror_rx;
2205 + bool mirror_tx;
2206 + int source_port;
2207 + int monitor_port;
2208 +};
2209 +
2210 +#define AR40XX_PORT_LINK_UP 1
2211 +#define AR40XX_PORT_LINK_DOWN 0
2212 +#define AR40XX_QM_NOT_EMPTY 1
2213 +#define AR40XX_QM_EMPTY 0
2214 +
2215 +#define AR40XX_LAN_VLAN 1
2216 +#define AR40XX_WAN_VLAN 2
2217 +
2218 +enum ar40xx_port_wrapper_cfg {
2219 + PORT_WRAPPER_PSGMII = 0,
2220 +};
2221 +
2222 +struct ar40xx_mib_desc {
2223 + u32 size;
2224 + u32 offset;
2225 + const char *name;
2226 +};
2227 +
2228 +#define AR40XX_PORT_CPU 0
2229 +
2230 +#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
2231 +#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
2232 +
2233 +#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
2234 +
2235 +#define AR40XX_MII_ATH_MMD_ADDR 0x0d
2236 +#define AR40XX_MII_ATH_MMD_DATA 0x0e
2237 +#define AR40XX_MII_ATH_DBG_ADDR 0x1d
2238 +#define AR40XX_MII_ATH_DBG_DATA 0x1e
2239 +
2240 +#define AR40XX_STATS_RXBROAD 0x00
2241 +#define AR40XX_STATS_RXPAUSE 0x04
2242 +#define AR40XX_STATS_RXMULTI 0x08
2243 +#define AR40XX_STATS_RXFCSERR 0x0c
2244 +#define AR40XX_STATS_RXALIGNERR 0x10
2245 +#define AR40XX_STATS_RXRUNT 0x14
2246 +#define AR40XX_STATS_RXFRAGMENT 0x18
2247 +#define AR40XX_STATS_RX64BYTE 0x1c
2248 +#define AR40XX_STATS_RX128BYTE 0x20
2249 +#define AR40XX_STATS_RX256BYTE 0x24
2250 +#define AR40XX_STATS_RX512BYTE 0x28
2251 +#define AR40XX_STATS_RX1024BYTE 0x2c
2252 +#define AR40XX_STATS_RX1518BYTE 0x30
2253 +#define AR40XX_STATS_RXMAXBYTE 0x34
2254 +#define AR40XX_STATS_RXTOOLONG 0x38
2255 +#define AR40XX_STATS_RXGOODBYTE 0x3c
2256 +#define AR40XX_STATS_RXBADBYTE 0x44
2257 +#define AR40XX_STATS_RXOVERFLOW 0x4c
2258 +#define AR40XX_STATS_FILTERED 0x50
2259 +#define AR40XX_STATS_TXBROAD 0x54
2260 +#define AR40XX_STATS_TXPAUSE 0x58
2261 +#define AR40XX_STATS_TXMULTI 0x5c
2262 +#define AR40XX_STATS_TXUNDERRUN 0x60
2263 +#define AR40XX_STATS_TX64BYTE 0x64
2264 +#define AR40XX_STATS_TX128BYTE 0x68
2265 +#define AR40XX_STATS_TX256BYTE 0x6c
2266 +#define AR40XX_STATS_TX512BYTE 0x70
2267 +#define AR40XX_STATS_TX1024BYTE 0x74
2268 +#define AR40XX_STATS_TX1518BYTE 0x78
2269 +#define AR40XX_STATS_TXMAXBYTE 0x7c
2270 +#define AR40XX_STATS_TXOVERSIZE 0x80
2271 +#define AR40XX_STATS_TXBYTE 0x84
2272 +#define AR40XX_STATS_TXCOLLISION 0x8c
2273 +#define AR40XX_STATS_TXABORTCOL 0x90
2274 +#define AR40XX_STATS_TXMULTICOL 0x94
2275 +#define AR40XX_STATS_TXSINGLECOL 0x98
2276 +#define AR40XX_STATS_TXEXCDEFER 0x9c
2277 +#define AR40XX_STATS_TXDEFER 0xa0
2278 +#define AR40XX_STATS_TXLATECOL 0xa4
2279 +
2280 +#define AR40XX_REG_MODULE_EN 0x030
2281 +#define AR40XX_MODULE_EN_MIB BIT(0)
2282 +
2283 +#define AR40XX_REG_MIB_FUNC 0x034
2284 +#define AR40XX_MIB_BUSY BIT(17)
2285 +#define AR40XX_MIB_CPU_KEEP BIT(20)
2286 +#define AR40XX_MIB_FUNC BITS(24, 3)
2287 +#define AR40XX_MIB_FUNC_S 24
2288 +#define AR40XX_MIB_FUNC_NO_OP 0x0
2289 +#define AR40XX_MIB_FUNC_FLUSH 0x1
2290 +
2291 +#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
2292 +#define AR40XX_PORT_SPEED BITS(0, 2)
2293 +#define AR40XX_PORT_STATUS_SPEED_S 0
2294 +#define AR40XX_PORT_TX_EN BIT(2)
2295 +#define AR40XX_PORT_RX_EN BIT(3)
2296 +#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
2297 +#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
2298 +#define AR40XX_PORT_DUPLEX BIT(6)
2299 +#define AR40XX_PORT_TXHALF_FLOW BIT(7)
2300 +#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
2301 +#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
2302 +#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
2303 +
2304 +#define AR40XX_REG_MAX_FRAME_SIZE 0x078
2305 +#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
2306 +
2307 +#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
2308 +
2309 +#define AR40XX_REG_EEE_CTRL 0x100
2310 +#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
2311 +
2312 +#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
2313 +#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
2314 +#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
2315 +#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
2316 +#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
2317 +
2318 +#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
2319 +#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
2320 +#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
2321 +#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
2322 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
2323 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
2324 +#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
2325 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
2326 +
2327 +#define AR40XX_REG_VTU_FUNC0 0x0610
2328 +#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
2329 +#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
2330 +#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
2331 +#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
2332 +#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
2333 +#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
2334 +#define AR40XX_VTU_FUNC0_IVL BIT(19)
2335 +#define AR40XX_VTU_FUNC0_VALID BIT(20)
2336 +
2337 +#define AR40XX_REG_VTU_FUNC1 0x0614
2338 +#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
2339 +#define AR40XX_VTU_FUNC1_OP_NOOP 0
2340 +#define AR40XX_VTU_FUNC1_OP_FLUSH 1
2341 +#define AR40XX_VTU_FUNC1_OP_LOAD 2
2342 +#define AR40XX_VTU_FUNC1_OP_PURGE 3
2343 +#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
2344 +#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
2345 +#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
2346 +#define AR40XX_VTU_FUNC1_FULL BIT(4)
2347 +#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
2348 +#define AR40XX_VTU_FUNC1_PORT_S 8
2349 +#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
2350 +#define AR40XX_VTU_FUNC1_VID_S 16
2351 +#define AR40XX_VTU_FUNC1_BUSY BIT(31)
2352 +
2353 +#define AR40XX_REG_FWD_CTRL0 0x620
2354 +#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
2355 +#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
2356 +#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
2357 +
2358 +#define AR40XX_REG_FWD_CTRL1 0x624
2359 +#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
2360 +#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
2361 +#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
2362 +#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
2363 +#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
2364 +#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
2365 +#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
2366 +#define AR40XX_FWD_CTRL1_IGMP_S 24
2367 +
2368 +#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
2369 +#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
2370 +#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
2371 +#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
2372 +#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
2373 +#define AR40XX_PORT_LOOKUP_STATE_S 16
2374 +#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
2375 +#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
2376 +#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
2377 +
2378 +#define AR40XX_REG_ATU_FUNC 0x60c
2379 +#define AR40XX_ATU_FUNC_OP BITS(0, 4)
2380 +#define AR40XX_ATU_FUNC_OP_NOOP 0x0
2381 +#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
2382 +#define AR40XX_ATU_FUNC_OP_LOAD 0x2
2383 +#define AR40XX_ATU_FUNC_OP_PURGE 0x3
2384 +#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
2385 +#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
2386 +#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
2387 +#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
2388 +#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
2389 +#define AR40XX_ATU_FUNC_BUSY BIT(31)
2390 +
2391 +#define AR40XX_REG_QM_DEBUG_ADDR 0x820
2392 +#define AR40XX_REG_QM_DEBUG_VALUE 0x824
2393 +#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
2394 +#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
2395 +
2396 +#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
2397 +#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
2398 +
2399 +#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
2400 +#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
2401 +#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
2402 +
2403 +#define AR40XX_PHY_DEBUG_0 0
2404 +#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
2405 +
2406 +#define AR40XX_PHY_DEBUG_2 2
2407 +
2408 +#define AR40XX_PHY_SPEC_STATUS 0x11
2409 +#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
2410 +#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
2411 +#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
2412 +
2413 +/* port forwarding state */
2414 +enum {
2415 + AR40XX_PORT_STATE_DISABLED = 0,
2416 + AR40XX_PORT_STATE_BLOCK = 1,
2417 + AR40XX_PORT_STATE_LISTEN = 2,
2418 + AR40XX_PORT_STATE_LEARN = 3,
2419 + AR40XX_PORT_STATE_FORWARD = 4
2420 +};
2421 +
2422 +/* ingress 802.1q mode */
2423 +enum {
2424 + AR40XX_IN_PORT_ONLY = 0,
2425 + AR40XX_IN_PORT_FALLBACK = 1,
2426 + AR40XX_IN_VLAN_ONLY = 2,
2427 + AR40XX_IN_SECURE = 3
2428 +};
2429 +
2430 +/* egress 802.1q mode */
2431 +enum {
2432 + AR40XX_OUT_KEEP = 0,
2433 + AR40XX_OUT_STRIP_VLAN = 1,
2434 + AR40XX_OUT_ADD_VLAN = 2
2435 +};
2436 +
2437 +/* port speed */
2438 +enum {
2439 + AR40XX_PORT_SPEED_10M = 0,
2440 + AR40XX_PORT_SPEED_100M = 1,
2441 + AR40XX_PORT_SPEED_1000M = 2,
2442 + AR40XX_PORT_SPEED_ERR = 3,
2443 +};
2444 +
2445 +#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
2446 +
2447 +#define AR40XX_QM_WORK_DELAY 100
2448 +
2449 +#define AR40XX_MIB_FUNC_CAPTURE 0x3
2450 +
2451 +#define AR40XX_REG_PORT_STATS_START 0x1000
2452 +#define AR40XX_REG_PORT_STATS_LEN 0x100
2453 +
2454 +#define AR40XX_PORTS_ALL 0x3f
2455 +
2456 +#define AR40XX_PSGMII_ID 5
2457 +#define AR40XX_PSGMII_CALB_NUM 100
2458 +#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
2459 +#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
2460 +#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
2461 +#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
2462 +#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
2463 +#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
2464 +#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
2465 +#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
2466 +#define AR40XX_MALIBU_PHY_LAST_ADDR 4
2467 +
2468 +static inline struct ar40xx_priv *
2469 +swdev_to_ar40xx(struct switch_dev *swdev)
2470 +{
2471 + return container_of(swdev, struct ar40xx_priv, dev);
2472 +}
2473 +
2474 +#endif
OpenWrt Source Repository