b3ccb2ede2cf2e13882f62b766024579e6a994cd
[openwrt/openwrt.git] / target / linux / ipq806x / files-4.9 / arch / arm / boot / dts / qcom-ipq8065.dtsi
1 #include "qcom-ipq8064.dtsi"
2
3 / {
4 model = "Qualcomm IPQ8065";
5 compatible = "qcom,ipq8065", "qcom,ipq8064";
6
7 qcom,pvs {
8 qcom,pvs-format-a;
9 qcom,speed0-pvs0-bin-v0 =
10 < 1725000000 1262500 >,
11 < 1400000000 1175000 >,
12 < 1000000000 1100000 >,
13 < 800000000 1050000 >,
14 < 600000000 1000000 >,
15 < 384000000 975000 >;
16 qcom,speed0-pvs1-bin-v0 =
17 < 1725000000 1225000 >,
18 < 1400000000 1150000 >,
19 < 1000000000 1075000 >,
20 < 800000000 1025000 >,
21 < 600000000 975000 >,
22 < 384000000 950000 >;
23 qcom,speed0-pvs2-bin-v0 =
24 < 1725000000 1200000 >,
25 < 1400000000 1125000 >,
26 < 1000000000 1050000 >,
27 < 800000000 1000000 >,
28 < 600000000 950000 >,
29 < 384000000 925000 >;
30 qcom,speed0-pvs3-bin-v0 =
31 < 1725000000 1175000 >,
32 < 1400000000 1100000 >,
33 < 1000000000 1025000 >,
34 < 800000000 975000 >,
35 < 600000000 925000 >,
36 < 384000000 900000 >;
37 qcom,speed0-pvs4-bin-v0 =
38 < 1725000000 1150000 >,
39 < 1400000000 1075000 >,
40 < 1000000000 1000000 >,
41 < 800000000 950000 >,
42 < 600000000 900000 >,
43 < 384000000 875000 >;
44 qcom,speed0-pvs5-bin-v0 =
45 < 1725000000 1100000 >,
46 < 1400000000 1025000 >,
47 < 1000000000 950000 >,
48 < 800000000 900000 >,
49 < 600000000 850000 >,
50 < 384000000 825000 >;
51 qcom,speed0-pvs6-bin-v0 =
52 < 1725000000 1050000 >,
53 < 1400000000 975000 >,
54 < 1000000000 900000 >,
55 < 800000000 850000 >,
56 < 600000000 800000 >,
57 < 384000000 775000 >;
58 };
59
60 soc: soc {
61
62 rpm@108000 {
63
64 regulators {
65
66 smb208_s2a: s2a {
67 regulator-min-microvolt = <775000>;
68 regulator-max-microvolt = <1275000>;
69 };
70
71 smb208_s2b: s2b {
72 regulator-min-microvolt = <775000>;
73 regulator-max-microvolt = <1275000>;
74 };
75 };
76 };
77
78 /* Temporary fixed regulator */
79 vsdcc_fixed: vsdcc-regulator {
80 compatible = "regulator-fixed";
81 regulator-name = "SDCC Power";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-always-on;
85 };
86
87 sdcc1bam:dma@12402000 {
88 compatible = "qcom,bam-v1.3.0";
89 reg = <0x12402000 0x8000>;
90 interrupts = <0 98 0>;
91 clocks = <&gcc SDC1_H_CLK>;
92 clock-names = "bam_clk";
93 #dma-cells = <1>;
94 qcom,ee = <0>;
95 };
96
97 sdcc3bam:dma@12182000 {
98 compatible = "qcom,bam-v1.3.0";
99 reg = <0x12182000 0x8000>;
100 interrupts = <0 96 0>;
101 clocks = <&gcc SDC3_H_CLK>;
102 clock-names = "bam_clk";
103 #dma-cells = <1>;
104 qcom,ee = <0>;
105 };
106
107 amba {
108 compatible = "arm,amba-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112 sdcc1: sdcc@12400000 {
113 status = "disabled";
114 compatible = "arm,pl18x", "arm,primecell";
115 arm,primecell-periphid = <0x00051180>;
116 reg = <0x12400000 0x2000>;
117 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-names = "cmd_irq";
119 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
120 clock-names = "mclk", "apb_pclk";
121 bus-width = <8>;
122 max-frequency = <96000000>;
123 non-removable;
124 cap-sd-highspeed;
125 cap-mmc-highspeed;
126 vmmc-supply = <&vsdcc_fixed>;
127 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
128 dma-names = "tx", "rx";
129 };
130
131 sdcc3: sdcc@12180000 {
132 compatible = "arm,pl18x", "arm,primecell";
133 arm,primecell-periphid = <0x00051180>;
134 status = "disabled";
135 reg = <0x12180000 0x2000>;
136 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
137 interrupt-names = "cmd_irq";
138 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
139 clock-names = "mclk", "apb_pclk";
140 bus-width = <8>;
141 cap-sd-highspeed;
142 cap-mmc-highspeed;
143 max-frequency = <192000000>;
144 #mmc-ddr-1_8v;
145 sd-uhs-sdr104;
146 sd-uhs-ddr50;
147 vqmmc-supply = <&vsdcc_fixed>;
148 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
149 dma-names = "tx", "rx";
150 };
151 };
152 };
153 };