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ipq806x: enable hw pseudo random number generator
[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8065";
15 compatible = "qcom,ipq8065", "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 qcom,imem = <&qfprom>;
33 clock-latency = <100000>;
34 cpu-supply = <&smb208_s2a>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
38 #cooling-cells = <2>;
39 cpu-idle-states = <&CPU_SPC>;
40 };
41
42 cpu1: cpu@1 {
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
45 device_type = "cpu";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 qcom,acc = <&acc1>;
49 qcom,saw = <&saw1>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 qcom,imem = <&qfprom>;
53 clock-latency = <100000>;
54 cpu-supply = <&smb208_s2b>;
55 cooling-min-state = <0>;
56 cooling-max-state = <10>;
57 #cooling-cells = <2>;
58 cpu-idle-states = <&CPU_SPC>;
59 };
60
61 L2: l2-cache {
62 compatible = "cache";
63 cache-level = <2>;
64 qcom,saw = <&saw_l2>;
65 };
66
67 qcom,l2 {
68 qcom,l2-rates = <384000000 1000000000 1200000000>;
69 };
70
71 idle-states {
72 CPU_SPC: spc {
73 compatible = "qcom,idle-state-spc",
74 "arm,idle-state";
75 entry-latency-us = <400>;
76 exit-latency-us = <900>;
77 min-residency-us = <3000>;
78 };
79 };
80 };
81
82 thermal-zones {
83 cpu-thermal0 {
84 polling-delay-passive = <250>;
85 polling-delay = <1000>;
86
87 thermal-sensors = <&gcc 5>;
88 coefficients = <1132 0>;
89
90 trips {
91 cpu_alert0: trip0 {
92 temperature = <75000>;
93 hysteresis = <2000>;
94 type = "passive";
95 };
96 cpu_crit0: trip1 {
97 temperature = <110000>;
98 hysteresis = <2000>;
99 type = "critical";
100 };
101 };
102 };
103
104 cpu-thermal1 {
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
107
108 thermal-sensors = <&gcc 6>;
109 coefficients = <1132 0>;
110
111 trips {
112 cpu_alert1: trip0 {
113 temperature = <75000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117 cpu_crit1: trip1 {
118 temperature = <110000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 cpu-thermal2 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
128
129 thermal-sensors = <&gcc 7>;
130 coefficients = <1199 0>;
131
132 trips {
133 cpu_alert2: trip0 {
134 temperature = <75000>;
135 hysteresis = <2000>;
136 type = "passive";
137 };
138 cpu_crit2: trip1 {
139 temperature = <110000>;
140 hysteresis = <2000>;
141 type = "critical";
142 };
143 };
144 };
145
146 cpu-thermal3 {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
149
150 thermal-sensors = <&gcc 8>;
151 coefficients = <1132 0>;
152
153 trips {
154 cpu_alert3: trip0 {
155 temperature = <75000>;
156 hysteresis = <2000>;
157 type = "passive";
158 };
159 cpu_crit3: trip1 {
160 temperature = <110000>;
161 hysteresis = <2000>;
162 type = "critical";
163 };
164 };
165 };
166 };
167
168 cpu-pmu {
169 compatible = "qcom,krait-pmu";
170 interrupts = <1 10 0x304>;
171 };
172
173 reserved-memory {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 ranges;
177
178 nss@40000000 {
179 reg = <0x40000000 0x1000000>;
180 no-map;
181 };
182
183 smem: smem@41000000 {
184 reg = <0x41000000 0x200000>;
185 no-map;
186 };
187 };
188
189 clocks {
190
191 cxo_board {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <25000000>;
195 };
196
197 pxo_board {
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <25000000>;
201 };
202
203 sleep_clk: sleep_clk {
204 compatible = "fixed-clock";
205 clock-frequency = <32768>;
206 #clock-cells = <0>;
207 };
208 };
209
210 kraitcc: clock-controller {
211 compatible = "qcom,krait-cc-v1";
212 #clock-cells = <1>;
213 };
214
215 qcom,pvs {
216 qcom,pvs-format-a;
217 qcom,speed0-pvs0-bin-v0 =
218 < 1725000000 1262500 >,
219 < 1400000000 1175000 >,
220 < 1000000000 1100000 >,
221 < 800000000 1050000 >,
222 < 600000000 1000000 >,
223 < 384000000 975000 >;
224 qcom,speed0-pvs1-bin-v0 =
225 < 1725000000 1225000 >,
226 < 1400000000 1150000 >,
227 < 1000000000 1075000 >,
228 < 800000000 1025000 >,
229 < 600000000 975000 >,
230 < 384000000 950000 >;
231 qcom,speed0-pvs2-bin-v0 =
232 < 1725000000 1200000 >,
233 < 1400000000 1125000 >,
234 < 1000000000 1050000 >,
235 < 800000000 1000000 >,
236 < 600000000 950000 >,
237 < 384000000 925000 >;
238 qcom,speed0-pvs3-bin-v0 =
239 < 1725000000 1175000 >,
240 < 1400000000 1100000 >,
241 < 1000000000 1025000 >,
242 < 800000000 975000 >,
243 < 600000000 925000 >,
244 < 384000000 900000 >;
245 qcom,speed0-pvs4-bin-v0 =
246 < 1725000000 1150000 >,
247 < 1400000000 1075000 >,
248 < 1000000000 1000000 >,
249 < 800000000 950000 >,
250 < 600000000 900000 >,
251 < 384000000 875000 >;
252 qcom,speed0-pvs5-bin-v0 =
253 < 1725000000 1100000 >,
254 < 1400000000 1025000 >,
255 < 1000000000 950000 >,
256 < 800000000 900000 >,
257 < 600000000 850000 >,
258 < 384000000 825000 >;
259 qcom,speed0-pvs6-bin-v0 =
260 < 1725000000 1050000 >,
261 < 1400000000 975000 >,
262 < 1000000000 900000 >,
263 < 800000000 850000 >,
264 < 600000000 800000 >,
265 < 384000000 775000 >;
266 };
267
268 soc: soc {
269 #address-cells = <1>;
270 #size-cells = <1>;
271 ranges;
272 compatible = "simple-bus";
273
274 lpass@28100000 {
275 compatible = "qcom,lpass-cpu";
276 status = "disabled";
277 clocks = <&lcc AHBIX_CLK>,
278 <&lcc MI2S_OSR_CLK>,
279 <&lcc MI2S_BIT_CLK>;
280 clock-names = "ahbix-clk",
281 "mi2s-osr-clk",
282 "mi2s-bit-clk";
283 interrupts = <0 85 1>;
284 interrupt-names = "lpass-irq-lpaif";
285 reg = <0x28100000 0x10000>;
286 reg-names = "lpass-lpaif";
287 };
288
289 qfprom: qfprom@700000 {
290 compatible = "qcom,qfprom", "syscon";
291 reg = <0x00700000 0x1000>;
292 #address-cells = <1>;
293 #size-cells = <1>;
294 ranges;
295
296 tsens_calib: calib {
297 reg = <0x400 0x10>;
298 };
299 tsens_backup: backup_calib {
300 reg = <0x410 0x10>;
301 };
302 };
303
304 rpm@108000 {
305 compatible = "qcom,rpm-ipq8064";
306 reg = <0x108000 0x1000>;
307 qcom,ipc = <&l2cc 0x8 2>;
308
309 interrupts = <0 19 0>,
310 <0 21 0>,
311 <0 22 0>;
312 interrupt-names = "ack",
313 "err",
314 "wakeup";
315
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
320 clock-names = "ram";
321
322 rpmcc: clock-controller {
323 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
324 #clock-cells = <1>;
325 };
326
327 smb208_regulators {
328 compatible = "qcom,rpm-smb208-regulators";
329
330 smb208_s1a: s1a {
331 regulator-min-microvolt = <1050000>;
332 regulator-max-microvolt = <1150000>;
333 qcom,switch-mode-frequency = <1200000>;
334 };
335
336 smb208_s1b: s1b {
337 regulator-min-microvolt = <1050000>;
338 regulator-max-microvolt = <1150000>;
339 qcom,switch-mode-frequency = <1200000>;
340 };
341
342 smb208_s2a: s2a {
343 regulator-min-microvolt = <775000>;
344 regulator-max-microvolt = <1275000>;
345 qcom,switch-mode-frequency = <1200000>;
346 };
347
348 smb208_s2b: s2b {
349 regulator-min-microvolt = <775000>;
350 regulator-max-microvolt = <1275000>;
351 qcom,switch-mode-frequency = <1200000>;
352 };
353 };
354 };
355
356 rng@1a500000 {
357 compatible = "qcom,prng";
358 reg = <0x1a500000 0x200>;
359 clocks = <&gcc PRNG_CLK>;
360 clock-names = "core";
361 };
362
363 qcom,msm-imem@2A03F000 {
364 compatible = "qcom,msm-imem";
365 reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
366 ranges = <0x0 0x2A03F000 0x1000>;
367 #address-cells = <1>;
368 #size-cells = <1>;
369
370 download_mode@0 {
371 compatible = "qcom,msm-imem-download_mode";
372 reg = <0x0 8>;
373 };
374
375 restart_reason@65c {
376 compatible = "qcom,msm-imem-restart_reason";
377 reg = <0x65c 4>;
378 };
379
380 l2_dump_offset@14 {
381 compatible = "qcom,msm-imem-l2_dump_offset";
382 reg = <0x14 8>;
383 };
384 };
385
386 qcom_pinmux: pinmux@800000 {
387 compatible = "qcom,ipq8064-pinctrl";
388 reg = <0x800000 0x4000>;
389
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 interrupts = <0 16 0x4>;
395
396 pcie0_pins: pcie0_pinmux {
397 mux {
398 pins = "gpio3";
399 function = "pcie1_rst";
400 drive-strength = <2>;
401 bias-disable;
402 };
403 };
404
405 pcie1_pins: pcie1_pinmux {
406 mux {
407 pins = "gpio48";
408 function = "pcie2_rst";
409 drive-strength = <2>;
410 bias-disable;
411 };
412 };
413
414 pcie2_pins: pcie2_pinmux {
415 mux {
416 pins = "gpio63";
417 function = "pcie3_rst";
418 drive-strength = <2>;
419 bias-disable;
420 output-low;
421 };
422 };
423 };
424
425 intc: interrupt-controller@2000000 {
426 compatible = "qcom,msm-qgic2";
427 interrupt-controller;
428 #interrupt-cells = <3>;
429 reg = <0x02000000 0x1000>,
430 <0x02002000 0x1000>;
431 };
432
433 timer@200a000 {
434 compatible = "qcom,kpss-timer", "qcom,msm-timer";
435 interrupts = <1 1 0x301>,
436 <1 2 0x301>,
437 <1 3 0x301>,
438 <1 4 0x301>,
439 <1 5 0x301>;
440 reg = <0x0200a000 0x100>;
441 clock-frequency = <25000000>,
442 <32768>;
443 clocks = <&sleep_clk>;
444 clock-names = "sleep";
445 cpu-offset = <0x80000>;
446 };
447
448 acc0: clock-controller@2088000 {
449 compatible = "qcom,kpss-acc-v1";
450 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
451 clock-output-names = "acpu0_aux";
452 };
453
454 acc1: clock-controller@2098000 {
455 compatible = "qcom,kpss-acc-v1";
456 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
457 clock-output-names = "acpu1_aux";
458 };
459
460 l2cc: clock-controller@2011000 {
461 compatible = "qcom,kpss-gcc", "syscon";
462 reg = <0x2011000 0x1000>;
463 clock-output-names = "acpu_l2_aux";
464 };
465
466 saw0: regulator@2089000 {
467 compatible = "qcom,saw2", "syscon";
468 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
469 regulator;
470 };
471
472 saw1: regulator@2099000 {
473 compatible = "qcom,saw2", "syscon";
474 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
475 regulator;
476 };
477
478 saw_l2: regulator@02012000 {
479 compatible = "qcom,saw2", "syscon";
480 reg = <0x02012000 0x1000>;
481 regulator;
482 };
483
484 sic_non_secure: sic-non-secure@12100000 {
485 compatible = "syscon";
486 reg = <0x12100000 0x10000>;
487 };
488
489 gsbi1: gsbi@12440000 {
490 compatible = "qcom,gsbi-v1.0.0";
491 cell-index = <1>;
492 reg = <0x12440000 0x100>;
493 clocks = <&gcc GSBI1_H_CLK>;
494 clock-names = "iface";
495 #address-cells = <1>;
496 #size-cells = <1>;
497 ranges;
498 status = "disabled";
499
500 syscon-tcsr = <&tcsr>;
501
502 uart1: serial@12450000 {
503 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
504 reg = <0x12450000 0x1000>,
505 <0x12440000 0x1000>;
506 interrupts = <0 193 0x0>;
507 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
508 clock-names = "core", "iface";
509 status = "disabled";
510 };
511
512 i2c@12460000 {
513 compatible = "qcom,i2c-qup-v1.1.1";
514 reg = <0x12460000 0x1000>;
515 interrupts = <0 194 0>;
516
517 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
518 clock-names = "core", "iface";
519 status = "disabled";
520
521 #address-cells = <1>;
522 #size-cells = <0>;
523 };
524
525 };
526
527 gsbi2: gsbi@12480000 {
528 compatible = "qcom,gsbi-v1.0.0";
529 cell-index = <2>;
530 reg = <0x12480000 0x100>;
531 clocks = <&gcc GSBI2_H_CLK>;
532 clock-names = "iface";
533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges;
536 status = "disabled";
537
538 syscon-tcsr = <&tcsr>;
539
540 uart2: serial@12490000 {
541 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
542 reg = <0x12490000 0x1000>,
543 <0x12480000 0x1000>;
544 interrupts = <0 195 0x0>;
545 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
546 clock-names = "core", "iface";
547 status = "disabled";
548 };
549
550 i2c@124a0000 {
551 compatible = "qcom,i2c-qup-v1.1.1";
552 reg = <0x124a0000 0x1000>;
553 interrupts = <0 196 0>;
554
555 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
556 clock-names = "core", "iface";
557 status = "disabled";
558
559 #address-cells = <1>;
560 #size-cells = <0>;
561 };
562
563 };
564
565 gsbi4: gsbi@16300000 {
566 compatible = "qcom,gsbi-v1.0.0";
567 cell-index = <4>;
568 reg = <0x16300000 0x100>;
569 clocks = <&gcc GSBI4_H_CLK>;
570 clock-names = "iface";
571 #address-cells = <1>;
572 #size-cells = <1>;
573 ranges;
574 status = "disabled";
575
576 syscon-tcsr = <&tcsr>;
577
578 uart4: serial@16340000 {
579 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
580 reg = <0x16340000 0x1000>,
581 <0x16300000 0x1000>;
582 interrupts = <0 152 0x0>;
583 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
584 clock-names = "core", "iface";
585 status = "disabled";
586 };
587
588 i2c@16380000 {
589 compatible = "qcom,i2c-qup-v1.1.1";
590 reg = <0x16380000 0x1000>;
591 interrupts = <0 153 0>;
592
593 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
594 clock-names = "core", "iface";
595 status = "disabled";
596
597 #address-cells = <1>;
598 #size-cells = <0>;
599 };
600 };
601
602 gsbi5: gsbi@1a200000 {
603 compatible = "qcom,gsbi-v1.0.0";
604 cell-index = <5>;
605 reg = <0x1a200000 0x100>;
606 clocks = <&gcc GSBI5_H_CLK>;
607 clock-names = "iface";
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges;
611 status = "disabled";
612
613 syscon-tcsr = <&tcsr>;
614
615 uart5: serial@1a240000 {
616 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
617 reg = <0x1a240000 0x1000>,
618 <0x1a200000 0x1000>;
619 interrupts = <0 154 0x0>;
620 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
621 clock-names = "core", "iface";
622 status = "disabled";
623 };
624
625 i2c@1a280000 {
626 compatible = "qcom,i2c-qup-v1.1.1";
627 reg = <0x1a280000 0x1000>;
628 interrupts = <0 155 0>;
629
630 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
631 clock-names = "core", "iface";
632 status = "disabled";
633
634 #address-cells = <1>;
635 #size-cells = <0>;
636 };
637
638 spi@1a280000 {
639 compatible = "qcom,spi-qup-v1.1.1";
640 reg = <0x1a280000 0x1000>;
641 interrupts = <0 155 0>;
642
643 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
644 clock-names = "core", "iface";
645 status = "disabled";
646
647 #address-cells = <1>;
648 #size-cells = <0>;
649 };
650 };
651
652 gsbi6: gsbi@16500000 {
653 compatible = "qcom,gsbi-v1.0.0";
654 cell-index = <6>;
655 reg = <0x16500000 0x100>;
656 clocks = <&gcc GSBI6_H_CLK>;
657 clock-names = "iface";
658 #address-cells = <1>;
659 #size-cells = <1>;
660 ranges;
661 status = "disabled";
662
663 syscon-tcsr = <&tcsr>;
664
665 uart6: serial@16540000 {
666 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
667 reg = <0x16540000 0x1000>,
668 <0x16500000 0x1000>;
669 interrupts = <0 156 0x0>;
670 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
671 clock-names = "core", "iface";
672 status = "disabled";
673 };
674
675 i2c@16580000 {
676 compatible = "qcom,i2c-qup-v1.1.1";
677 reg = <0x16580000 0x1000>;
678 interrupts = <0 157 0>;
679
680 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
681 clock-names = "core", "iface";
682 status = "disabled";
683
684 #address-cells = <1>;
685 #size-cells = <0>;
686 };
687
688 spi@16580000 {
689 compatible = "qcom,spi-qup-v1.1.1";
690 reg = <0x16580000 0x1000>;
691 interrupts = <0 157 0>;
692
693 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
694 clock-names = "core", "iface";
695 status = "disabled";
696
697 #address-cells = <1>;
698 #size-cells = <0>;
699 };
700 };
701
702 gsbi7: gsbi@16600000 {
703 compatible = "qcom,gsbi-v1.0.0";
704 cell-index = <7>;
705 reg = <0x16600000 0x100>;
706 clocks = <&gcc GSBI7_H_CLK>;
707 clock-names = "iface";
708 #address-cells = <1>;
709 #size-cells = <1>;
710 ranges;
711 status = "disabled";
712
713 syscon-tcsr = <&tcsr>;
714
715 uart7: serial@16640000 {
716 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
717 reg = <0x16640000 0x1000>,
718 <0x16600000 0x1000>;
719 interrupts = <0 158 0x0>;
720 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
721 clock-names = "core", "iface";
722 status = "disabled";
723 };
724
725 i2c@16680000 {
726 compatible = "qcom,i2c-qup-v1.1.1";
727 reg = <0x16680000 0x1000>;
728 interrupts = <0 159 0>;
729
730 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
731 clock-names = "core", "iface";
732 status = "disabled";
733
734 #address-cells = <1>;
735 #size-cells = <0>;
736 };
737
738 };
739
740 sata_phy: sata-phy@1b400000 {
741 compatible = "qcom,ipq806x-sata-phy";
742 reg = <0x1b400000 0x200>;
743
744 clocks = <&gcc SATA_PHY_CFG_CLK>;
745 clock-names = "cfg";
746
747 #phy-cells = <0>;
748 status = "disabled";
749 };
750
751 sata@29000000 {
752 compatible = "qcom,ipq806x-ahci", "generic-ahci";
753 reg = <0x29000000 0x180>;
754
755 interrupts = <0 209 0x0>;
756
757 clocks = <&gcc SFAB_SATA_S_H_CLK>,
758 <&gcc SATA_H_CLK>,
759 <&gcc SATA_A_CLK>,
760 <&gcc SATA_RXOOB_CLK>,
761 <&gcc SATA_PMALIVE_CLK>;
762 clock-names = "slave_face", "iface", "core",
763 "rxoob", "pmalive";
764
765 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
766 assigned-clock-rates = <100000000>, <100000000>;
767
768 phys = <&sata_phy>;
769 phy-names = "sata-phy";
770 status = "disabled";
771 };
772
773 qcom,ssbi@500000 {
774 compatible = "qcom,ssbi";
775 reg = <0x00500000 0x1000>;
776 qcom,controller-type = "pmic-arbiter";
777 };
778
779 gcc: clock-controller@900000 {
780 compatible = "qcom,gcc-ipq8064";
781 reg = <0x00900000 0x4000>;
782 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
783 nvmem-cell-names = "calib", "calib_backup";
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
787 #thermal-sensor-cells = <1>;
788 };
789
790 lcc: clock-controller@28000000 {
791 compatible = "qcom,lcc-ipq8064";
792 reg = <0x28000000 0x1000>;
793 #clock-cells = <1>;
794 #reset-cells = <1>;
795 };
796
797 tcsr: syscon@1a400000 {
798 compatible = "qcom,tcsr-ipq8064", "syscon";
799 reg = <0x1a400000 0x100>;
800 };
801
802 qcom,msm-thermal {
803 compatible = "qcom,msm-thermal";
804 qcom,sensor-id = <0>;
805 qcom,poll-ms = <250>;
806 qcom,limit-temp = <105>;
807 qcom,temp-hysteresis = <10>;
808 qcom,freq-step = <2>;
809 qcom,core-limit-temp = <115>;
810 qcom,core-temp-hysteresis = <10>;
811 qcom,core-control-mask = <0xe>;
812 };
813
814 sfpb_mutex_block: syscon@1200600 {
815 compatible = "syscon";
816 reg = <0x01200600 0x100>;
817 };
818
819 hs_phy_1: phy@100f8800 {
820 compatible = "qcom,dwc3-hs-usb-phy";
821 reg = <0x100f8800 0x30>;
822 clocks = <&gcc USB30_1_UTMI_CLK>;
823 clock-names = "ref";
824 #phy-cells = <0>;
825
826 status = "disabled";
827 };
828
829 ss_phy_1: phy@100f8830 {
830 compatible = "qcom,dwc3-ss-usb-phy";
831 reg = <0x100f8830 0x30>;
832 clocks = <&gcc USB30_1_MASTER_CLK>;
833 clock-names = "ref";
834 #phy-cells = <0>;
835
836 status = "disabled";
837 };
838
839 hs_phy_0: phy@110f8800 {
840 compatible = "qcom,dwc3-hs-usb-phy";
841 reg = <0x110f8800 0x30>;
842 clocks = <&gcc USB30_0_UTMI_CLK>;
843 clock-names = "ref";
844 #phy-cells = <0>;
845
846 status = "disabled";
847 };
848
849 ss_phy_0: phy@110f8830 {
850 compatible = "qcom,dwc3-ss-usb-phy";
851 reg = <0x110f8830 0x30>;
852 clocks = <&gcc USB30_0_MASTER_CLK>;
853 clock-names = "ref";
854 #phy-cells = <0>;
855
856 status = "disabled";
857 };
858
859 usb3_0: usb30@0 {
860 compatible = "qcom,dwc3";
861 #address-cells = <1>;
862 #size-cells = <1>;
863 clocks = <&gcc USB30_0_MASTER_CLK>;
864 clock-names = "core";
865
866 syscon-tcsr = <&tcsr 0xb0 1>;
867
868 ranges;
869
870 status = "disabled";
871 resets = <&gcc USB30_0_MASTER_RESET>;
872 reset-names = "usb30_mstr_rst";
873
874 dwc3@11000000 {
875 compatible = "snps,dwc3";
876 reg = <0x11000000 0xcd00>;
877 interrupts = <0 110 0x4>;
878 phys = <&hs_phy_0>, <&ss_phy_0>;
879 phy-names = "usb2-phy", "usb3-phy";
880 dr_mode = "host";
881 snps,dis_u3_susphy_quirk;
882 };
883 };
884
885 usb3_1: usb30@1 {
886 compatible = "qcom,dwc3";
887 #address-cells = <1>;
888 #size-cells = <1>;
889 clocks = <&gcc USB30_1_MASTER_CLK>;
890 clock-names = "core";
891
892 syscon-tcsr = <&tcsr 0xb0 0>;
893
894 ranges;
895
896 status = "disabled";
897
898 dwc3@10000000 {
899 compatible = "snps,dwc3";
900 reg = <0x10000000 0xcd00>;
901 interrupts = <0 205 0x4>;
902 phys = <&hs_phy_1>, <&ss_phy_1>;
903 phy-names = "usb2-phy", "usb3-phy";
904 dr_mode = "host";
905 snps,dis_u3_susphy_quirk;
906 };
907 };
908
909 pcie0: pci@1b500000 {
910 compatible = "qcom,pcie-v0";
911 reg = <0x1b500000 0x1000
912 0x1b502000 0x80
913 0x1b600000 0x100
914 0x0ff00000 0x100000>;
915 reg-names = "dbi", "elbi", "parf", "config";
916 device_type = "pci";
917 linux,pci-domain = <0>;
918 bus-range = <0x00 0xff>;
919 num-lanes = <1>;
920 #address-cells = <3>;
921 #size-cells = <2>;
922
923 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
924 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
925
926 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
927 interrupt-names = "msi";
928 #interrupt-cells = <1>;
929 interrupt-map-mask = <0 0 0 0x7>;
930 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
931 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
932 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
933 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934
935 clocks = <&gcc PCIE_A_CLK>,
936 <&gcc PCIE_H_CLK>,
937 <&gcc PCIE_PHY_CLK>,
938 <&gcc PCIE_AUX_CLK>,
939 <&gcc PCIE_ALT_REF_CLK>;
940 clock-names = "core", "iface", "phy", "aux", "ref";
941
942 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
943 assigned-clock-rates = <100000000>;
944
945 resets = <&gcc PCIE_ACLK_RESET>,
946 <&gcc PCIE_HCLK_RESET>,
947 <&gcc PCIE_POR_RESET>,
948 <&gcc PCIE_PCI_RESET>,
949 <&gcc PCIE_PHY_RESET>,
950 <&gcc PCIE_EXT_RESET>;
951 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
952
953 pinctrl-0 = <&pcie0_pins>;
954 pinctrl-names = "default";
955
956 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
957
958 status = "disabled";
959 };
960
961 pcie1: pci@1b700000 {
962 compatible = "qcom,pcie-v0";
963 reg = <0x1b700000 0x1000
964 0x1b702000 0x80
965 0x1b800000 0x100
966 0x31f00000 0x100000>;
967 reg-names = "dbi", "elbi", "parf", "config";
968 device_type = "pci";
969 linux,pci-domain = <1>;
970 bus-range = <0x00 0xff>;
971 num-lanes = <1>;
972 #address-cells = <3>;
973 #size-cells = <2>;
974
975 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
976 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
977
978 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
979 interrupt-names = "msi";
980 #interrupt-cells = <1>;
981 interrupt-map-mask = <0 0 0 0x7>;
982 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
983 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
984 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
985 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
986
987 clocks = <&gcc PCIE_1_A_CLK>,
988 <&gcc PCIE_1_H_CLK>,
989 <&gcc PCIE_1_PHY_CLK>,
990 <&gcc PCIE_1_AUX_CLK>,
991 <&gcc PCIE_1_ALT_REF_CLK>;
992 clock-names = "core", "iface", "phy", "aux", "ref";
993
994 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
995 assigned-clock-rates = <100000000>;
996
997 resets = <&gcc PCIE_1_ACLK_RESET>,
998 <&gcc PCIE_1_HCLK_RESET>,
999 <&gcc PCIE_1_POR_RESET>,
1000 <&gcc PCIE_1_PCI_RESET>,
1001 <&gcc PCIE_1_PHY_RESET>,
1002 <&gcc PCIE_1_EXT_RESET>;
1003 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1004
1005 pinctrl-0 = <&pcie1_pins>;
1006 pinctrl-names = "default";
1007
1008 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1009
1010 status = "disabled";
1011 };
1012
1013 pcie2: pci@1b900000 {
1014 compatible = "qcom,pcie-v0";
1015 reg = <0x1b900000 0x1000
1016 0x1b902000 0x80
1017 0x1ba00000 0x100
1018 0x35f00000 0x100000>;
1019 reg-names = "dbi", "elbi", "parf", "config";
1020 device_type = "pci";
1021 linux,pci-domain = <2>;
1022 bus-range = <0x00 0xff>;
1023 num-lanes = <1>;
1024 #address-cells = <3>;
1025 #size-cells = <2>;
1026
1027 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1028 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1029
1030 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
1031 interrupt-names = "msi";
1032 #interrupt-cells = <1>;
1033 interrupt-map-mask = <0 0 0 0x7>;
1034 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1035 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1036 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1037 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1038
1039 clocks = <&gcc PCIE_2_A_CLK>,
1040 <&gcc PCIE_2_H_CLK>,
1041 <&gcc PCIE_2_PHY_CLK>,
1042 <&gcc PCIE_2_AUX_CLK>,
1043 <&gcc PCIE_2_ALT_REF_CLK>;
1044 clock-names = "core", "iface", "phy", "aux", "ref";
1045
1046 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1047 assigned-clock-rates = <100000000>;
1048
1049 resets = <&gcc PCIE_2_ACLK_RESET>,
1050 <&gcc PCIE_2_HCLK_RESET>,
1051 <&gcc PCIE_2_POR_RESET>,
1052 <&gcc PCIE_2_PCI_RESET>,
1053 <&gcc PCIE_2_PHY_RESET>,
1054 <&gcc PCIE_2_EXT_RESET>;
1055 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1056
1057 pinctrl-0 = <&pcie2_pins>;
1058 pinctrl-names = "default";
1059
1060 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1061
1062 status = "disabled";
1063 };
1064
1065 adm_dma: dma@18300000 {
1066 compatible = "qcom,adm";
1067 reg = <0x18300000 0x100000>;
1068 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
1069 #dma-cells = <1>;
1070
1071 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1072 clock-names = "core", "iface";
1073
1074 resets = <&gcc ADM0_RESET>,
1075 <&gcc ADM0_PBUS_RESET>,
1076 <&gcc ADM0_C0_RESET>,
1077 <&gcc ADM0_C1_RESET>,
1078 <&gcc ADM0_C2_RESET>;
1079 reset-names = "clk", "pbus", "c0", "c1", "c2";
1080 qcom,ee = <0>;
1081
1082 status = "disabled";
1083 };
1084
1085 nand@1ac00000 {
1086 compatible = "qcom,ebi2-nandc";
1087 reg = <0x1ac00000 0x800>;
1088
1089 clocks = <&gcc EBI2_CLK>,
1090 <&gcc EBI2_AON_CLK>;
1091 clock-names = "core", "aon";
1092
1093 dmas = <&adm_dma 3>;
1094 dma-names = "rxtx";
1095 qcom,cmd-crci = <15>;
1096 qcom,data-crci = <3>;
1097
1098 status = "disabled";
1099 };
1100
1101 nss_common: syscon@03000000 {
1102 compatible = "syscon";
1103 reg = <0x03000000 0x0000FFFF>;
1104 };
1105
1106 qsgmii_csr: syscon@1bb00000 {
1107 compatible = "syscon";
1108 reg = <0x1bb00000 0x000001FF>;
1109 };
1110
1111 gmac0: ethernet@37000000 {
1112 device_type = "network";
1113 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1114 reg = <0x37000000 0x200000>;
1115 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1116 interrupt-names = "macirq";
1117
1118 qcom,nss-common = <&nss_common>;
1119 qcom,qsgmii-csr = <&qsgmii_csr>;
1120
1121 clocks = <&gcc GMAC_CORE1_CLK>;
1122 clock-names = "stmmaceth";
1123
1124 resets = <&gcc GMAC_CORE1_RESET>;
1125 reset-names = "stmmaceth";
1126
1127 status = "disabled";
1128 };
1129
1130 gmac1: ethernet@37200000 {
1131 device_type = "network";
1132 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1133 reg = <0x37200000 0x200000>;
1134 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "macirq";
1136
1137 qcom,nss-common = <&nss_common>;
1138 qcom,qsgmii-csr = <&qsgmii_csr>;
1139
1140 clocks = <&gcc GMAC_CORE2_CLK>;
1141 clock-names = "stmmaceth";
1142
1143 resets = <&gcc GMAC_CORE2_RESET>;
1144 reset-names = "stmmaceth";
1145
1146 status = "disabled";
1147 };
1148
1149 gmac2: ethernet@37400000 {
1150 device_type = "network";
1151 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1152 reg = <0x37400000 0x200000>;
1153 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1154 interrupt-names = "macirq";
1155
1156 qcom,nss-common = <&nss_common>;
1157 qcom,qsgmii-csr = <&qsgmii_csr>;
1158
1159 clocks = <&gcc GMAC_CORE3_CLK>;
1160 clock-names = "stmmaceth";
1161
1162 resets = <&gcc GMAC_CORE3_RESET>;
1163 reset-names = "stmmaceth";
1164
1165 status = "disabled";
1166 };
1167
1168 gmac3: ethernet@37600000 {
1169 device_type = "network";
1170 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1171 reg = <0x37600000 0x200000>;
1172 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1173 interrupt-names = "macirq";
1174
1175 qcom,nss-common = <&nss_common>;
1176 qcom,qsgmii-csr = <&qsgmii_csr>;
1177
1178 clocks = <&gcc GMAC_CORE4_CLK>;
1179 clock-names = "stmmaceth";
1180
1181 resets = <&gcc GMAC_CORE4_RESET>;
1182 reset-names = "stmmaceth";
1183
1184 status = "disabled";
1185 };
1186
1187 /* Temporary fixed regulator */
1188 vsdcc_fixed: vsdcc-regulator {
1189 compatible = "regulator-fixed";
1190 regulator-name = "SDCC Power";
1191 regulator-min-microvolt = <3300000>;
1192 regulator-max-microvolt = <3300000>;
1193 regulator-always-on;
1194 };
1195
1196 sdcc1bam:dma@12402000 {
1197 compatible = "qcom,bam-v1.3.0";
1198 reg = <0x12402000 0x8000>;
1199 interrupts = <0 98 0>;
1200 clocks = <&gcc SDC1_H_CLK>;
1201 clock-names = "bam_clk";
1202 #dma-cells = <1>;
1203 qcom,ee = <0>;
1204 };
1205
1206 sdcc3bam:dma@12182000 {
1207 compatible = "qcom,bam-v1.3.0";
1208 reg = <0x12182000 0x8000>;
1209 interrupts = <0 96 0>;
1210 clocks = <&gcc SDC3_H_CLK>;
1211 clock-names = "bam_clk";
1212 #dma-cells = <1>;
1213 qcom,ee = <0>;
1214 };
1215
1216 amba {
1217 compatible = "arm,amba-bus";
1218 #address-cells = <1>;
1219 #size-cells = <1>;
1220 ranges;
1221 sdcc1: sdcc@12400000 {
1222 status = "disabled";
1223 compatible = "arm,pl18x", "arm,primecell";
1224 arm,primecell-periphid = <0x00051180>;
1225 reg = <0x12400000 0x2000>;
1226 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "cmd_irq";
1228 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1229 clock-names = "mclk", "apb_pclk";
1230 bus-width = <8>;
1231 max-frequency = <96000000>;
1232 non-removable;
1233 cap-sd-highspeed;
1234 cap-mmc-highspeed;
1235 mmc-ddr-1_8v;
1236 vmmc-supply = <&vsdcc_fixed>;
1237 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1238 dma-names = "tx", "rx";
1239 };
1240
1241 sdcc3: sdcc@12180000 {
1242 compatible = "arm,pl18x", "arm,primecell";
1243 arm,primecell-periphid = <0x00051180>;
1244 status = "disabled";
1245 reg = <0x12180000 0x2000>;
1246 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1247 interrupt-names = "cmd_irq";
1248 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1249 clock-names = "mclk", "apb_pclk";
1250 bus-width = <8>;
1251 cap-sd-highspeed;
1252 cap-mmc-highspeed;
1253 max-frequency = <192000000>;
1254 #mmc-ddr-1_8v;
1255 sd-uhs-sdr104;
1256 sd-uhs-ddr50;
1257 vqmmc-supply = <&vsdcc_fixed>;
1258 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1259 dma-names = "tx", "rx";
1260 };
1261 };
1262 };
1263
1264 sfpb_mutex: sfpb-mutex {
1265 compatible = "qcom,sfpb-mutex";
1266 syscon = <&sfpb_mutex_block 4 4>;
1267
1268 #hwlock-cells = <1>;
1269 };
1270
1271 smem {
1272 compatible = "qcom,smem";
1273 memory-region = <&smem>;
1274 hwlocks = <&sfpb_mutex 3>;
1275 };
1276 };
OpenWrt Source Repository