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ipq806x: add CPU idle states
[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8065";
15 compatible = "qcom,ipq8065", "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 qcom,imem = <&imem>;
33 clock-latency = <100000>;
34 cpu-supply = <&smb208_s2a>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
38 #cooling-cells = <2>;
39 cpu-idle-states = <&CPU_SPC>;
40 };
41
42 cpu1: cpu@1 {
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
45 device_type = "cpu";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 qcom,acc = <&acc1>;
49 qcom,saw = <&saw1>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 qcom,imem = <&imem>;
53 clock-latency = <100000>;
54 cpu-supply = <&smb208_s2b>;
55 cooling-min-state = <0>;
56 cooling-max-state = <10>;
57 #cooling-cells = <2>;
58 cpu-idle-states = <&CPU_SPC>;
59 };
60
61 L2: l2-cache {
62 compatible = "cache";
63 cache-level = <2>;
64 qcom,saw = <&saw_l2>;
65 };
66
67 qcom,l2 {
68 qcom,l2-rates = <384000000 1000000000 1200000000>;
69 };
70
71 idle-states {
72 CPU_SPC: spc {
73 compatible = "qcom,idle-state-spc",
74 "arm,idle-state";
75 entry-latency-us = <400>;
76 exit-latency-us = <900>;
77 min-residency-us = <3000>;
78 };
79 };
80 };
81
82 cpu-pmu {
83 compatible = "qcom,krait-pmu";
84 interrupts = <1 10 0x304>;
85 };
86
87 reserved-memory {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 nss@40000000 {
93 reg = <0x40000000 0x1000000>;
94 no-map;
95 };
96
97 smem: smem@41000000 {
98 reg = <0x41000000 0x200000>;
99 no-map;
100 };
101 };
102
103 clocks {
104 sleep_clk: sleep_clk {
105 compatible = "fixed-clock";
106 clock-frequency = <32768>;
107 #clock-cells = <0>;
108 };
109 };
110
111 kraitcc: clock-controller {
112 compatible = "qcom,krait-cc-v1";
113 #clock-cells = <1>;
114 };
115
116 qcom,pvs {
117 qcom,pvs-format-a;
118 qcom,speed0-pvs0-bin-v0 =
119 < 1725000000 1262500 >,
120 < 1400000000 1175000 >,
121 < 1000000000 1100000 >,
122 < 800000000 1050000 >,
123 < 600000000 1000000 >,
124 < 384000000 975000 >;
125 qcom,speed0-pvs1-bin-v0 =
126 < 1725000000 1262500 >,
127 < 1400000000 1175000 >,
128 < 1000000000 1100000 >,
129 < 800000000 1050000 >,
130 < 600000000 1000000 >,
131 < 384000000 950000 >;
132 qcom,speed0-pvs2-bin-v0 =
133 < 1725000000 1200000 >,
134 < 1400000000 1125000 >,
135 < 1000000000 1050000 >,
136 < 800000000 1000000 >,
137 < 600000000 950000 >,
138 < 384000000 925000 >;
139 qcom,speed0-pvs3-bin-v0 =
140 < 1725000000 1175000 >,
141 < 1400000000 1100000 >,
142 < 1000000000 1025000 >,
143 < 800000000 975000 >,
144 < 600000000 925000 >,
145 < 384000000 900000 >;
146 qcom,speed0-pvs4-bin-v0 =
147 < 1725000000 1150000 >,
148 < 1400000000 1075000 >,
149 < 1000000000 1000000 >,
150 < 800000000 950000 >,
151 < 600000000 900000 >,
152 < 384000000 875000 >;
153 qcom,speed0-pvs5-bin-v0 =
154 < 1725000000 1100000 >,
155 < 1400000000 1025000 >,
156 < 1000000000 950000 >,
157 < 800000000 900000 >,
158 < 600000000 850000 >,
159 < 384000000 825000 >;
160 qcom,speed0-pvs6-bin-v0 =
161 < 1725000000 1050000 >,
162 < 1400000000 975000 >,
163 < 1000000000 900000 >,
164 < 800000000 850000 >,
165 < 600000000 800000 >,
166 < 384000000 775000 >;
167 };
168
169 soc: soc {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges;
173 compatible = "simple-bus";
174
175 lpass@28100000 {
176 compatible = "qcom,lpass-cpu";
177 status = "disabled";
178 clocks = <&lcc AHBIX_CLK>,
179 <&lcc MI2S_OSR_CLK>,
180 <&lcc MI2S_BIT_CLK>;
181 clock-names = "ahbix-clk",
182 "mi2s-osr-clk",
183 "mi2s-bit-clk";
184 interrupts = <0 85 1>;
185 interrupt-names = "lpass-irq-lpaif";
186 reg = <0x28100000 0x10000>;
187 reg-names = "lpass-lpaif";
188 };
189
190 imem: memory@700000 {
191 compatible = "qcom,qfprom", "syscon";
192 reg = <0x00700000 0x1000>;
193 #address-cells = <1>;
194 #size-cells = <1>;
195 stride = <1>;
196 ranges = <0x0 0x00700000 0x1000>;
197 };
198
199 rpm@108000 {
200 compatible = "qcom,rpm-ipq8064";
201 reg = <0x108000 0x1000>;
202 qcom,ipc = <&l2cc 0x8 2>;
203
204 interrupts = <0 19 0>,
205 <0 21 0>,
206 <0 22 0>;
207 interrupt-names = "ack",
208 "err",
209 "wakeup";
210
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 smb208_regulators {
215 compatible = "qcom,rpm-smb208-regulators";
216
217 smb208_s1a: s1a {
218 regulator-min-microvolt = <1050000>;
219 regulator-max-microvolt = <1150000>;
220 qcom,switch-mode-frequency = <1200000>;
221 };
222
223 smb208_s1b: s1b {
224 regulator-min-microvolt = <1050000>;
225 regulator-max-microvolt = <1150000>;
226 qcom,switch-mode-frequency = <1200000>;
227 };
228
229 smb208_s2a: s2a {
230 regulator-min-microvolt = < 800000>;
231 regulator-max-microvolt = <1275000>;
232 qcom,switch-mode-frequency = <1200000>;
233 };
234
235 smb208_s2b: s2b {
236 regulator-min-microvolt = < 800000>;
237 regulator-max-microvolt = <1275000>;
238 qcom,switch-mode-frequency = <1200000>;
239 };
240 };
241 };
242
243 rng@1a500000 {
244 compatible = "qcom,prng";
245 reg = <0x1a500000 0x200>;
246 clocks = <&gcc PRNG_CLK>;
247 clock-names = "core";
248 };
249
250 qcom,msm-imem@2A03F000 {
251 compatible = "qcom,msm-imem";
252 reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
253 ranges = <0x0 0x2A03F000 0x1000>;
254 #address-cells = <1>;
255 #size-cells = <1>;
256
257 download_mode@0 {
258 compatible = "qcom,msm-imem-download_mode";
259 reg = <0x0 8>;
260 };
261
262 restart_reason@65c {
263 compatible = "qcom,msm-imem-restart_reason";
264 reg = <0x65c 4>;
265 };
266
267 l2_dump_offset@14 {
268 compatible = "qcom,msm-imem-l2_dump_offset";
269 reg = <0x14 8>;
270 };
271 };
272
273 qcom_pinmux: pinmux@800000 {
274 compatible = "qcom,ipq8064-pinctrl";
275 reg = <0x800000 0x4000>;
276
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 interrupts = <0 16 0x4>;
282
283 pcie0_pins: pcie0_pinmux {
284 mux {
285 pins = "gpio3";
286 function = "pcie1_rst";
287 drive-strength = <12>;
288 bias-disable;
289 };
290 };
291
292 pcie1_pins: pcie1_pinmux {
293 mux {
294 pins = "gpio48";
295 function = "pcie2_rst";
296 drive-strength = <12>;
297 bias-disable;
298 };
299 };
300
301 pcie2_pins: pcie2_pinmux {
302 mux {
303 pins = "gpio63";
304 function = "pcie3_rst";
305 drive-strength = <12>;
306 bias-disable;
307 };
308 };
309 };
310
311 intc: interrupt-controller@2000000 {
312 compatible = "qcom,msm-qgic2";
313 interrupt-controller;
314 #interrupt-cells = <3>;
315 reg = <0x02000000 0x1000>,
316 <0x02002000 0x1000>;
317 };
318
319 timer@200a000 {
320 compatible = "qcom,kpss-timer", "qcom,msm-timer";
321 interrupts = <1 1 0x301>,
322 <1 2 0x301>,
323 <1 3 0x301>,
324 <1 4 0x301>,
325 <1 5 0x301>;
326 reg = <0x0200a000 0x100>;
327 clock-frequency = <25000000>,
328 <32768>;
329 clocks = <&sleep_clk>;
330 clock-names = "sleep";
331 cpu-offset = <0x80000>;
332 };
333
334 acc0: clock-controller@2088000 {
335 compatible = "qcom,kpss-acc-v1";
336 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
337 clock-output-names = "acpu0_aux";
338 };
339
340 acc1: clock-controller@2098000 {
341 compatible = "qcom,kpss-acc-v1";
342 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
343 clock-output-names = "acpu1_aux";
344 };
345
346 l2cc: clock-controller@2011000 {
347 compatible = "qcom,kpss-gcc", "syscon";
348 reg = <0x2011000 0x1000>;
349 clock-output-names = "acpu_l2_aux";
350 };
351
352 saw0: regulator@2089000 {
353 compatible = "qcom,saw2", "syscon";
354 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
355 regulator;
356 };
357
358 saw1: regulator@2099000 {
359 compatible = "qcom,saw2", "syscon";
360 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
361 regulator;
362 };
363
364 saw_l2: regulator@02012000 {
365 compatible = "qcom,saw2", "syscon";
366 reg = <0x02012000 0x1000>;
367 regulator;
368 };
369
370 sic_non_secure: sic-non-secure@12100000 {
371 compatible = "syscon";
372 reg = <0x12100000 0x10000>;
373 };
374
375 gsbi1: gsbi@12440000 {
376 compatible = "qcom,gsbi-v1.0.0";
377 cell-index = <1>;
378 reg = <0x12440000 0x100>;
379 clocks = <&gcc GSBI1_H_CLK>;
380 clock-names = "iface";
381 #address-cells = <1>;
382 #size-cells = <1>;
383 ranges;
384 status = "disabled";
385
386 syscon-tcsr = <&tcsr>;
387
388 uart1: serial@12450000 {
389 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
390 reg = <0x12450000 0x1000>,
391 <0x12440000 0x1000>;
392 interrupts = <0 193 0x0>;
393 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
394 clock-names = "core", "iface";
395 status = "disabled";
396 };
397
398 i2c@12460000 {
399 compatible = "qcom,i2c-qup-v1.1.1";
400 reg = <0x12460000 0x1000>;
401 interrupts = <0 194 0>;
402
403 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
404 clock-names = "core", "iface";
405 status = "disabled";
406
407 #address-cells = <1>;
408 #size-cells = <0>;
409 };
410
411 };
412
413 gsbi2: gsbi@12480000 {
414 compatible = "qcom,gsbi-v1.0.0";
415 cell-index = <2>;
416 reg = <0x12480000 0x100>;
417 clocks = <&gcc GSBI2_H_CLK>;
418 clock-names = "iface";
419 #address-cells = <1>;
420 #size-cells = <1>;
421 ranges;
422 status = "disabled";
423
424 syscon-tcsr = <&tcsr>;
425
426 uart2: serial@12490000 {
427 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
428 reg = <0x12490000 0x1000>,
429 <0x12480000 0x1000>;
430 interrupts = <0 195 0x0>;
431 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
432 clock-names = "core", "iface";
433 status = "disabled";
434 };
435
436 i2c@124a0000 {
437 compatible = "qcom,i2c-qup-v1.1.1";
438 reg = <0x124a0000 0x1000>;
439 interrupts = <0 196 0>;
440
441 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
442 clock-names = "core", "iface";
443 status = "disabled";
444
445 #address-cells = <1>;
446 #size-cells = <0>;
447 };
448
449 };
450
451 gsbi4: gsbi@16300000 {
452 compatible = "qcom,gsbi-v1.0.0";
453 cell-index = <4>;
454 reg = <0x16300000 0x100>;
455 clocks = <&gcc GSBI4_H_CLK>;
456 clock-names = "iface";
457 #address-cells = <1>;
458 #size-cells = <1>;
459 ranges;
460 status = "disabled";
461
462 syscon-tcsr = <&tcsr>;
463
464 uart4: serial@16340000 {
465 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
466 reg = <0x16340000 0x1000>,
467 <0x16300000 0x1000>;
468 interrupts = <0 152 0x0>;
469 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
470 clock-names = "core", "iface";
471 status = "disabled";
472 };
473
474 i2c@16380000 {
475 compatible = "qcom,i2c-qup-v1.1.1";
476 reg = <0x16380000 0x1000>;
477 interrupts = <0 153 0>;
478
479 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
480 clock-names = "core", "iface";
481 status = "disabled";
482
483 #address-cells = <1>;
484 #size-cells = <0>;
485 };
486 };
487
488 gsbi5: gsbi@1a200000 {
489 compatible = "qcom,gsbi-v1.0.0";
490 cell-index = <5>;
491 reg = <0x1a200000 0x100>;
492 clocks = <&gcc GSBI5_H_CLK>;
493 clock-names = "iface";
494 #address-cells = <1>;
495 #size-cells = <1>;
496 ranges;
497 status = "disabled";
498
499 syscon-tcsr = <&tcsr>;
500
501 uart5: serial@1a240000 {
502 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
503 reg = <0x1a240000 0x1000>,
504 <0x1a200000 0x1000>;
505 interrupts = <0 154 0x0>;
506 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
507 clock-names = "core", "iface";
508 status = "disabled";
509 };
510
511 i2c@1a280000 {
512 compatible = "qcom,i2c-qup-v1.1.1";
513 reg = <0x1a280000 0x1000>;
514 interrupts = <0 155 0>;
515
516 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
517 clock-names = "core", "iface";
518 status = "disabled";
519
520 #address-cells = <1>;
521 #size-cells = <0>;
522 };
523
524 spi@1a280000 {
525 compatible = "qcom,spi-qup-v1.1.1";
526 reg = <0x1a280000 0x1000>;
527 interrupts = <0 155 0>;
528
529 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
530 clock-names = "core", "iface";
531 status = "disabled";
532
533 #address-cells = <1>;
534 #size-cells = <0>;
535 };
536 };
537
538 gsbi6: gsbi@16500000 {
539 compatible = "qcom,gsbi-v1.0.0";
540 cell-index = <6>;
541 reg = <0x16500000 0x100>;
542 clocks = <&gcc GSBI6_H_CLK>;
543 clock-names = "iface";
544 #address-cells = <1>;
545 #size-cells = <1>;
546 ranges;
547 status = "disabled";
548
549 syscon-tcsr = <&tcsr>;
550
551 uart6: serial@16540000 {
552 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
553 reg = <0x16540000 0x1000>,
554 <0x16500000 0x1000>;
555 interrupts = <0 156 0x0>;
556 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
557 clock-names = "core", "iface";
558 status = "disabled";
559 };
560
561 i2c@16580000 {
562 compatible = "qcom,i2c-qup-v1.1.1";
563 reg = <0x16580000 0x1000>;
564 interrupts = <0 157 0>;
565
566 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
567 clock-names = "core", "iface";
568 status = "disabled";
569
570 #address-cells = <1>;
571 #size-cells = <0>;
572 };
573
574 spi@16580000 {
575 compatible = "qcom,spi-qup-v1.1.1";
576 reg = <0x16580000 0x1000>;
577 interrupts = <0 157 0>;
578
579 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
580 clock-names = "core", "iface";
581 status = "disabled";
582
583 #address-cells = <1>;
584 #size-cells = <0>;
585 };
586 };
587
588 gsbi7: gsbi@16600000 {
589 compatible = "qcom,gsbi-v1.0.0";
590 cell-index = <7>;
591 reg = <0x16600000 0x100>;
592 clocks = <&gcc GSBI7_H_CLK>;
593 clock-names = "iface";
594 #address-cells = <1>;
595 #size-cells = <1>;
596 ranges;
597 status = "disabled";
598
599 syscon-tcsr = <&tcsr>;
600
601 uart7: serial@16640000 {
602 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
603 reg = <0x16640000 0x1000>,
604 <0x16600000 0x1000>;
605 interrupts = <0 158 0x0>;
606 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
607 clock-names = "core", "iface";
608 status = "disabled";
609 };
610
611 i2c@16680000 {
612 compatible = "qcom,i2c-qup-v1.1.1";
613 reg = <0x16680000 0x1000>;
614 interrupts = <0 159 0>;
615
616 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
617 clock-names = "core", "iface";
618 status = "disabled";
619
620 #address-cells = <1>;
621 #size-cells = <0>;
622 };
623
624 };
625
626 sata_phy: sata-phy@1b400000 {
627 compatible = "qcom,ipq806x-sata-phy";
628 reg = <0x1b400000 0x200>;
629
630 clocks = <&gcc SATA_PHY_CFG_CLK>;
631 clock-names = "cfg";
632
633 #phy-cells = <0>;
634 status = "disabled";
635 };
636
637 sata@29000000 {
638 compatible = "qcom,ipq806x-ahci", "generic-ahci";
639 reg = <0x29000000 0x180>;
640
641 interrupts = <0 209 0x0>;
642
643 clocks = <&gcc SFAB_SATA_S_H_CLK>,
644 <&gcc SATA_H_CLK>,
645 <&gcc SATA_A_CLK>,
646 <&gcc SATA_RXOOB_CLK>,
647 <&gcc SATA_PMALIVE_CLK>;
648 clock-names = "slave_face", "iface", "core",
649 "rxoob", "pmalive";
650
651 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
652 assigned-clock-rates = <100000000>, <100000000>;
653
654 phys = <&sata_phy>;
655 phy-names = "sata-phy";
656 status = "disabled";
657 };
658
659 qcom,ssbi@500000 {
660 compatible = "qcom,ssbi";
661 reg = <0x00500000 0x1000>;
662 qcom,controller-type = "pmic-arbiter";
663 };
664
665 gcc: clock-controller@900000 {
666 compatible = "qcom,gcc-ipq8064";
667 reg = <0x00900000 0x4000>;
668 #clock-cells = <1>;
669 #reset-cells = <1>;
670 #power-domain-cells = <1>;
671 };
672
673 lcc: clock-controller@28000000 {
674 compatible = "qcom,lcc-ipq8064";
675 reg = <0x28000000 0x1000>;
676 #clock-cells = <1>;
677 #reset-cells = <1>;
678 };
679
680 tcsr: syscon@1a400000 {
681 compatible = "qcom,tcsr-ipq8064", "syscon";
682 reg = <0x1a400000 0x100>;
683 };
684
685 tsens: tsens-ipq806x {
686 compatible = "qcom,ipq806x-tsens";
687 reg = <0x900000 0x3678>, <0x700000 0x420>;
688 reg-names = "tsens_physical", "tsens_eeprom_physical";
689 interrupts = <0 178 0>;
690 qcom,sensors = <11>;
691 qcom,tsens_factor = <1000>;
692 qcom,slope = <1176 1176 1154 1176 1111 1132 1132 1199 1132 1199 1132>;
693 };
694
695 qcom,msm-thermal {
696 compatible = "qcom,msm-thermal";
697 qcom,sensor-id = <0>;
698 qcom,poll-ms = <250>;
699 qcom,limit-temp = <105>;
700 qcom,temp-hysteresis = <10>;
701 qcom,freq-step = <2>;
702 qcom,core-limit-temp = <115>;
703 qcom,core-temp-hysteresis = <10>;
704 qcom,core-control-mask = <0xe>;
705 };
706
707 sfpb_mutex_block: syscon@1200600 {
708 compatible = "syscon";
709 reg = <0x01200600 0x100>;
710 };
711
712 hs_phy_1: phy@100f8800 {
713 compatible = "qcom,dwc3-hs-usb-phy";
714 reg = <0x100f8800 0x30>;
715 clocks = <&gcc USB30_1_UTMI_CLK>;
716 clock-names = "ref";
717 #phy-cells = <0>;
718
719 status = "disabled";
720 };
721
722 ss_phy_1: phy@100f8830 {
723 compatible = "qcom,dwc3-ss-usb-phy";
724 reg = <0x100f8830 0x30>;
725 clocks = <&gcc USB30_1_MASTER_CLK>;
726 clock-names = "ref";
727 #phy-cells = <0>;
728
729 status = "disabled";
730 };
731
732 hs_phy_0: phy@110f8800 {
733 compatible = "qcom,dwc3-hs-usb-phy";
734 reg = <0x110f8800 0x30>;
735 clocks = <&gcc USB30_0_UTMI_CLK>;
736 clock-names = "ref";
737 #phy-cells = <0>;
738
739 status = "disabled";
740 };
741
742 ss_phy_0: phy@110f8830 {
743 compatible = "qcom,dwc3-ss-usb-phy";
744 reg = <0x110f8830 0x30>;
745 clocks = <&gcc USB30_0_MASTER_CLK>;
746 clock-names = "ref";
747 #phy-cells = <0>;
748
749 status = "disabled";
750 };
751
752 usb3_0: usb30@0 {
753 compatible = "qcom,dwc3";
754 #address-cells = <1>;
755 #size-cells = <1>;
756 clocks = <&gcc USB30_0_MASTER_CLK>;
757 clock-names = "core";
758
759 ranges;
760
761 status = "disabled";
762 resets = <&gcc USB30_0_MASTER_RESET>;
763 reset-names = "usb30_mstr_rst";
764
765 dwc3@11000000 {
766 compatible = "snps,dwc3";
767 reg = <0x11000000 0xcd00>;
768 interrupts = <0 110 0x4>;
769 phys = <&hs_phy_0>, <&ss_phy_0>;
770 phy-names = "usb2-phy", "usb3-phy";
771 tx-fifo-resize;
772 dr_mode = "host";
773 };
774 };
775
776 usb3_1: usb30@1 {
777 compatible = "qcom,dwc3";
778 #address-cells = <1>;
779 #size-cells = <1>;
780 clocks = <&gcc USB30_1_MASTER_CLK>;
781 clock-names = "core";
782
783 ranges;
784
785 status = "disabled";
786
787 dwc3@10000000 {
788 compatible = "snps,dwc3";
789 reg = <0x10000000 0xcd00>;
790 interrupts = <0 205 0x4>;
791 phys = <&hs_phy_1>, <&ss_phy_1>;
792 phy-names = "usb2-phy", "usb3-phy";
793 tx-fifo-resize;
794 dr_mode = "host";
795 };
796 };
797
798 pcie0: pci@1b500000 {
799 compatible = "qcom,pcie-v0";
800 reg = <0x1b500000 0x1000
801 0x1b502000 0x80
802 0x1b600000 0x100
803 0x0ff00000 0x100000>;
804 reg-names = "dbi", "elbi", "parf", "config";
805 device_type = "pci";
806 linux,pci-domain = <0>;
807 bus-range = <0x00 0xff>;
808 num-lanes = <1>;
809 #address-cells = <3>;
810 #size-cells = <2>;
811
812 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
813 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
814
815 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
816 interrupt-names = "msi";
817 #interrupt-cells = <1>;
818 interrupt-map-mask = <0 0 0 0x7>;
819 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
820 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
821 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
822 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
823
824 clocks = <&gcc PCIE_A_CLK>,
825 <&gcc PCIE_H_CLK>,
826 <&gcc PCIE_PHY_CLK>,
827 <&gcc PCIE_AUX_CLK>,
828 <&gcc PCIE_ALT_REF_CLK>;
829 clock-names = "core", "iface", "phy", "aux", "ref";
830
831 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
832 assigned-clock-rates = <100000000>;
833
834 resets = <&gcc PCIE_ACLK_RESET>,
835 <&gcc PCIE_HCLK_RESET>,
836 <&gcc PCIE_POR_RESET>,
837 <&gcc PCIE_PCI_RESET>,
838 <&gcc PCIE_PHY_RESET>,
839 <&gcc PCIE_EXT_RESET>;
840 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
841
842 pinctrl-0 = <&pcie0_pins>;
843 pinctrl-names = "default";
844
845 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
846
847 status = "disabled";
848 };
849
850 pcie1: pci@1b700000 {
851 compatible = "qcom,pcie-v0";
852 reg = <0x1b700000 0x1000
853 0x1b702000 0x80
854 0x1b800000 0x100
855 0x31f00000 0x100000>;
856 reg-names = "dbi", "elbi", "parf", "config";
857 device_type = "pci";
858 linux,pci-domain = <1>;
859 bus-range = <0x00 0xff>;
860 num-lanes = <1>;
861 #address-cells = <3>;
862 #size-cells = <2>;
863
864 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
865 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
866
867 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
868 interrupt-names = "msi";
869 #interrupt-cells = <1>;
870 interrupt-map-mask = <0 0 0 0x7>;
871 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
872 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
873 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
874 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
875
876 clocks = <&gcc PCIE_1_A_CLK>,
877 <&gcc PCIE_1_H_CLK>,
878 <&gcc PCIE_1_PHY_CLK>,
879 <&gcc PCIE_1_AUX_CLK>,
880 <&gcc PCIE_1_ALT_REF_CLK>;
881 clock-names = "core", "iface", "phy", "aux", "ref";
882
883 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
884 assigned-clock-rates = <100000000>;
885
886 resets = <&gcc PCIE_1_ACLK_RESET>,
887 <&gcc PCIE_1_HCLK_RESET>,
888 <&gcc PCIE_1_POR_RESET>,
889 <&gcc PCIE_1_PCI_RESET>,
890 <&gcc PCIE_1_PHY_RESET>,
891 <&gcc PCIE_1_EXT_RESET>;
892 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
893
894 pinctrl-0 = <&pcie1_pins>;
895 pinctrl-names = "default";
896
897 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
898
899 status = "disabled";
900 };
901
902 pcie2: pci@1b900000 {
903 compatible = "qcom,pcie-v0";
904 reg = <0x1b900000 0x1000
905 0x1b902000 0x80
906 0x1ba00000 0x100
907 0x35f00000 0x100000>;
908 reg-names = "dbi", "elbi", "parf", "config";
909 device_type = "pci";
910 linux,pci-domain = <2>;
911 bus-range = <0x00 0xff>;
912 num-lanes = <1>;
913 #address-cells = <3>;
914 #size-cells = <2>;
915
916 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
917 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
918
919 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
920 interrupt-names = "msi";
921 #interrupt-cells = <1>;
922 interrupt-map-mask = <0 0 0 0x7>;
923 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
924 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
925 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
926 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
927
928 clocks = <&gcc PCIE_2_A_CLK>,
929 <&gcc PCIE_2_H_CLK>,
930 <&gcc PCIE_2_PHY_CLK>,
931 <&gcc PCIE_2_AUX_CLK>,
932 <&gcc PCIE_2_ALT_REF_CLK>;
933 clock-names = "core", "iface", "phy", "aux", "ref";
934
935 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
936 assigned-clock-rates = <100000000>;
937
938 resets = <&gcc PCIE_2_ACLK_RESET>,
939 <&gcc PCIE_2_HCLK_RESET>,
940 <&gcc PCIE_2_POR_RESET>,
941 <&gcc PCIE_2_PCI_RESET>,
942 <&gcc PCIE_2_PHY_RESET>,
943 <&gcc PCIE_2_EXT_RESET>;
944 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
945
946 pinctrl-0 = <&pcie2_pins>;
947 pinctrl-names = "default";
948
949 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
950
951 status = "disabled";
952 };
953
954 adm_dma: dma@18300000 {
955 compatible = "qcom,adm";
956 reg = <0x18300000 0x100000>;
957 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
958 #dma-cells = <1>;
959
960 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
961 clock-names = "core", "iface";
962
963 resets = <&gcc ADM0_RESET>,
964 <&gcc ADM0_PBUS_RESET>,
965 <&gcc ADM0_C0_RESET>,
966 <&gcc ADM0_C1_RESET>,
967 <&gcc ADM0_C2_RESET>;
968 reset-names = "clk", "pbus", "c0", "c1", "c2";
969 qcom,ee = <0>;
970
971 status = "disabled";
972 };
973
974 nand@1ac00000 {
975 compatible = "qcom,ebi2-nandc";
976 reg = <0x1ac00000 0x800>;
977
978 clocks = <&gcc EBI2_CLK>,
979 <&gcc EBI2_AON_CLK>;
980 clock-names = "core", "aon";
981
982 dmas = <&adm_dma 3>;
983 dma-names = "rxtx";
984 qcom,cmd-crci = <15>;
985 qcom,data-crci = <3>;
986
987 status = "disabled";
988 };
989
990 nss_common: syscon@03000000 {
991 compatible = "syscon";
992 reg = <0x03000000 0x0000FFFF>;
993 };
994
995 qsgmii_csr: syscon@1bb00000 {
996 compatible = "syscon";
997 reg = <0x1bb00000 0x000001FF>;
998 };
999
1000 gmac0: ethernet@37000000 {
1001 device_type = "network";
1002 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1003 reg = <0x37000000 0x200000>;
1004 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1005 interrupt-names = "macirq";
1006
1007 qcom,nss-common = <&nss_common>;
1008 qcom,qsgmii-csr = <&qsgmii_csr>;
1009
1010 clocks = <&gcc GMAC_CORE1_CLK>;
1011 clock-names = "stmmaceth";
1012
1013 resets = <&gcc GMAC_CORE1_RESET>;
1014 reset-names = "stmmaceth";
1015
1016 status = "disabled";
1017 };
1018
1019 gmac1: ethernet@37200000 {
1020 device_type = "network";
1021 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1022 reg = <0x37200000 0x200000>;
1023 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1024 interrupt-names = "macirq";
1025
1026 qcom,nss-common = <&nss_common>;
1027 qcom,qsgmii-csr = <&qsgmii_csr>;
1028
1029 clocks = <&gcc GMAC_CORE2_CLK>;
1030 clock-names = "stmmaceth";
1031
1032 resets = <&gcc GMAC_CORE2_RESET>;
1033 reset-names = "stmmaceth";
1034
1035 status = "disabled";
1036 };
1037
1038 gmac2: ethernet@37400000 {
1039 device_type = "network";
1040 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1041 reg = <0x37400000 0x200000>;
1042 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1043 interrupt-names = "macirq";
1044
1045 qcom,nss-common = <&nss_common>;
1046 qcom,qsgmii-csr = <&qsgmii_csr>;
1047
1048 clocks = <&gcc GMAC_CORE3_CLK>;
1049 clock-names = "stmmaceth";
1050
1051 resets = <&gcc GMAC_CORE3_RESET>;
1052 reset-names = "stmmaceth";
1053
1054 status = "disabled";
1055 };
1056
1057 gmac3: ethernet@37600000 {
1058 device_type = "network";
1059 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1060 reg = <0x37600000 0x200000>;
1061 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1062 interrupt-names = "macirq";
1063
1064 qcom,nss-common = <&nss_common>;
1065 qcom,qsgmii-csr = <&qsgmii_csr>;
1066
1067 clocks = <&gcc GMAC_CORE4_CLK>;
1068 clock-names = "stmmaceth";
1069
1070 resets = <&gcc GMAC_CORE4_RESET>;
1071 reset-names = "stmmaceth";
1072
1073 status = "disabled";
1074 };
1075
1076 /* Temporary fixed regulator */
1077 vsdcc_fixed: vsdcc-regulator {
1078 compatible = "regulator-fixed";
1079 regulator-name = "SDCC Power";
1080 regulator-min-microvolt = <3300000>;
1081 regulator-max-microvolt = <3300000>;
1082 regulator-always-on;
1083 };
1084
1085 sdcc1bam:dma@12402000 {
1086 compatible = "qcom,bam-v1.3.0";
1087 reg = <0x12402000 0x8000>;
1088 interrupts = <0 98 0>;
1089 clocks = <&gcc SDC1_H_CLK>;
1090 clock-names = "bam_clk";
1091 #dma-cells = <1>;
1092 qcom,ee = <0>;
1093 };
1094
1095 sdcc3bam:dma@12182000 {
1096 compatible = "qcom,bam-v1.3.0";
1097 reg = <0x12182000 0x8000>;
1098 interrupts = <0 96 0>;
1099 clocks = <&gcc SDC3_H_CLK>;
1100 clock-names = "bam_clk";
1101 #dma-cells = <1>;
1102 qcom,ee = <0>;
1103 };
1104
1105 amba {
1106 compatible = "arm,amba-bus";
1107 #address-cells = <1>;
1108 #size-cells = <1>;
1109 ranges;
1110 sdcc1: sdcc@12400000 {
1111 status = "disabled";
1112 compatible = "arm,pl18x", "arm,primecell";
1113 arm,primecell-periphid = <0x00051180>;
1114 reg = <0x12400000 0x2000>;
1115 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1116 interrupt-names = "cmd_irq";
1117 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1118 clock-names = "mclk", "apb_pclk";
1119 bus-width = <8>;
1120 max-frequency = <48000000>;
1121 non-removable;
1122 cap-sd-highspeed;
1123 cap-mmc-highspeed;
1124 vmmc-supply = <&vsdcc_fixed>;
1125 #dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1126 #dma-names = "tx", "rx";
1127 };
1128
1129 sdcc3: sdcc@12180000 {
1130 compatible = "arm,pl18x", "arm,primecell";
1131 arm,primecell-periphid = <0x00051180>;
1132 status = "disabled";
1133 reg = <0x12180000 0x2000>;
1134 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "cmd_irq";
1136 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1137 clock-names = "mclk", "apb_pclk";
1138 bus-width = <8>;
1139 cap-sd-highspeed;
1140 cap-mmc-highspeed;
1141 max-frequency = <192000000>;
1142 #mmc-ddr-1_8v;
1143 sd-uhs-sdr50;
1144 vmmc-supply = <&vsdcc_fixed>;
1145 #dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1146 #dma-names = "tx", "rx";
1147 };
1148 };
1149 };
1150
1151 sfpb_mutex: sfpb-mutex {
1152 compatible = "qcom,sfpb-mutex";
1153 syscon = <&sfpb_mutex_block 4 4>;
1154
1155 #hwlock-cells = <1>;
1156 };
1157
1158 smem {
1159 compatible = "qcom,smem";
1160 memory-region = <&smem>;
1161 hwlocks = <&sfpb_mutex 3>;
1162 };
1163 };
OpenWrt Source Repository