target/linux/ipq806x/patches-4.0/134-clk-mux-Split-out-register-accessors-for-reuse.patch

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   4 Subject: [v3,02/13] clk: mux: Split out register accessors for reuse
   5 From: Stephen Boyd <sboyd@codeaurora.org>
   6 X-Patchwork-Id: 6063111
   7 Message-Id: <1426920332-9340-3-git-send-email-sboyd@codeaurora.org>
   8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
   9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
  10         linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
  11         Viresh Kumar <viresh.kumar@linaro.org>
  12 Date: Fri, 20 Mar 2015 23:45:21 -0700
  13
  14 We want to reuse the logic in clk-mux.c for other clock drivers
  15 that don't use readl as register accessors. Fortunately, there
  16 really isn't much to the mux code besides the table indirection
  17 and quirk flags if you assume any bit shifting and masking has
  18 been done already. Pull that logic out into reusable functions
  19 that operate on an optional table and some flags so that other
  20 drivers can use the same logic.
  21
  22 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  23
  24 ---
  25 drivers/clk/clk-mux.c        | 76 +++++++++++++++++++++++++++-----------------
  26  include/linux/clk-provider.h |  9 ++++--
  27  2 files changed, 54 insertions(+), 31 deletions(-)
  28
  29 --- a/drivers/clk/clk-mux.c
  30 +++ b/drivers/clk/clk-mux.c
  31 @@ -29,35 +29,24 @@
  32
  33  #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
  34
  35 -static u8 clk_mux_get_parent(struct clk_hw *hw)
  36 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
  37 +                               unsigned int *table, unsigned long flags)
  38  {
  39 -       struct clk_mux *mux = to_clk_mux(hw);
  40         int num_parents = __clk_get_num_parents(hw->clk);
  41 -       u32 val;
  42
  43 -       /*
  44 -        * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  45 -        * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  46 -        * to 0x7 (index starts at one)
  47 -        * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  48 -        * val = 0x4 really means "bit 2, index starts at bit 0"
  49 -        */
  50 -       val = clk_readl(mux->reg) >> mux->shift;
  51 -       val &= mux->mask;
  52 -
  53 -       if (mux->table) {
  54 +       if (table) {
  55                 int i;
  56
  57                 for (i = 0; i < num_parents; i++)
  58 -                       if (mux->table[i] == val)
  59 +                       if (table[i] == val)
  60                                 return i;
  61                 return -EINVAL;
  62         }
  63
  64 -       if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  65 +       if (val && (flags & CLK_MUX_INDEX_BIT))
  66                 val = ffs(val) - 1;
  67
  68 -       if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  69 +       if (val && (flags & CLK_MUX_INDEX_ONE))
  70                 val--;
  71
  72         if (val >= num_parents)
  73 @@ -65,24 +54,53 @@ static u8 clk_mux_get_parent(struct clk_
  74
  75         return val;
  76  }
  77 +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
  78
  79 -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
  80 +static u8 _clk_mux_get_parent(struct clk_hw *hw)
  81  {
  82         struct clk_mux *mux = to_clk_mux(hw);
  83         u32 val;
  84 -       unsigned long flags = 0;
  85
  86 -       if (mux->table)
  87 -               index = mux->table[index];
  88 +       /*
  89 +        * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  90 +        * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  91 +        * to 0x7 (index starts at one)
  92 +        * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  93 +        * val = 0x4 really means "bit 2, index starts at bit 0"
  94 +        */
  95 +       val = clk_readl(mux->reg) >> mux->shift;
  96 +       val &= mux->mask;
  97 +
  98 +       return clk_mux_get_parent(hw, val, mux->table, mux->flags);
  99 +}
 100
 101 -       else {
 102 -               if (mux->flags & CLK_MUX_INDEX_BIT)
 103 -                       index = 1 << index;
 104 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
 105 +                            unsigned long flags)
 106 +{
 107 +       unsigned int val = index;
 108
 109 -               if (mux->flags & CLK_MUX_INDEX_ONE)
 110 -                       index++;
 111 +       if (table) {
 112 +               val = table[val];
 113 +       } else {
 114 +               if (flags & CLK_MUX_INDEX_BIT)
 115 +                       val = 1 << index;
 116 +
 117 +               if (flags & CLK_MUX_INDEX_ONE)
 118 +                       val++;
 119         }
 120
 121 +       return val;
 122 +}
 123 +EXPORT_SYMBOL_GPL(clk_mux_reindex);
 124 +
 125 +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 126 +{
 127 +       struct clk_mux *mux = to_clk_mux(hw);
 128 +       u32 val;
 129 +       unsigned long flags = 0;
 130 +
 131 +       index = clk_mux_reindex(index, mux->table, mux->flags);
 132 +
 133         if (mux->lock)
 134                 spin_lock_irqsave(mux->lock, flags);
 135
 136 @@ -102,21 +120,21 @@ static int clk_mux_set_parent(struct clk
 137  }
 138
 139  const struct clk_ops clk_mux_ops = {
 140 -       .get_parent = clk_mux_get_parent,
 141 +       .get_parent = _clk_mux_get_parent,
 142         .set_parent = clk_mux_set_parent,
 143         .determine_rate = __clk_mux_determine_rate,
 144  };
 145  EXPORT_SYMBOL_GPL(clk_mux_ops);
 146
 147  const struct clk_ops clk_mux_ro_ops = {
 148 -       .get_parent = clk_mux_get_parent,
 149 +       .get_parent = _clk_mux_get_parent,
 150  };
 151  EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
 152
 153  struct clk *clk_register_mux_table(struct device *dev, const char *name,
 154                 const char **parent_names, u8 num_parents, unsigned long flags,
 155                 void __iomem *reg, u8 shift, u32 mask,
 156 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock)
 157 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
 158  {
 159         struct clk_mux *mux;
 160         struct clk *clk;
 161 --- a/include/linux/clk-provider.h
 162 +++ b/include/linux/clk-provider.h
 163 @@ -409,7 +409,7 @@ void clk_unregister_divider(struct clk *
 164  struct clk_mux {
 165         struct clk_hw   hw;
 166         void __iomem    *reg;
 167 -       u32             *table;
 168 +       unsigned int    *table;
 169         u32             mask;
 170         u8              shift;
 171         u8              flags;
 172 @@ -425,6 +425,11 @@ struct clk_mux {
 173  extern const struct clk_ops clk_mux_ops;
 174  extern const struct clk_ops clk_mux_ro_ops;
 175
 176 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
 177 +                               unsigned int *table, unsigned long flags);
 178 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
 179 +                            unsigned long flags);
 180 +
 181  struct clk *clk_register_mux(struct device *dev, const char *name,
 182                 const char **parent_names, u8 num_parents, unsigned long flags,
 183                 void __iomem *reg, u8 shift, u8 width,
 184 @@ -433,7 +438,7 @@ struct clk *clk_register_mux(struct devi
 185  struct clk *clk_register_mux_table(struct device *dev, const char *name,
 186                 const char **parent_names, u8 num_parents, unsigned long flags,
 187                 void __iomem *reg, u8 shift, u32 mask,
 188 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 189 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
 190
 191  void clk_unregister_mux(struct clk *clk);
 192