target/linux/ipq806x/patches-4.0/137-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch

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   4 Subject: [v3,05/13] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
   5 From: Stephen Boyd <sboyd@codeaurora.org>
   6 X-Patchwork-Id: 6063261
   7 Message-Id: <1426920332-9340-6-git-send-email-sboyd@codeaurora.org>
   8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
   9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
  10         linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
  11         Viresh Kumar <viresh.kumar@linaro.org>
  12 Date: Fri, 20 Mar 2015 23:45:24 -0700
  13
  14 HFPLLs are the main frequency source for Krait CPU clocks. Add
  15 support for changing the rate of these PLLs.
  16
  17 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  18
  19 ---
  20 I'd really like to get rid of __clk_hfpll_init_once() if possible...
  21
  22  drivers/clk/qcom/Makefile    |   1 +
  23  drivers/clk/qcom/clk-hfpll.c | 253 +++++++++++++++++++++++++++++++++++++++++++
  24  drivers/clk/qcom/clk-hfpll.h |  54 +++++++++
  25  3 files changed, 308 insertions(+)
  26  create mode 100644 drivers/clk/qcom/clk-hfpll.c
  27  create mode 100644 drivers/clk/qcom/clk-hfpll.h
  28
  29 --- a/drivers/clk/qcom/Makefile
  30 +++ b/drivers/clk/qcom/Makefile
  31 @@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o
  32  clk-qcom-y += clk-branch.o
  33  clk-qcom-y += clk-regmap-divider.o
  34  clk-qcom-y += clk-regmap-mux.o
  35 +clk-qcom-y += clk-hfpll.o
  36  clk-qcom-y += reset.o
  37
  38  obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
  39 --- /dev/null
  40 +++ b/drivers/clk/qcom/clk-hfpll.c
  41 @@ -0,0 +1,253 @@
  42 +/*
  43 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  44 + *
  45 + * This program is free software; you can redistribute it and/or modify
  46 + * it under the terms of the GNU General Public License version 2 and
  47 + * only version 2 as published by the Free Software Foundation.
  48 + *
  49 + * This program is distributed in the hope that it will be useful,
  50 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  51 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  52 + * GNU General Public License for more details.
  53 + */
  54 +#include <linux/kernel.h>
  55 +#include <linux/export.h>
  56 +#include <linux/regmap.h>
  57 +#include <linux/delay.h>
  58 +#include <linux/err.h>
  59 +#include <linux/clk-provider.h>
  60 +#include <linux/spinlock.h>
  61 +
  62 +#include "clk-regmap.h"
  63 +#include "clk-hfpll.h"
  64 +
  65 +#define PLL_OUTCTRL    BIT(0)
  66 +#define PLL_BYPASSNL   BIT(1)
  67 +#define PLL_RESET_N    BIT(2)
  68 +
  69 +/* Initialize a HFPLL at a given rate and enable it. */
  70 +static void __clk_hfpll_init_once(struct clk_hw *hw)
  71 +{
  72 +       struct clk_hfpll *h = to_clk_hfpll(hw);
  73 +       struct hfpll_data const *hd = h->d;
  74 +       struct regmap *regmap = h->clkr.regmap;
  75 +
  76 +       if (likely(h->init_done))
  77 +               return;
  78 +
  79 +       /* Configure PLL parameters for integer mode. */
  80 +       if (hd->config_val)
  81 +               regmap_write(regmap, hd->config_reg, hd->config_val);
  82 +       regmap_write(regmap, hd->m_reg, 0);
  83 +       regmap_write(regmap, hd->n_reg, 1);
  84 +
  85 +       if (hd->user_reg) {
  86 +               u32 regval = hd->user_val;
  87 +               unsigned long rate;
  88 +
  89 +               rate = __clk_get_rate(hw->clk);
  90 +
  91 +               /* Pick the right VCO. */
  92 +               if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
  93 +                       regval |= hd->user_vco_mask;
  94 +               regmap_write(regmap, hd->user_reg, regval);
  95 +       }
  96 +
  97 +       if (hd->droop_reg)
  98 +               regmap_write(regmap, hd->droop_reg, hd->droop_val);
  99 +
 100 +       h->init_done = true;
 101 +}
 102 +
 103 +static void __clk_hfpll_enable(struct clk_hw *hw)
 104 +{
 105 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 106 +       struct hfpll_data const *hd = h->d;
 107 +       struct regmap *regmap = h->clkr.regmap;
 108 +       u32 val;
 109 +
 110 +       __clk_hfpll_init_once(hw);
 111 +
 112 +       /* Disable PLL bypass mode. */
 113 +       regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
 114 +
 115 +       /*
 116 +        * H/W requires a 5us delay between disabling the bypass and
 117 +        * de-asserting the reset. Delay 10us just to be safe.
 118 +        */
 119 +       udelay(10);
 120 +
 121 +       /* De-assert active-low PLL reset. */
 122 +       regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
 123 +
 124 +       /* Wait for PLL to lock. */
 125 +       if (hd->status_reg) {
 126 +               do {
 127 +                       regmap_read(regmap, hd->status_reg, &val);
 128 +               } while (!(val & BIT(hd->lock_bit)));
 129 +       } else {
 130 +               udelay(60);
 131 +       }
 132 +
 133 +       /* Enable PLL output. */
 134 +       regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
 135 +}
 136 +
 137 +/* Enable an already-configured HFPLL. */
 138 +static int clk_hfpll_enable(struct clk_hw *hw)
 139 +{
 140 +       unsigned long flags;
 141 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 142 +       struct hfpll_data const *hd = h->d;
 143 +       struct regmap *regmap = h->clkr.regmap;
 144 +       u32 mode;
 145 +
 146 +       spin_lock_irqsave(&h->lock, flags);
 147 +       regmap_read(regmap, hd->mode_reg, &mode);
 148 +       if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
 149 +               __clk_hfpll_enable(hw);
 150 +       spin_unlock_irqrestore(&h->lock, flags);
 151 +
 152 +       return 0;
 153 +}
 154 +
 155 +static void __clk_hfpll_disable(struct clk_hfpll *h)
 156 +{
 157 +       struct hfpll_data const *hd = h->d;
 158 +       struct regmap *regmap = h->clkr.regmap;
 159 +
 160 +       /*
 161 +        * Disable the PLL output, disable test mode, enable the bypass mode,
 162 +        * and assert the reset.
 163 +        */
 164 +       regmap_update_bits(regmap, hd->mode_reg,
 165 +                       PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
 166 +}
 167 +
 168 +static void clk_hfpll_disable(struct clk_hw *hw)
 169 +{
 170 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 171 +       unsigned long flags;
 172 +
 173 +       spin_lock_irqsave(&h->lock, flags);
 174 +       __clk_hfpll_disable(h);
 175 +       spin_unlock_irqrestore(&h->lock, flags);
 176 +}
 177 +
 178 +static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
 179 +                                unsigned long *parent_rate)
 180 +{
 181 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 182 +       struct hfpll_data const *hd = h->d;
 183 +       unsigned long rrate;
 184 +
 185 +       rate = clamp(rate, hd->min_rate, hd->max_rate);
 186 +
 187 +       rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
 188 +       if (rrate > hd->max_rate)
 189 +               rrate -= *parent_rate;
 190 +
 191 +       return rrate;
 192 +}
 193 +
 194 +/*
 195 + * For optimization reasons, assumes no downstream clocks are actively using
 196 + * it.
 197 + */
 198 +static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
 199 +                             unsigned long parent_rate)
 200 +{
 201 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 202 +       struct hfpll_data const *hd = h->d;
 203 +       struct regmap *regmap = h->clkr.regmap;
 204 +       unsigned long flags;
 205 +       u32 l_val, val;
 206 +       bool enabled;
 207 +
 208 +       l_val = rate / parent_rate;
 209 +
 210 +       spin_lock_irqsave(&h->lock, flags);
 211 +
 212 +       enabled = __clk_is_enabled(hw->clk);
 213 +       if (enabled)
 214 +               __clk_hfpll_disable(h);
 215 +
 216 +       /* Pick the right VCO. */
 217 +       if (hd->user_reg && hd->user_vco_mask) {
 218 +               regmap_read(regmap, hd->user_reg, &val);
 219 +               if (rate <= hd->low_vco_max_rate)
 220 +                       val &= ~hd->user_vco_mask;
 221 +               else
 222 +                       val |= hd->user_vco_mask;
 223 +               regmap_write(regmap, hd->user_reg, val);
 224 +       }
 225 +
 226 +       regmap_write(regmap, hd->l_reg, l_val);
 227 +
 228 +       if (enabled)
 229 +               __clk_hfpll_enable(hw);
 230 +
 231 +       spin_unlock_irqrestore(&h->lock, flags);
 232 +
 233 +       return 0;
 234 +}
 235 +
 236 +static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw,
 237 +                                          unsigned long parent_rate)
 238 +{
 239 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 240 +       struct hfpll_data const *hd = h->d;
 241 +       struct regmap *regmap = h->clkr.regmap;
 242 +       u32 l_val;
 243 +
 244 +       regmap_read(regmap, hd->l_reg, &l_val);
 245 +
 246 +       return l_val * parent_rate;
 247 +}
 248 +
 249 +static void clk_hfpll_init(struct clk_hw *hw)
 250 +{
 251 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 252 +       struct hfpll_data const *hd = h->d;
 253 +       struct regmap *regmap = h->clkr.regmap;
 254 +       u32 mode, status;
 255 +
 256 +       regmap_read(regmap, hd->mode_reg, &mode);
 257 +       if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) {
 258 +               __clk_hfpll_init_once(hw);
 259 +               return;
 260 +       }
 261 +
 262 +       if (hd->status_reg) {
 263 +               regmap_read(regmap, hd->status_reg, &status);
 264 +               if (!(status & BIT(hd->lock_bit))) {
 265 +                       WARN(1, "HFPLL %s is ON, but not locked!\n",
 266 +                                       __clk_get_name(hw->clk));
 267 +                       clk_hfpll_disable(hw);
 268 +                       __clk_hfpll_init_once(hw);
 269 +               }
 270 +       }
 271 +}
 272 +
 273 +static int hfpll_is_enabled(struct clk_hw *hw)
 274 +{
 275 +       struct clk_hfpll *h = to_clk_hfpll(hw);
 276 +       struct hfpll_data const *hd = h->d;
 277 +       struct regmap *regmap = h->clkr.regmap;
 278 +       u32 mode;
 279 +
 280 +       regmap_read(regmap, hd->mode_reg, &mode);
 281 +       mode &= 0x7;
 282 +       return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL);
 283 +}
 284 +
 285 +const struct clk_ops clk_ops_hfpll = {
 286 +       .enable = clk_hfpll_enable,
 287 +       .disable = clk_hfpll_disable,
 288 +       .is_enabled = hfpll_is_enabled,
 289 +       .round_rate = clk_hfpll_round_rate,
 290 +       .set_rate = clk_hfpll_set_rate,
 291 +       .recalc_rate = clk_hfpll_recalc_rate,
 292 +       .init = clk_hfpll_init,
 293 +};
 294 +EXPORT_SYMBOL_GPL(clk_ops_hfpll);
 295 --- /dev/null
 296 +++ b/drivers/clk/qcom/clk-hfpll.h
 297 @@ -0,0 +1,54 @@
 298 +/*
 299 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 300 + *
 301 + * This program is free software; you can redistribute it and/or modify
 302 + * it under the terms of the GNU General Public License version 2 and
 303 + * only version 2 as published by the Free Software Foundation.
 304 + *
 305 + * This program is distributed in the hope that it will be useful,
 306 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 307 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 308 + * GNU General Public License for more details.
 309 + */
 310 +#ifndef __QCOM_CLK_HFPLL_H__
 311 +#define __QCOM_CLK_HFPLL_H__
 312 +
 313 +#include <linux/clk-provider.h>
 314 +#include <linux/spinlock.h>
 315 +#include "clk-regmap.h"
 316 +
 317 +struct hfpll_data {
 318 +       u32 mode_reg;
 319 +       u32 l_reg;
 320 +       u32 m_reg;
 321 +       u32 n_reg;
 322 +       u32 user_reg;
 323 +       u32 droop_reg;
 324 +       u32 config_reg;
 325 +       u32 status_reg;
 326 +       u8  lock_bit;
 327 +
 328 +       u32 droop_val;
 329 +       u32 config_val;
 330 +       u32 user_val;
 331 +       u32 user_vco_mask;
 332 +       unsigned long low_vco_max_rate;
 333 +
 334 +       unsigned long min_rate;
 335 +       unsigned long max_rate;
 336 +};
 337 +
 338 +struct clk_hfpll {
 339 +       struct hfpll_data const *d;
 340 +       int init_done;
 341 +
 342 +       struct clk_regmap clkr;
 343 +       spinlock_t lock;
 344 +};
 345 +
 346 +#define to_clk_hfpll(_hw) \
 347 +       container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
 348 +
 349 +extern const struct clk_ops clk_ops_hfpll;
 350 +
 351 +#endif