target/linux/ipq806x/patches-4.1/111-PCI-qcom-Add-Qualcomm-PCIe-controller-driver.patch

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   4 Subject: [v2,4/5] PCI: qcom: Add Qualcomm PCIe controller driver
   5 From: Stanimir Varbanov <svarbanov@mm-sol.com>
   6 X-Patchwork-Id: 6326161
   7 Message-Id: <1430743338-10441-5-git-send-email-svarbanov@mm-sol.com>
   8 To: Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>,
   9         Mark Rutland <mark.rutland@arm.com>,
  10         Grant Likely <grant.likely@linaro.org>,
  11         Bjorn Helgaas <bhelgaas@google.com>,
  12         Kishon Vijay Abraham I <kishon@ti.com>,
  13         Russell King <linux@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>
  14 Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
  15         linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
  16         linux-pci@vger.kernel.org, Mathieu Olivari <mathieu@codeaurora.org>,
  17         Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
  18         Stanimir Varbanov <svarbanov@mm-sol.com>
  19 Date: Mon,  4 May 2015 15:42:17 +0300
  20
  21 The PCIe driver reuse the Designware common code for host
  22 and MSI initialization, and also program the Qualcomm
  23 application specific registers.
  24
  25 Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  26
  27 ---
  28 MAINTAINERS                  |    7 +
  29  drivers/pci/host/Kconfig     |    9 +
  30  drivers/pci/host/Makefile    |    1 +
  31  drivers/pci/host/pcie-qcom.c |  677 ++++++++++++++++++++++++++++++++++++++++++
  32  4 files changed, 694 insertions(+), 0 deletions(-)
  33  create mode 100644 drivers/pci/host/pcie-qcom.c
  34
  35 --- a/MAINTAINERS
  36 +++ b/MAINTAINERS
  37 @@ -7599,6 +7599,13 @@ L:       linux-pci@vger.kernel.org
  38  S:     Maintained
  39  F:     drivers/pci/host/*spear*
  40
  41 +PCIE DRIVER FOR QUALCOMM MSM
  42 +M:     Stanimir Varbanov <svarbanov@mm-sol.com>
  43 +L:     linux-pci@vger.kernel.org
  44 +L:     linux-arm-msm@vger.kernel.org
  45 +S:     Maintained
  46 +F:     drivers/pci/host/*qcom*
  47 +
  48  PCMCIA SUBSYSTEM
  49  P:     Linux PCMCIA Team
  50  L:     linux-pcmcia@lists.infradead.org
  51 --- a/drivers/pci/host/Kconfig
  52 +++ b/drivers/pci/host/Kconfig
  53 @@ -125,4 +125,13 @@ config PCIE_IPROC_PLATFORM
  54           Say Y here if you want to use the Broadcom iProc PCIe controller
  55           through the generic platform bus interface
  56
  57 +config PCIE_QCOM
  58 +       bool "Qualcomm PCIe controller"
  59 +       depends on ARCH_QCOM && OF || (ARM && COMPILE_TEST)
  60 +       select PCIE_DW
  61 +       select PCIEPORTBUS
  62 +       help
  63 +         Say Y here to enable PCIe controller support on Qualcomm SoCs. The
  64 +         PCIe controller use Designware core plus Qualcomm specific hardware
  65 +         wrappers.
  66  endmenu
  67 --- /dev/null
  68 +++ b/drivers/pci/host/pcie-qcom.c
  69 @@ -0,0 +1,677 @@
  70 +/*
  71 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  72 + *
  73 + * This program is free software; you can redistribute it and/or modify
  74 + * it under the terms of the GNU General Public License version 2 and
  75 + * only version 2 as published by the Free Software Foundation.
  76 + *
  77 + * This program is distributed in the hope that it will be useful,
  78 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  79 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  80 + * GNU General Public License for more details.
  81 + */
  82 +
  83 +#include <linux/clk.h>
  84 +#include <linux/delay.h>
  85 +#include <linux/gpio.h>
  86 +#include <linux/interrupt.h>
  87 +#include <linux/io.h>
  88 +#include <linux/kernel.h>
  89 +#include <linux/module.h>
  90 +#include <linux/of_gpio.h>
  91 +#include <linux/pci.h>
  92 +#include <linux/platform_device.h>
  93 +#include <linux/phy/phy.h>
  94 +#include <linux/regulator/consumer.h>
  95 +#include <linux/reset.h>
  96 +#include <linux/slab.h>
  97 +#include <linux/types.h>
  98 +
  99 +#include "pcie-designware.h"
 100 +
 101 +#define PCIE20_PARF_PHY_CTRL                   0x40
 102 +#define PCIE20_PARF_PHY_REFCLK                 0x4C
 103 +#define PCIE20_PARF_DBI_BASE_ADDR              0x168
 104 +#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE                0x16c
 105 +#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT      0x178
 106 +
 107 +#define PCIE20_ELBI_SYS_CTRL                   0x04
 108 +#define PCIE20_ELBI_SYS_STTS                   0x08
 109 +#define XMLH_LINK_UP                           BIT(10)
 110 +
 111 +#define PCIE20_CAP                             0x70
 112 +#define PCIE20_CAP_LINKCTRLSTATUS              (PCIE20_CAP + 0x10)
 113 +
 114 +#define PERST_DELAY_MIN_US                     1000
 115 +#define PERST_DELAY_MAX_US                     1005
 116 +
 117 +#define LINKUP_DELAY_MIN_US                    5000
 118 +#define LINKUP_DELAY_MAX_US                    5100
 119 +#define LINKUP_RETRIES_COUNT                   20
 120 +
 121 +#define PCIE_V0                                        0       /* apq8064 */
 122 +#define PCIE_V1                                        1       /* apq8084 */
 123 +
 124 +struct qcom_pcie_resources_v0 {
 125 +       struct clk *iface_clk;
 126 +       struct clk *core_clk;
 127 +       struct clk *phy_clk;
 128 +       struct reset_control *pci_reset;
 129 +       struct reset_control *axi_reset;
 130 +       struct reset_control *ahb_reset;
 131 +       struct reset_control *por_reset;
 132 +       struct reset_control *phy_reset;
 133 +       struct regulator *vdda;
 134 +       struct regulator *vdda_phy;
 135 +       struct regulator *vdda_refclk;
 136 +};
 137 +
 138 +struct qcom_pcie_resources_v1 {
 139 +       struct clk *iface;
 140 +       struct clk *aux;
 141 +       struct clk *master_bus;
 142 +       struct clk *slave_bus;
 143 +       struct reset_control *core;
 144 +       struct regulator *vdda;
 145 +};
 146 +
 147 +union pcie_resources {
 148 +       struct qcom_pcie_resources_v0 v0;
 149 +       struct qcom_pcie_resources_v1 v1;
 150 +};
 151 +
 152 +struct qcom_pcie {
 153 +       struct pcie_port pp;
 154 +       struct device *dev;
 155 +       union pcie_resources res;
 156 +       void __iomem *parf;
 157 +       void __iomem *dbi;
 158 +       void __iomem *elbi;
 159 +       struct phy *phy;
 160 +       struct gpio_desc *reset;
 161 +       unsigned int version;
 162 +};
 163 +
 164 +#define to_qcom_pcie(x)                container_of(x, struct qcom_pcie, pp)
 165 +
 166 +static inline void
 167 +writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
 168 +{
 169 +       u32 val = readl(addr);
 170 +
 171 +       val &= ~clear_mask;
 172 +       val |= set_mask;
 173 +       writel(val, addr);
 174 +}
 175 +
 176 +static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
 177 +{
 178 +       int val, active_low;
 179 +
 180 +       if (IS_ERR_OR_NULL(pcie->reset))
 181 +               return;
 182 +
 183 +       active_low = gpiod_is_active_low(pcie->reset);
 184 +
 185 +       if (assert)
 186 +               val = !!active_low;
 187 +       else
 188 +               val = !active_low;
 189 +
 190 +       gpiod_set_value(pcie->reset, val);
 191 +
 192 +       usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
 193 +}
 194 +
 195 +static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
 196 +{
 197 +       qcom_ep_reset_assert_deassert(pcie, 1);
 198 +}
 199 +
 200 +static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
 201 +{
 202 +       qcom_ep_reset_assert_deassert(pcie, 0);
 203 +}
 204 +
 205 +static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
 206 +{
 207 +       struct pcie_port *pp = arg;
 208 +
 209 +       return dw_handle_msi_irq(pp);
 210 +}
 211 +
 212 +static int qcom_pcie_link_up(struct pcie_port *pp)
 213 +{
 214 +       struct qcom_pcie *pcie = to_qcom_pcie(pp);
 215 +       u32 val = readl(pcie->dbi + PCIE20_CAP_LINKCTRLSTATUS);
 216 +
 217 +       return val & BIT(29) ? 1 : 0;
 218 +}
 219 +
 220 +static void qcom_pcie_disable_resources_v0(struct qcom_pcie *pcie)
 221 +{
 222 +       struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
 223 +
 224 +       reset_control_assert(res->pci_reset);
 225 +       reset_control_assert(res->axi_reset);
 226 +       reset_control_assert(res->ahb_reset);
 227 +       reset_control_assert(res->por_reset);
 228 +       reset_control_assert(res->pci_reset);
 229 +       clk_disable_unprepare(res->iface_clk);
 230 +       clk_disable_unprepare(res->core_clk);
 231 +       clk_disable_unprepare(res->phy_clk);
 232 +       regulator_disable(res->vdda);
 233 +       regulator_disable(res->vdda_phy);
 234 +       regulator_disable(res->vdda_refclk);
 235 +}
 236 +
 237 +static void qcom_pcie_disable_resources_v1(struct qcom_pcie *pcie)
 238 +{
 239 +       struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
 240 +
 241 +       reset_control_assert(res->core);
 242 +       clk_disable_unprepare(res->slave_bus);
 243 +       clk_disable_unprepare(res->master_bus);
 244 +       clk_disable_unprepare(res->iface);
 245 +       clk_disable_unprepare(res->aux);
 246 +       regulator_disable(res->vdda);
 247 +}
 248 +
 249 +static int qcom_pcie_enable_resources_v0(struct qcom_pcie *pcie)
 250 +{
 251 +       struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
 252 +       struct device *dev = pcie->dev;
 253 +       int ret;
 254 +
 255 +       ret = regulator_enable(res->vdda);
 256 +       if (ret) {
 257 +               dev_err(dev, "cannot enable vdda regulator\n");
 258 +               return ret;
 259 +       }
 260 +
 261 +       ret = regulator_enable(res->vdda_refclk);
 262 +       if (ret) {
 263 +               dev_err(dev, "cannot enable vdda_refclk regulator\n");
 264 +               goto err_refclk;
 265 +       }
 266 +
 267 +       ret = regulator_enable(res->vdda_phy);
 268 +       if (ret) {
 269 +               dev_err(dev, "cannot enable vdda_phy regulator\n");
 270 +               goto err_vdda_phy;
 271 +       }
 272 +
 273 +       ret = clk_prepare_enable(res->iface_clk);
 274 +       if (ret) {
 275 +               dev_err(dev, "cannot prepare/enable iface clock\n");
 276 +               goto err_iface;
 277 +       }
 278 +
 279 +       ret = clk_prepare_enable(res->core_clk);
 280 +       if (ret) {
 281 +               dev_err(dev, "cannot prepare/enable core clock\n");
 282 +               goto err_clk_core;
 283 +       }
 284 +
 285 +       ret = clk_prepare_enable(res->phy_clk);
 286 +       if (ret) {
 287 +               dev_err(dev, "cannot prepare/enable phy clock\n");
 288 +               goto err_clk_phy;
 289 +       }
 290 +
 291 +       ret = reset_control_deassert(res->ahb_reset);
 292 +       if (ret) {
 293 +               dev_err(dev, "cannot deassert ahb reset\n");
 294 +               goto err_reset_ahb;
 295 +       }
 296 +
 297 +       return 0;
 298 +
 299 +err_reset_ahb:
 300 +       clk_disable_unprepare(res->phy_clk);
 301 +err_clk_phy:
 302 +       clk_disable_unprepare(res->core_clk);
 303 +err_clk_core:
 304 +       clk_disable_unprepare(res->iface_clk);
 305 +err_iface:
 306 +       regulator_disable(res->vdda_phy);
 307 +err_vdda_phy:
 308 +       regulator_disable(res->vdda_refclk);
 309 +err_refclk:
 310 +       regulator_disable(res->vdda);
 311 +       return ret;
 312 +}
 313 +
 314 +static int qcom_pcie_enable_resources_v1(struct qcom_pcie *pcie)
 315 +{
 316 +       struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
 317 +       struct device *dev = pcie->dev;
 318 +       int ret;
 319 +
 320 +       ret = reset_control_deassert(res->core);
 321 +       if (ret) {
 322 +               dev_err(dev, "cannot deassert core reset\n");
 323 +               return ret;
 324 +       }
 325 +
 326 +       ret = clk_prepare_enable(res->aux);
 327 +       if (ret) {
 328 +               dev_err(dev, "cannot prepare/enable aux clock\n");
 329 +               goto err_res;
 330 +       }
 331 +
 332 +       ret = clk_prepare_enable(res->iface);
 333 +       if (ret) {
 334 +               dev_err(dev, "cannot prepare/enable iface clock\n");
 335 +               goto err_aux;
 336 +       }
 337 +
 338 +       ret = clk_prepare_enable(res->master_bus);
 339 +       if (ret) {
 340 +               dev_err(dev, "cannot prepare/enable master_bus clock\n");
 341 +               goto err_iface;
 342 +       }
 343 +
 344 +       ret = clk_prepare_enable(res->slave_bus);
 345 +       if (ret) {
 346 +               dev_err(dev, "cannot prepare/enable slave_bus clock\n");
 347 +               goto err_master;
 348 +       }
 349 +
 350 +       ret = regulator_enable(res->vdda);
 351 +       if (ret) {
 352 +               dev_err(dev, "cannot enable vdda regulator\n");
 353 +               goto err_slave;
 354 +       }
 355 +
 356 +       return 0;
 357 +
 358 +err_slave:
 359 +       clk_disable_unprepare(res->slave_bus);
 360 +err_master:
 361 +       clk_disable_unprepare(res->master_bus);
 362 +err_iface:
 363 +       clk_disable_unprepare(res->iface);
 364 +err_aux:
 365 +       clk_disable_unprepare(res->aux);
 366 +err_res:
 367 +       reset_control_assert(res->core);
 368 +
 369 +       return ret;
 370 +}
 371 +
 372 +static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
 373 +{
 374 +       struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
 375 +       struct device *dev = pcie->dev;
 376 +
 377 +       res->vdda = devm_regulator_get(dev, "vdda");
 378 +       if (IS_ERR(res->vdda))
 379 +               return PTR_ERR(res->vdda);
 380 +
 381 +       res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
 382 +       if (IS_ERR(res->vdda_phy))
 383 +               return PTR_ERR(res->vdda_phy);
 384 +
 385 +       res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
 386 +       if (IS_ERR(res->vdda_refclk))
 387 +               return PTR_ERR(res->vdda_refclk);
 388 +
 389 +       res->iface_clk = devm_clk_get(dev, "iface");
 390 +       if (IS_ERR(res->iface_clk))
 391 +               return PTR_ERR(res->iface_clk);
 392 +
 393 +       res->core_clk = devm_clk_get(dev, "core");
 394 +       if (IS_ERR(res->core_clk))
 395 +               return PTR_ERR(res->core_clk);
 396 +
 397 +       res->phy_clk = devm_clk_get(dev, "phy");
 398 +       if (IS_ERR(res->phy_clk))
 399 +               return PTR_ERR(res->phy_clk);
 400 +
 401 +       res->pci_reset = devm_reset_control_get(dev, "pci");
 402 +       if (IS_ERR(res->pci_reset))
 403 +               return PTR_ERR(res->pci_reset);
 404 +
 405 +       res->axi_reset = devm_reset_control_get(dev, "axi");
 406 +       if (IS_ERR(res->axi_reset))
 407 +               return PTR_ERR(res->axi_reset);
 408 +
 409 +       res->ahb_reset = devm_reset_control_get(dev, "ahb");
 410 +       if (IS_ERR(res->ahb_reset))
 411 +               return PTR_ERR(res->ahb_reset);
 412 +
 413 +       res->por_reset = devm_reset_control_get(dev, "por");
 414 +       if (IS_ERR(res->por_reset))
 415 +               return PTR_ERR(res->por_reset);
 416 +
 417 +       res->phy_reset = devm_reset_control_get(dev, "phy");
 418 +       if (IS_ERR(res->phy_reset))
 419 +               return PTR_ERR(res->phy_reset);
 420 +
 421 +       return 0;
 422 +}
 423 +
 424 +static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
 425 +{
 426 +       struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
 427 +       struct device *dev = pcie->dev;
 428 +
 429 +       res->vdda = devm_regulator_get(dev, "vdda");
 430 +       if (IS_ERR(res->vdda))
 431 +               return PTR_ERR(res->vdda);
 432 +
 433 +       res->iface = devm_clk_get(dev, "iface");
 434 +       if (IS_ERR(res->iface))
 435 +               return PTR_ERR(res->iface);
 436 +
 437 +       res->aux = devm_clk_get(dev, "aux");
 438 +       if (IS_ERR(res->aux) && PTR_ERR(res->aux) == -EPROBE_DEFER)
 439 +               return -EPROBE_DEFER;
 440 +       else if (IS_ERR(res->aux))
 441 +               res->aux = NULL;
 442 +
 443 +       res->master_bus = devm_clk_get(dev, "master_bus");
 444 +       if (IS_ERR(res->master_bus))
 445 +               return PTR_ERR(res->master_bus);
 446 +
 447 +       res->slave_bus = devm_clk_get(dev, "slave_bus");
 448 +       if (IS_ERR(res->slave_bus))
 449 +               return PTR_ERR(res->slave_bus);
 450 +
 451 +       res->core = devm_reset_control_get(dev, "core");
 452 +       if (IS_ERR(res->core))
 453 +               return PTR_ERR(res->core);
 454 +
 455 +       return 0;
 456 +}
 457 +
 458 +static int qcom_pcie_enable_link_training(struct pcie_port *pp)
 459 +{
 460 +       struct qcom_pcie *pcie = to_qcom_pcie(pp);
 461 +       struct device *dev = pp->dev;
 462 +       int retries;
 463 +       u32 val;
 464 +
 465 +       /* enable link training */
 466 +       writel_masked(pcie->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0));
 467 +
 468 +       /* wait for up to 100ms for the link to come up */
 469 +       retries = LINKUP_RETRIES_COUNT;
 470 +       do {
 471 +               val = readl(pcie->elbi + PCIE20_ELBI_SYS_STTS);
 472 +               if (val & XMLH_LINK_UP)
 473 +                       break;
 474 +               usleep_range(LINKUP_DELAY_MIN_US, LINKUP_DELAY_MAX_US);
 475 +       } while (retries--);
 476 +
 477 +       if (retries < 0 || !dw_pcie_link_up(pp)) {
 478 +               dev_err(dev, "link initialization failed\n");
 479 +               return -ENXIO;
 480 +       }
 481 +
 482 +       return 0;
 483 +}
 484 +
 485 +static void qcom_pcie_host_init_v1(struct pcie_port *pp)
 486 +{
 487 +       struct qcom_pcie *pcie = to_qcom_pcie(pp);
 488 +       int ret;
 489 +
 490 +       qcom_ep_reset_assert(pcie);
 491 +
 492 +       ret = qcom_pcie_enable_resources_v1(pcie);
 493 +       if (ret)
 494 +               return;
 495 +
 496 +       /* change DBI base address */
 497 +       writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 498 +
 499 +       if (IS_ENABLED(CONFIG_PCI_MSI))
 500 +               writel_masked(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,
 501 +                             0, BIT(31));
 502 +
 503 +       ret = phy_init(pcie->phy);
 504 +       if (ret)
 505 +               goto err_res;
 506 +
 507 +       ret = phy_power_on(pcie->phy);
 508 +       if (ret)
 509 +               goto err_phy;
 510 +
 511 +       dw_pcie_setup_rc(pp);
 512 +
 513 +       if (IS_ENABLED(CONFIG_PCI_MSI))
 514 +               dw_pcie_msi_init(pp);
 515 +
 516 +       qcom_ep_reset_deassert(pcie);
 517 +
 518 +       ret = qcom_pcie_enable_link_training(pp);
 519 +       if (ret)
 520 +               goto err;
 521 +
 522 +       return;
 523 +
 524 +err:
 525 +       qcom_ep_reset_assert(pcie);
 526 +       phy_power_off(pcie->phy);
 527 +err_phy:
 528 +       phy_exit(pcie->phy);
 529 +err_res:
 530 +       qcom_pcie_disable_resources_v1(pcie);
 531 +}
 532 +
 533 +static void qcom_pcie_host_init_v0(struct pcie_port *pp)
 534 +{
 535 +       struct qcom_pcie *pcie = to_qcom_pcie(pp);
 536 +       struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
 537 +       struct device *dev = pcie->dev;
 538 +       int ret;
 539 +
 540 +       qcom_ep_reset_assert(pcie);
 541 +
 542 +       ret = qcom_pcie_enable_resources_v0(pcie);
 543 +       if (ret)
 544 +               return;
 545 +
 546 +       writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
 547 +
 548 +       /* enable external reference clock */
 549 +       writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16));
 550 +
 551 +       ret = reset_control_deassert(res->phy_reset);
 552 +       if (ret) {
 553 +               dev_err(dev, "cannot deassert phy reset\n");
 554 +               return;
 555 +       }
 556 +
 557 +       ret = reset_control_deassert(res->pci_reset);
 558 +       if (ret) {
 559 +               dev_err(dev, "cannot deassert pci reset\n");
 560 +               return;
 561 +       }
 562 +
 563 +       ret = reset_control_deassert(res->por_reset);
 564 +       if (ret) {
 565 +               dev_err(dev, "cannot deassert por reset\n");
 566 +               return;
 567 +       }
 568 +
 569 +       ret = reset_control_deassert(res->axi_reset);
 570 +       if (ret) {
 571 +               dev_err(dev, "cannot deassert axi reset\n");
 572 +               return;
 573 +       }
 574 +
 575 +       /* wait 150ms for clock acquisition */
 576 +       usleep_range(10000, 15000);
 577 +
 578 +       dw_pcie_setup_rc(pp);
 579 +
 580 +       if (IS_ENABLED(CONFIG_PCI_MSI))
 581 +               dw_pcie_msi_init(pp);
 582 +
 583 +       qcom_ep_reset_deassert(pcie);
 584 +
 585 +       ret = qcom_pcie_enable_link_training(pp);
 586 +       if (ret)
 587 +               goto err;
 588 +
 589 +       return;
 590 +err:
 591 +       qcom_ep_reset_assert(pcie);
 592 +       qcom_pcie_disable_resources_v0(pcie);
 593 +}
 594 +
 595 +static void qcom_pcie_host_init(struct pcie_port *pp)
 596 +{
 597 +       struct qcom_pcie *pcie = to_qcom_pcie(pp);
 598 +
 599 +       if (pcie->version == PCIE_V0)
 600 +               return qcom_pcie_host_init_v0(pp);
 601 +       else
 602 +               return qcom_pcie_host_init_v1(pp);
 603 +}
 604 +
 605 +static int
 606 +qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val)
 607 +{
 608 +       /* the device class is not reported correctly from the register */
 609 +       if (where == PCI_CLASS_REVISION && size == 4) {
 610 +               *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
 611 +               *val &= ~(0xffff << 16);
 612 +               *val |= PCI_CLASS_BRIDGE_PCI << 16;
 613 +               return PCIBIOS_SUCCESSFUL;
 614 +       }
 615 +
 616 +       return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
 617 +                               size, val);
 618 +}
 619 +
 620 +static struct pcie_host_ops qcom_pcie_ops = {
 621 +       .link_up = qcom_pcie_link_up,
 622 +       .host_init = qcom_pcie_host_init,
 623 +       .rd_own_conf = qcom_pcie_rd_own_conf,
 624 +};
 625 +
 626 +static const struct of_device_id qcom_pcie_match[] = {
 627 +       { .compatible = "qcom,pcie-v0", .data = (void *)PCIE_V0 },
 628 +       { .compatible = "qcom,pcie-v1", .data = (void *)PCIE_V1 },
 629 +       { }
 630 +};
 631 +
 632 +static int qcom_pcie_probe(struct platform_device *pdev)
 633 +{
 634 +       struct device *dev = &pdev->dev;
 635 +       const struct of_device_id *match;
 636 +       struct resource *res;
 637 +       struct qcom_pcie *pcie;
 638 +       struct pcie_port *pp;
 639 +       int ret;
 640 +
 641 +       match = of_match_node(qcom_pcie_match, dev->of_node);
 642 +       if (!match)
 643 +               return -ENXIO;
 644 +
 645 +       pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 646 +       if (!pcie)
 647 +               return -ENOMEM;
 648 +
 649 +       pcie->version = (unsigned int)match->data;
 650 +
 651 +       pcie->reset = devm_gpiod_get_optional(dev, "perst");
 652 +       if (IS_ERR(pcie->reset) && PTR_ERR(pcie->reset) == -EPROBE_DEFER)
 653 +               return PTR_ERR(pcie->reset);
 654 +
 655 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
 656 +       pcie->parf = devm_ioremap_resource(dev, res);
 657 +       if (IS_ERR(pcie->parf))
 658 +               return PTR_ERR(pcie->parf);
 659 +
 660 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
 661 +       pcie->dbi = devm_ioremap_resource(dev, res);
 662 +       if (IS_ERR(pcie->dbi))
 663 +               return PTR_ERR(pcie->dbi);
 664 +
 665 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
 666 +       pcie->elbi = devm_ioremap_resource(dev, res);
 667 +       if (IS_ERR(pcie->elbi))
 668 +               return PTR_ERR(pcie->elbi);
 669 +
 670 +       pcie->phy = devm_phy_optional_get(dev, "pciephy");
 671 +       if (IS_ERR(pcie->phy))
 672 +               return PTR_ERR(pcie->phy);
 673 +
 674 +       pcie->dev = dev;
 675 +
 676 +       if (pcie->version == PCIE_V0)
 677 +               ret = qcom_pcie_get_resources_v0(pcie);
 678 +       else
 679 +               ret = qcom_pcie_get_resources_v1(pcie);
 680 +
 681 +       if (ret)
 682 +               return ret;
 683 +
 684 +       pp = &pcie->pp;
 685 +       pp->dev = dev;
 686 +       pp->dbi_base = pcie->dbi;
 687 +       pp->root_bus_nr = -1;
 688 +       pp->ops = &qcom_pcie_ops;
 689 +
 690 +       if (IS_ENABLED(CONFIG_PCI_MSI)) {
 691 +               pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 692 +               if (pp->msi_irq < 0) {
 693 +                       dev_err(dev, "cannot get msi irq\n");
 694 +                       return pp->msi_irq;
 695 +               }
 696 +
 697 +               ret = devm_request_irq(dev, pp->msi_irq,
 698 +                                      qcom_pcie_msi_irq_handler,
 699 +                                      IRQF_SHARED, "qcom-pcie-msi", pp);
 700 +               if (ret) {
 701 +                       dev_err(dev, "cannot request msi irq\n");
 702 +                       return ret;
 703 +               }
 704 +       }
 705 +
 706 +       ret = dw_pcie_host_init(pp);
 707 +       if (ret) {
 708 +               dev_err(dev, "cannot initialize host\n");
 709 +               return ret;
 710 +       }
 711 +
 712 +       platform_set_drvdata(pdev, pcie);
 713 +
 714 +       return 0;
 715 +}
 716 +
 717 +static int qcom_pcie_remove(struct platform_device *pdev)
 718 +{
 719 +       struct qcom_pcie *pcie = platform_get_drvdata(pdev);
 720 +
 721 +       qcom_ep_reset_assert(pcie);
 722 +       phy_power_off(pcie->phy);
 723 +       phy_exit(pcie->phy);
 724 +       if (pcie->version == PCIE_V0)
 725 +               qcom_pcie_disable_resources_v0(pcie);
 726 +       else
 727 +               qcom_pcie_disable_resources_v1(pcie);
 728 +
 729 +       return 0;
 730 +}
 731 +
 732 +static struct platform_driver qcom_pcie_driver = {
 733 +       .probe = qcom_pcie_probe,
 734 +       .remove = qcom_pcie_remove,
 735 +       .driver = {
 736 +               .name = "qcom-pcie",
 737 +               .of_match_table = qcom_pcie_match,
 738 +       },
 739 +};
 740 +
 741 +module_platform_driver(qcom_pcie_driver);
 742 +
 743 +MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
 744 +MODULE_DESCRIPTION("Qualcomm PCIe root complex driver");
 745 +MODULE_LICENSE("GPL v2");
 746 +MODULE_ALIAS("platform:qcom-pcie");
 747 --- a/drivers/pci/host/Makefile
 748 +++ b/drivers/pci/host/Makefile
 749 @@ -15,3 +15,4 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-laye
 750  obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 751  obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 752  obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 753 +obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o