target/linux/ipq806x/patches-4.14/0035-clk-mux-Split-out-register-accessors-for-reuse.patch

   1 From patchwork Fri Dec  8 09:42:20 2017
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   5 Subject: [v4,02/12] clk: mux: Split out register accessors for reuse
   6 From: Sricharan R <sricharan@codeaurora.org>
   7 X-Patchwork-Id: 10102103
   8 Message-Id: <1512726150-7204-3-git-send-email-sricharan@codeaurora.org>
   9 To: mturquette@baylibre.com, sboyd@codeaurora.org,
  10  devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
  11  linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
  12  viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
  13 Cc: sricharan@codeaurora.org
  14 Date: Fri,  8 Dec 2017 15:12:20 +0530
  15
  16 From: Stephen Boyd <sboyd@codeaurora.org>
  17
  18 We want to reuse the logic in clk-mux.c for other clock drivers
  19 that don't use readl as register accessors. Fortunately, there
  20 really isn't much to the mux code besides the table indirection
  21 and quirk flags if you assume any bit shifting and masking has
  22 been done already. Pull that logic out into reusable functions
  23 that operate on an optional table and some flags so that other
  24 drivers can use the same logic.
  25
  26 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  27 ---
  28  drivers/clk/clk-mux.c        | 75 +++++++++++++++++++++++++++-----------------
  29  include/linux/clk-provider.h |  9 ++++--
  30  2 files changed, 54 insertions(+), 30 deletions(-)
  31
  32 --- a/drivers/clk/clk-mux.c
  33 +++ b/drivers/clk/clk-mux.c
  34 @@ -26,35 +26,24 @@
  35   * parent - parent is adjustable through clk_set_parent
  36   */
  37
  38 -static u8 clk_mux_get_parent(struct clk_hw *hw)
  39 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
  40 +                               unsigned int *table, unsigned long flags)
  41  {
  42 -       struct clk_mux *mux = to_clk_mux(hw);
  43         int num_parents = clk_hw_get_num_parents(hw);
  44 -       u32 val;
  45 -
  46 -       /*
  47 -        * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  48 -        * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  49 -        * to 0x7 (index starts at one)
  50 -        * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  51 -        * val = 0x4 really means "bit 2, index starts at bit 0"
  52 -        */
  53 -       val = clk_readl(mux->reg) >> mux->shift;
  54 -       val &= mux->mask;
  55
  56 -       if (mux->table) {
  57 +       if (table) {
  58                 int i;
  59
  60                 for (i = 0; i < num_parents; i++)
  61 -                       if (mux->table[i] == val)
  62 +                       if (table[i] == val)
  63                                 return i;
  64                 return -EINVAL;
  65         }
  66
  67 -       if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  68 +       if (val && (flags & CLK_MUX_INDEX_BIT))
  69                 val = ffs(val) - 1;
  70
  71 -       if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  72 +       if (val && (flags & CLK_MUX_INDEX_ONE))
  73                 val--;
  74
  75         if (val >= num_parents)
  76 @@ -62,23 +51,53 @@ static u8 clk_mux_get_parent(struct clk_
  77
  78         return val;
  79  }
  80 +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
  81
  82 -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
  83 +static u8 _clk_mux_get_parent(struct clk_hw *hw)
  84  {
  85         struct clk_mux *mux = to_clk_mux(hw);
  86         u32 val;
  87 -       unsigned long flags = 0;
  88
  89 -       if (mux->table) {
  90 -               index = mux->table[index];
  91 +       /*
  92 +        * FIXME need a mux-specific flag to determine if val is bitwise or
  93 +        * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
  94 +        * but ranges from 0x1 to 0x7 (index starts at one)
  95 +        * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  96 +        * val = 0x4 really means "bit 2, index starts at bit 0"
  97 +        */
  98 +       val = clk_readl(mux->reg) >> mux->shift;
  99 +       val &= mux->mask;
 100 +
 101 +       return clk_mux_get_parent(hw, val, mux->table, mux->flags);
 102 +}
 103 +
 104 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
 105 +                            unsigned long flags)
 106 +{
 107 +       unsigned int val = index;
 108 +
 109 +       if (table) {
 110 +               val = table[val];
 111         } else {
 112 -               if (mux->flags & CLK_MUX_INDEX_BIT)
 113 -                       index = 1 << index;
 114 +               if (flags & CLK_MUX_INDEX_BIT)
 115 +                       val = 1 << index;
 116
 117 -               if (mux->flags & CLK_MUX_INDEX_ONE)
 118 -                       index++;
 119 +               if (flags & CLK_MUX_INDEX_ONE)
 120 +                       val++;
 121         }
 122
 123 +       return val;
 124 +}
 125 +EXPORT_SYMBOL_GPL(clk_mux_reindex);
 126 +
 127 +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 128 +{
 129 +       struct clk_mux *mux = to_clk_mux(hw);
 130 +       u32 val;
 131 +       unsigned long flags = 0;
 132 +
 133 +       index = clk_mux_reindex(index, mux->table, mux->flags);
 134 +
 135         if (mux->lock)
 136                 spin_lock_irqsave(mux->lock, flags);
 137         else
 138 @@ -110,14 +129,14 @@ static int clk_mux_determine_rate(struct
 139  }
 140
 141  const struct clk_ops clk_mux_ops = {
 142 -       .get_parent = clk_mux_get_parent,
 143 +       .get_parent = _clk_mux_get_parent,
 144         .set_parent = clk_mux_set_parent,
 145         .determine_rate = clk_mux_determine_rate,
 146  };
 147  EXPORT_SYMBOL_GPL(clk_mux_ops);
 148
 149  const struct clk_ops clk_mux_ro_ops = {
 150 -       .get_parent = clk_mux_get_parent,
 151 +       .get_parent = _clk_mux_get_parent,
 152  };
 153  EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
 154
 155 @@ -125,7 +144,7 @@ struct clk_hw *clk_hw_register_mux_table
 156                 const char * const *parent_names, u8 num_parents,
 157                 unsigned long flags,
 158                 void __iomem *reg, u8 shift, u32 mask,
 159 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock)
 160 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
 161  {
 162         struct clk_mux *mux;
 163         struct clk_hw *hw;
 164 --- a/include/linux/clk-provider.h
 165 +++ b/include/linux/clk-provider.h
 166 @@ -468,7 +468,7 @@ void clk_hw_unregister_divider(struct cl
 167  struct clk_mux {
 168         struct clk_hw   hw;
 169         void __iomem    *reg;
 170 -       u32             *table;
 171 +       unsigned int    *table;
 172         u32             mask;
 173         u8              shift;
 174         u8              flags;
 175 @@ -486,6 +486,11 @@ struct clk_mux {
 176  extern const struct clk_ops clk_mux_ops;
 177  extern const struct clk_ops clk_mux_ro_ops;
 178
 179 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
 180 +                               unsigned int *table, unsigned long flags);
 181 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
 182 +                            unsigned long flags);
 183 +
 184  struct clk *clk_register_mux(struct device *dev, const char *name,
 185                 const char * const *parent_names, u8 num_parents,
 186                 unsigned long flags,
 187 @@ -506,7 +511,7 @@ struct clk_hw *clk_hw_register_mux_table
 188                 const char * const *parent_names, u8 num_parents,
 189                 unsigned long flags,
 190                 void __iomem *reg, u8 shift, u32 mask,
 191 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 192 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
 193
 194  void clk_unregister_mux(struct clk *clk);
 195  void clk_hw_unregister_mux(struct clk_hw *hw);