a2ae1e064b8246b0f655c99a4c9dd0ef1dfb6b06
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.14 / 0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch
1 From 490d103232287eb51c92c49a4ef8865fd0a9d59e Mon Sep 17 00:00:00 2001
2 From: Sham Muthayyan <smuthayy@codeaurora.org>
3 Date: Tue, 19 Jul 2016 18:58:18 +0530
4 Subject: PCI: qcom: Fixed IPQ806x PCIE reset changes
5
6 Change-Id: Ia6590e960b9754b1e8b7a51f318788cd63e9e321
7 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
8 ---
9 drivers/pci/host/pcie-qcom.c | 24 +++++++++++++++++++-----
10 1 file changed, 19 insertions(+), 5 deletions(-)
11
12 --- a/drivers/pci/dwc/pcie-qcom.c
13 +++ b/drivers/pci/dwc/pcie-qcom.c
14 @@ -98,6 +98,7 @@
15 struct reset_control *ahb_reset;
16 struct reset_control *por_reset;
17 struct reset_control *phy_reset;
18 + struct reset_control *ext_reset;
19 struct regulator *vdda;
20 struct regulator *vdda_phy;
21 struct regulator *vdda_refclk;
22 @@ -275,6 +276,10 @@
23 if (IS_ERR(res->por_reset))
24 return PTR_ERR(res->por_reset);
25
26 + res->ext_reset = devm_reset_control_get(dev, "ext");
27 + if (IS_ERR(res->ext_reset))
28 + return PTR_ERR(res->ext_reset);
29 +
30 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
31 return PTR_ERR_OR_ZERO(res->phy_reset);
32 }
33 @@ -288,6 +293,7 @@
34 reset_control_assert(res->ahb_reset);
35 reset_control_assert(res->por_reset);
36 reset_control_assert(res->pci_reset);
37 + reset_control_assert(res->ext_reset);
38 clk_disable_unprepare(res->iface_clk);
39 clk_disable_unprepare(res->core_clk);
40 clk_disable_unprepare(res->phy_clk);
41 @@ -306,6 +312,12 @@
42 u32 val;
43 int ret;
44
45 + ret = reset_control_assert(res->ahb_reset);
46 + if (ret) {
47 + dev_err(dev, "cannot assert ahb reset\n");
48 + return ret;
49 + }
50 +
51 ret = regulator_enable(res->vdda);
52 if (ret) {
53 dev_err(dev, "cannot enable vdda regulator\n");
54 @@ -324,16 +336,16 @@
55 goto err_vdda_phy;
56 }
57
58 - ret = reset_control_assert(res->ahb_reset);
59 + ret = reset_control_deassert(res->ext_reset);
60 if (ret) {
61 - dev_err(dev, "cannot assert ahb reset\n");
62 - goto err_assert_ahb;
63 + dev_err(dev, "cannot assert ext reset\n");
64 + goto err_reset_ext;
65 }
66
67 ret = clk_prepare_enable(res->iface_clk);
68 if (ret) {
69 dev_err(dev, "cannot prepare/enable iface clock\n");
70 - goto err_assert_ahb;
71 + goto err_iface;
72 }
73
74 ret = clk_prepare_enable(res->core_clk);
75 @@ -422,7 +434,9 @@
76 clk_disable_unprepare(res->core_clk);
77 err_clk_core:
78 clk_disable_unprepare(res->iface_clk);
79 -err_assert_ahb:
80 +err_iface:
81 + reset_control_assert(res->ext_reset);
82 +err_reset_ext:
83 regulator_disable(res->vdda_phy);
84 err_vdda_phy:
85 regulator_disable(res->vdda_refclk);