target/linux/ipq806x/patches-4.14/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch

   1 From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001
   2 From: Sham Muthayyan <smuthayy@codeaurora.org>
   3 Date: Tue, 26 Jul 2016 12:28:31 +0530
   4 Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x
   5
   6 Resolved PCIE EP detection errors caused due to missing iATU programming.
   7
   8 Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe
   9 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  10 ---
  11  drivers/pci/host/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++++++++++++++
  12  1 file changed, 77 insertions(+)
  13
  14 --- a/drivers/pci/dwc/pcie-qcom.c
  15 +++ b/drivers/pci/dwc/pcie-qcom.c
  16 @@ -83,6 +83,30 @@
  17  #define PCIE20_CAP_LINK_1                      (PCIE20_CAP + 0x14)
  18  #define PCIE_CAP_LINK1_VAL                     0x2FD7F
  19
  20 +#define PCIE20_CAP_LINKCTRLSTATUS              (PCIE20_CAP + 0x10)
  21 +
  22 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0                0x818
  23 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1                0x81c
  24 +
  25 +#define PCIE20_PLR_IATU_VIEWPORT               0x900
  26 +#define PCIE20_PLR_IATU_REGION_OUTBOUND                (0x0 << 31)
  27 +#define PCIE20_PLR_IATU_REGION_INDEX(x)                (x << 0)
  28 +
  29 +#define PCIE20_PLR_IATU_CTRL1                  0x904
  30 +#define PCIE20_PLR_IATU_TYPE_CFG0              (0x4 << 0)
  31 +#define PCIE20_PLR_IATU_TYPE_MEM               (0x0 << 0)
  32 +
  33 +#define PCIE20_PLR_IATU_CTRL2                  0x908
  34 +#define PCIE20_PLR_IATU_ENABLE                 BIT(31)
  35 +
  36 +#define PCIE20_PLR_IATU_LBAR                   0x90C
  37 +#define PCIE20_PLR_IATU_UBAR                   0x910
  38 +#define PCIE20_PLR_IATU_LAR                    0x914
  39 +#define PCIE20_PLR_IATU_LTAR                   0x918
  40 +#define PCIE20_PLR_IATU_UTAR                   0x91c
  41 +
  42 +#define MSM_PCIE_DEV_CFG_ADDR                  0x01000000
  43 +
  44  #define PCIE20_PARF_Q2A_FLUSH                  0x1AC
  45
  46  #define PCIE20_MISC_CONTROL_1_REG              0x8BC
  47 @@ -251,6 +275,57 @@
  48         writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
  49  }
  50
  51 +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
  52 +{
  53 +       struct pcie_port *pp = &pcie->pci->pp;
  54 +
  55 +       /*
  56 +        * program and enable address translation region 0 (device config
  57 +        * address space); region type config;
  58 +        * axi config address range to device config address range
  59 +        */
  60 +       writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
  61 +              PCIE20_PLR_IATU_REGION_INDEX(0),
  62 +              pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT);
  63 +
  64 +       writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1);
  65 +       writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2);
  66 +       writel(pp->cfg0_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR);
  67 +       writel((pp->cfg0_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR);
  68 +       writel((pp->cfg0_base + pp->cfg0_size - 1),
  69 +              pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR);
  70 +       writel(busdev, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR);
  71 +       writel(0, pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR);
  72 +}
  73 +
  74 +static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
  75 +{
  76 +       struct pcie_port *pp = &pcie->pci->pp;
  77 +
  78 +       /*
  79 +        * program and enable address translation region 2 (device resource
  80 +        * address space); region type memory;
  81 +        * axi device bar address range to device bar address range
  82 +        */
  83 +       writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
  84 +              PCIE20_PLR_IATU_REGION_INDEX(2),
  85 +              pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT);
  86 +
  87 +       writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1);
  88 +       writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2);
  89 +       writel(pp->mem_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR);
  90 +       writel((pp->mem_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR);
  91 +       writel(pp->mem_base + pp->mem_size - 1,
  92 +              pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR);
  93 +       writel(pp->mem_bus_addr, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR);
  94 +       writel(upper_32_bits(pp->mem_bus_addr),
  95 +              pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR);
  96 +
  97 +       /* 256B PCIE buffer setting */
  98 +       writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
  99 +       writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 100 +}
 101 +
 102  static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 103  {
 104         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 105 @@ -465,6 +538,9 @@
 106         writel(CFG_BRIDGE_SB_INIT,
 107                pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 108
 109 +       qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
 110 +       qcom_pcie_prog_viewport_mem2_outbound(pcie);
 111 +
 112         return 0;
 113
 114  err_deassert_ahb: