4bba0ac557c5356f0ee0e11a061bf4a2510786b4
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.4 / 100-usb-phy-Add-Qualcomm-DWC3-HS-SS-PHY-drivers.patch
1 --- a/drivers/phy/Kconfig
2 +++ b/drivers/phy/Kconfig
3 @@ -390,4 +390,15 @@ config PHY_CYGNUS_PCIE
4 Enable this to support the Broadcom Cygnus PCIe PHY.
5 If unsure, say N.
6
7 +config PHY_QCOM_DWC3
8 + tristate "QCOM DWC3 USB PHY support"
9 + depends on ARCH_QCOM
10 + depends on HAS_IOMEM
11 + depends on OF
12 + select GENERIC_PHY
13 + help
14 + This option enables support for the Synopsis PHYs present inside the
15 + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
16 + PHY controllers.
17 +
18 endmenu
19 --- a/drivers/phy/Makefile
20 +++ b/drivers/phy/Makefile
21 @@ -48,3 +48,4 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1
22 obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
23 obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
24 obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
25 +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
26 --- /dev/null
27 +++ b/drivers/phy/phy-qcom-dwc3.c
28 @@ -0,0 +1,482 @@
29 +/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved.
30 + *
31 + * This program is free software; you can redistribute it and/or modify
32 + * it under the terms of the GNU General Public License version 2 and
33 + * only version 2 as published by the Free Software Foundation.
34 + *
35 + * This program is distributed in the hope that it will be useful,
36 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 + * GNU General Public License for more details.
39 + */
40 +
41 +#include <linux/clk.h>
42 +#include <linux/err.h>
43 +#include <linux/io.h>
44 +#include <linux/module.h>
45 +#include <linux/of.h>
46 +#include <linux/phy/phy.h>
47 +#include <linux/platform_device.h>
48 +#include <linux/delay.h>
49 +
50 +/**
51 + * USB QSCRATCH Hardware registers
52 + */
53 +#define QSCRATCH_GENERAL_CFG (0x08)
54 +#define HSUSB_PHY_CTRL_REG (0x10)
55 +
56 +/* PHY_CTRL_REG */
57 +#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
58 +#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
59 +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
60 +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
61 +#define HSUSB_CTRL_USE_CLKCORE BIT(18)
62 +#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
63 +#define HSUSB_CTRL_COMMONONN BIT(11)
64 +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
65 +#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
66 +#define HSUSB_CTRL_CLAMP_EN BIT(7)
67 +#define HSUSB_CTRL_RETENABLEN BIT(1)
68 +#define HSUSB_CTRL_POR BIT(0)
69 +
70 +/* QSCRATCH_GENERAL_CFG */
71 +#define HSUSB_GCFG_XHCI_REV BIT(2)
72 +
73 +/**
74 + * USB QSCRATCH Hardware registers
75 + */
76 +#define SSUSB_PHY_CTRL_REG (0x00)
77 +#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
78 +#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
79 +#define CR_PROTOCOL_DATA_IN_REG (0x0c)
80 +#define CR_PROTOCOL_DATA_OUT_REG (0x10)
81 +#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
82 +#define CR_PROTOCOL_CAP_DATA_REG (0x18)
83 +#define CR_PROTOCOL_READ_REG (0x1c)
84 +#define CR_PROTOCOL_WRITE_REG (0x20)
85 +
86 +/* PHY_CTRL_REG */
87 +#define SSUSB_CTRL_REF_USE_PAD BIT(28)
88 +#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
89 +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
90 +#define SSUSB_CTRL_SS_PHY_EN BIT(8)
91 +#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
92 +
93 +/* SSPHY control registers */
94 +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
95 +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane)
96 +
97 +/* RX OVRD IN HI bits */
98 +#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
99 +#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
100 +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
101 +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700
102 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8
103 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
104 +#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
105 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
106 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018
107 +#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
108 +#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003
109 +
110 +/* TX OVRD DRV LO register bits */
111 +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F
112 +#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80
113 +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
114 +#define TX_OVRD_DRV_LO_EN BIT(14)
115 +
116 +struct qcom_dwc3_usb_phy {
117 + void __iomem *base;
118 + struct device *dev;
119 + struct phy *phy;
120 +
121 + int (*phy_init)(struct qcom_dwc3_usb_phy *phy_dwc3);
122 + int (*phy_exit)(struct qcom_dwc3_usb_phy *phy_dwc3);
123 +
124 + struct clk *xo_clk;
125 + struct clk *ref_clk;
126 +};
127 +
128 +/**
129 + * Write register and read back masked value to confirm it is written
130 + *
131 + * @base - QCOM DWC3 PHY base virtual address.
132 + * @offset - register offset.
133 + * @mask - register bitmask specifying what should be updated
134 + * @val - value to write.
135 + */
136 +static inline void qcom_dwc3_phy_write_readback(
137 + struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
138 + const u32 mask, u32 val)
139 +{
140 + u32 write_val, tmp = readl(phy_dwc3->base + offset);
141 +
142 + tmp &= ~mask; /* retain other bits */
143 + write_val = tmp | val;
144 +
145 + writel(write_val, phy_dwc3->base + offset);
146 +
147 + /* Read back to see if val was written */
148 + tmp = readl(phy_dwc3->base + offset);
149 + tmp &= mask; /* clear other bits */
150 +
151 + if (tmp != val)
152 + dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
153 + val, offset);
154 +}
155 +
156 +static int wait_for_latch(void __iomem *addr)
157 +{
158 + u32 retry = 10;
159 +
160 + while (true) {
161 + if (!readl(addr))
162 + break;
163 +
164 + if (--retry == 0)
165 + return -ETIMEDOUT;
166 +
167 + usleep_range(10, 20);
168 + }
169 +
170 + return 0;
171 +}
172 +
173 +/**
174 + * Write SSPHY register
175 + *
176 + * @base - QCOM DWC3 PHY base virtual address.
177 + * @addr - SSPHY address to write.
178 + * @val - value to write.
179 + */
180 +static int qcom_dwc3_ss_write_phycreg(void __iomem *base, u32 addr, u32 val)
181 +{
182 + int ret;
183 +
184 + writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
185 + writel(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
186 +
187 + ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG);
188 + if (ret)
189 + goto err_wait;
190 +
191 + writel(val, base + CR_PROTOCOL_DATA_IN_REG);
192 + writel(0x1, base + CR_PROTOCOL_CAP_DATA_REG);
193 +
194 + ret = wait_for_latch(base + CR_PROTOCOL_CAP_DATA_REG);
195 + if (ret)
196 + goto err_wait;
197 +
198 + writel(0x1, base + CR_PROTOCOL_WRITE_REG);
199 +
200 + ret = wait_for_latch(base + CR_PROTOCOL_WRITE_REG);
201 +
202 +err_wait:
203 + return ret;
204 +}
205 +
206 +/**
207 + * Read SSPHY register.
208 + *
209 + * @base - QCOM DWC3 PHY base virtual address.
210 + * @addr - SSPHY address to read.
211 + */
212 +static int qcom_dwc3_ss_read_phycreg(void __iomem *base, u32 addr, u32 *val)
213 +{
214 + int ret;
215 + bool first_read = true;
216 +
217 + writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
218 + writel(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
219 +
220 + ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG);
221 + if (ret)
222 + goto err_wait;
223 +
224 + /*
225 + * Due to hardware bug, first read of SSPHY register might be
226 + * incorrect. Hence as workaround, SW should perform SSPHY register
227 + * read twice, but use only second read and ignore first read.
228 + */
229 +retry:
230 + writel(0x1, base + CR_PROTOCOL_READ_REG);
231 +
232 + ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
233 + if (ret)
234 + goto err_wait;
235 +
236 + if (first_read) {
237 + readl(base + CR_PROTOCOL_DATA_OUT_REG);
238 + first_read = false;
239 + goto retry;
240 + }
241 +
242 + *val = readl(base + CR_PROTOCOL_DATA_OUT_REG);
243 +
244 +err_wait:
245 + return ret;
246 +}
247 +
248 +static int qcom_dwc3_phy_power_on(struct phy *phy)
249 +{
250 + int ret;
251 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
252 +
253 + ret = clk_prepare_enable(phy_dwc3->xo_clk);
254 + if (ret)
255 + return ret;
256 +
257 + ret = clk_prepare_enable(phy_dwc3->ref_clk);
258 + if (ret)
259 + clk_disable_unprepare(phy_dwc3->xo_clk);
260 +
261 + return ret;
262 +}
263 +
264 +static int qcom_dwc3_phy_power_off(struct phy *phy)
265 +{
266 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
267 +
268 + clk_disable_unprepare(phy_dwc3->ref_clk);
269 + clk_disable_unprepare(phy_dwc3->xo_clk);
270 +
271 + return 0;
272 +}
273 +
274 +static int qcom_dwc3_hs_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3)
275 +{
276 + u32 val;
277 +
278 + /*
279 + * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
280 + * enable clamping, and disable RETENTION (power-on default is ENABLED)
281 + */
282 + val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
283 + HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
284 + HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
285 + HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
286 + HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
287 +
288 + /* use core clock if external reference is not present */
289 + if (!phy_dwc3->xo_clk)
290 + val |= HSUSB_CTRL_USE_CLKCORE;
291 +
292 + writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
293 + usleep_range(2000, 2200);
294 +
295 + /* Disable (bypass) VBUS and ID filters */
296 + writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
297 +
298 + return 0;
299 +}
300 +
301 +static int qcom_dwc3_ss_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3)
302 +{
303 + int ret;
304 + u32 data = 0;
305 +
306 + /* reset phy */
307 + data = readl_relaxed(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
308 + writel_relaxed(data | SSUSB_CTRL_SS_PHY_RESET,
309 + phy_dwc3->base + SSUSB_PHY_CTRL_REG);
310 + usleep_range(2000, 2200);
311 + writel_relaxed(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
312 +
313 + /* clear REF_PAD if we don't have XO clk */
314 + if (!phy_dwc3->xo_clk)
315 + data &= ~SSUSB_CTRL_REF_USE_PAD;
316 + else
317 + data |= SSUSB_CTRL_REF_USE_PAD;
318 +
319 + writel_relaxed(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
320 + msleep(30);
321 +
322 + data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
323 + writel_relaxed(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
324 +
325 + /*
326 + * Fix RX Equalization setting as follows
327 + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
328 + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
329 + * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
330 + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
331 + */
332 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
333 + SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
334 + if (ret)
335 + goto err_phy_trans;
336 +
337 + data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
338 + data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
339 + data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
340 + data |= 0x3 << RX_OVRD_IN_HI_RX_EQ_SHIFT;
341 + data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
342 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3->base,
343 + SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
344 + if (ret)
345 + goto err_phy_trans;
346 +
347 + /*
348 + * Set EQ and TX launch amplitudes as follows
349 + * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
350 + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
351 + * LANE0.TX_OVRD_DRV_LO.EN set to 1.
352 + */
353 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
354 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
355 + if (ret)
356 + goto err_phy_trans;
357 +
358 + data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
359 + data |= 0x16 << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
360 + data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
361 + data |= 0x7f;
362 + data |= TX_OVRD_DRV_LO_EN;
363 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3->base,
364 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
365 + if (ret)
366 + goto err_phy_trans;
367 +
368 + /*
369 + * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
370 + * TX_FULL_SWING [26:20] amplitude to 127
371 + * TX_DEEMPH_3_5DB [13:8] to 22
372 + * LOS_BIAS [2:0] to 0x5
373 + */
374 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
375 + 0x07f03f07, 0x07f01605);
376 +
377 +err_phy_trans:
378 + return ret;
379 +}
380 +
381 +static int qcom_dwc3_ss_phy_exit(struct qcom_dwc3_usb_phy *phy_dwc3)
382 +{
383 + /* Sequence to put SSPHY in low power state:
384 + * 1. Clear REF_PHY_EN in PHY_CTRL_REG
385 + * 2. Clear REF_USE_PAD in PHY_CTRL_REG
386 + * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
387 + * 4. Disable SSPHY ref clk
388 + */
389 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
390 + SSUSB_CTRL_SS_PHY_EN, 0x0);
391 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
392 + SSUSB_CTRL_REF_USE_PAD, 0x0);
393 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
394 + 0x0, SSUSB_CTRL_TEST_POWERDOWN);
395 +
396 + return 0;
397 +}
398 +
399 +static int qcom_dwc3_phy_init(struct phy *phy)
400 +{
401 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
402 +
403 + if (phy_dwc3->phy_init)
404 + return phy_dwc3->phy_init(phy_dwc3);
405 +
406 + return 0;
407 +}
408 +
409 +static int qcom_dwc3_phy_exit(struct phy *phy)
410 +{
411 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
412 +
413 + if (phy_dwc3->phy_exit)
414 + return qcom_dwc3_ss_phy_exit(phy_dwc3);
415 +
416 + return 0;
417 +}
418 +
419 +static struct phy_ops qcom_dwc3_phy_ops = {
420 + .init = qcom_dwc3_phy_init,
421 + .exit = qcom_dwc3_phy_exit,
422 + .power_on = qcom_dwc3_phy_power_on,
423 + .power_off = qcom_dwc3_phy_power_off,
424 + .owner = THIS_MODULE,
425 +};
426 +
427 +static const struct of_device_id qcom_dwc3_phy_table[] = {
428 + { .compatible = "qcom,dwc3-hs-usb-phy", },
429 + { .compatible = "qcom,dwc3-ss-usb-phy", },
430 + { /* Sentinel */ }
431 +};
432 +MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
433 +
434 +static int qcom_dwc3_phy_probe(struct platform_device *pdev)
435 +{
436 + struct qcom_dwc3_usb_phy *phy_dwc3;
437 + struct phy_provider *phy_provider;
438 + struct resource *res;
439 +
440 + phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
441 + if (!phy_dwc3)
442 + return -ENOMEM;
443 +
444 + platform_set_drvdata(pdev, phy_dwc3);
445 +
446 + phy_dwc3->dev = &pdev->dev;
447 +
448 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
449 + phy_dwc3->base = devm_ioremap_resource(phy_dwc3->dev, res);
450 + if (IS_ERR(phy_dwc3->base))
451 + return PTR_ERR(phy_dwc3->base);
452 +
453 + phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
454 + if (IS_ERR(phy_dwc3->ref_clk)) {
455 + dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
456 + return PTR_ERR(phy_dwc3->ref_clk);
457 + }
458 +
459 + if (of_device_is_compatible(pdev->dev.of_node,
460 + "qcom,dwc3-hs-usb-phy")) {
461 + clk_set_rate(phy_dwc3->ref_clk, 60000000);
462 + phy_dwc3->phy_init = qcom_dwc3_hs_phy_init;
463 + } else if (of_device_is_compatible(pdev->dev.of_node,
464 + "qcom,dwc3-ss-usb-phy")) {
465 + phy_dwc3->phy_init = qcom_dwc3_ss_phy_init;
466 + phy_dwc3->phy_exit = qcom_dwc3_ss_phy_exit;
467 + clk_set_rate(phy_dwc3->ref_clk, 125000000);
468 + } else {
469 + dev_err(phy_dwc3->dev, "Unknown phy\n");
470 + return -EINVAL;
471 + }
472 +
473 + phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
474 + if (IS_ERR(phy_dwc3->xo_clk)) {
475 + dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
476 + phy_dwc3->xo_clk = NULL;
477 + }
478 +
479 + phy_dwc3->phy = devm_phy_create(phy_dwc3->dev, NULL, &qcom_dwc3_phy_ops);
480 +
481 + if (IS_ERR(phy_dwc3->phy))
482 + return PTR_ERR(phy_dwc3->phy);
483 +
484 + phy_set_drvdata(phy_dwc3->phy, phy_dwc3);
485 +
486 + phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
487 + of_phy_simple_xlate);
488 +
489 + if (IS_ERR(phy_provider))
490 + return PTR_ERR(phy_provider);
491 +
492 + return 0;
493 +}
494 +
495 +static struct platform_driver qcom_dwc3_phy_driver = {
496 + .probe = qcom_dwc3_phy_probe,
497 + .driver = {
498 + .name = "qcom-dwc3-usb-phy",
499 + .owner = THIS_MODULE,
500 + .of_match_table = qcom_dwc3_phy_table,
501 + },
502 +};
503 +
504 +module_platform_driver(qcom_dwc3_phy_driver);
505 +
506 +MODULE_ALIAS("platform:phy-qcom-dwc3");
507 +MODULE_LICENSE("GPL v2");
508 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
509 +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
510 +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");