ipq806x: sync with latest patches sent by QCA
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.4 / 100-usb-phy-Add-Qualcomm-DWC3-HS-SS-PHY-drivers.patch
1 --- a/drivers/phy/Kconfig
2 +++ b/drivers/phy/Kconfig
3 @@ -390,4 +390,15 @@
4 Enable this to support the Broadcom Cygnus PCIe PHY.
5 If unsure, say N.
6
7 +config PHY_QCOM_DWC3
8 + tristate "QCOM DWC3 USB PHY support"
9 + depends on ARCH_QCOM
10 + depends on HAS_IOMEM
11 + depends on OF
12 + select GENERIC_PHY
13 + help
14 + This option enables support for the Synopsis PHYs present inside the
15 + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
16 + PHY controllers.
17 +
18 endmenu
19 --- a/drivers/phy/Makefile
20 +++ b/drivers/phy/Makefile
21 @@ -48,3 +48,4 @@ obj-$(CONFIG_PHY_TUSB1210) +=
22 obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
23 obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
24 obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
25 +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
26 --- /dev/null
27 +++ b/drivers/phy/phy-qcom-dwc3.c
28 @@ -0,0 +1,484 @@
29 +/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
30 + *
31 + * This program is free software; you can redistribute it and/or modify
32 + * it under the terms of the GNU General Public License version 2 and
33 + * only version 2 as published by the Free Software Foundation.
34 + *
35 +* This program is distributed in the hope that it will be useful,
36 +* but WITHOUT ANY WARRANTY; without even the implied warranty of
37 +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 +* GNU General Public License for more details.
39 +*/
40 +
41 +#include <linux/clk.h>
42 +#include <linux/err.h>
43 +#include <linux/io.h>
44 +#include <linux/module.h>
45 +#include <linux/of.h>
46 +#include <linux/phy/phy.h>
47 +#include <linux/platform_device.h>
48 +#include <linux/delay.h>
49 +
50 +/**
51 + * USB QSCRATCH Hardware registers
52 + */
53 +#define QSCRATCH_GENERAL_CFG (0x08)
54 +#define HSUSB_PHY_CTRL_REG (0x10)
55 +
56 +/* PHY_CTRL_REG */
57 +#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
58 +#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
59 +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
60 +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
61 +#define HSUSB_CTRL_USE_CLKCORE BIT(18)
62 +#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
63 +#define HSUSB_CTRL_COMMONONN BIT(11)
64 +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
65 +#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
66 +#define HSUSB_CTRL_CLAMP_EN BIT(7)
67 +#define HSUSB_CTRL_RETENABLEN BIT(1)
68 +#define HSUSB_CTRL_POR BIT(0)
69 +
70 +/* QSCRATCH_GENERAL_CFG */
71 +#define HSUSB_GCFG_XHCI_REV BIT(2)
72 +
73 +/**
74 + * USB QSCRATCH Hardware registers
75 + */
76 +#define SSUSB_PHY_CTRL_REG (0x00)
77 +#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
78 +#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
79 +#define CR_PROTOCOL_DATA_IN_REG (0x0c)
80 +#define CR_PROTOCOL_DATA_OUT_REG (0x10)
81 +#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
82 +#define CR_PROTOCOL_CAP_DATA_REG (0x18)
83 +#define CR_PROTOCOL_READ_REG (0x1c)
84 +#define CR_PROTOCOL_WRITE_REG (0x20)
85 +
86 +/* PHY_CTRL_REG */
87 +#define SSUSB_CTRL_REF_USE_PAD BIT(28)
88 +#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
89 +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
90 +#define SSUSB_CTRL_SS_PHY_EN BIT(8)
91 +#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
92 +
93 +/* SSPHY control registers */
94 +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
95 +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane)
96 +
97 +/* RX OVRD IN HI bits */
98 +#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
99 +#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
100 +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
101 +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700
102 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8
103 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
104 +#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
105 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
106 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018
107 +#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
108 +#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003
109 +
110 +/* TX OVRD DRV LO register bits */
111 +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F
112 +#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80
113 +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
114 +#define TX_OVRD_DRV_LO_EN BIT(14)
115 +
116 +/* SS CAP register bits */
117 +#define SS_CR_CAP_ADDR_REG BIT(0)
118 +#define SS_CR_CAP_DATA_REG BIT(0)
119 +#define SS_CR_READ_REG BIT(0)
120 +#define SS_CR_WRITE_REG BIT(0)
121 +
122 +struct qcom_dwc3_usb_phy {
123 + void __iomem *base;
124 + struct device *dev;
125 + struct clk *xo_clk;
126 + struct clk *ref_clk;
127 +};
128 +
129 +struct qcom_dwc3_phy_drvdata {
130 + struct phy_ops ops;
131 + u32 clk_rate;
132 +};
133 +
134 +/**
135 + * Write register and read back masked value to confirm it is written
136 + *
137 + * @base - QCOM DWC3 PHY base virtual address.
138 + * @offset - register offset.
139 + * @mask - register bitmask specifying what should be updated
140 + * @val - value to write.
141 + */
142 +static inline void qcom_dwc3_phy_write_readback(
143 + struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
144 + const u32 mask, u32 val)
145 +{
146 + u32 write_val, tmp = readl(phy_dwc3->base + offset);
147 +
148 + tmp &= ~mask; /* retain other bits */
149 + write_val = tmp | val;
150 +
151 + writel(write_val, phy_dwc3->base + offset);
152 +
153 + /* Read back to see if val was written */
154 + tmp = readl(phy_dwc3->base + offset);
155 + tmp &= mask; /* clear other bits */
156 +
157 + if (tmp != val)
158 + dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
159 + val, offset);
160 +}
161 +
162 +static int wait_for_latch(void __iomem *addr)
163 +{
164 + u32 retry = 10;
165 +
166 + while (true) {
167 + if (!readl(addr))
168 + break;
169 +
170 + if (--retry == 0)
171 + return -ETIMEDOUT;
172 +
173 + usleep_range(10, 20);
174 + }
175 +
176 + return 0;
177 +}
178 +
179 +/**
180 + * Write SSPHY register
181 + *
182 + * @base - QCOM DWC3 PHY base virtual address.
183 + * @addr - SSPHY address to write.
184 + * @val - value to write.
185 + */
186 +static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3,
187 + u32 addr, u32 val)
188 +{
189 + int ret;
190 +
191 + writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
192 + writel(SS_CR_CAP_ADDR_REG, phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
193 +
194 + ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
195 + if (ret)
196 + goto err_wait;
197 +
198 + writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
199 + writel(SS_CR_CAP_DATA_REG, phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
200 +
201 + ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
202 + if (ret)
203 + goto err_wait;
204 +
205 + writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
206 +
207 + ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
208 +
209 +err_wait:
210 + if (ret)
211 + dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
212 + return ret;
213 +}
214 +
215 +/**
216 + * Read SSPHY register.
217 + *
218 + * @base - QCOM DWC3 PHY base virtual address.
219 + * @addr - SSPHY address to read.
220 + */
221 +static int qcom_dwc3_ss_read_phycreg(void __iomem *base, u32 addr, u32 *val)
222 +{
223 + int ret;
224 +
225 + writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
226 + writel(SS_CR_CAP_ADDR_REG, base + CR_PROTOCOL_CAP_ADDR_REG);
227 +
228 + ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG);
229 + if (ret)
230 + goto err_wait;
231 +
232 + /*
233 + * Due to hardware bug, first read of SSPHY register might be
234 + * incorrect. Hence as workaround, SW should perform SSPHY register
235 + * read twice, but use only second read and ignore first read.
236 + */
237 + writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
238 +
239 + ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
240 + if (ret)
241 + goto err_wait;
242 +
243 + /* throwaway read */
244 + readl(base + CR_PROTOCOL_DATA_OUT_REG);
245 +
246 + writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
247 +
248 + ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
249 + if (ret)
250 + goto err_wait;
251 +
252 + *val = readl(base + CR_PROTOCOL_DATA_OUT_REG);
253 +
254 +err_wait:
255 + return ret;
256 +}
257 +
258 +static int qcom_dwc3_phy_power_on(struct phy *phy)
259 +{
260 + int ret;
261 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
262 +
263 + ret = clk_prepare_enable(phy_dwc3->xo_clk);
264 + if (ret)
265 + return ret;
266 +
267 + ret = clk_prepare_enable(phy_dwc3->ref_clk);
268 + if (ret)
269 + clk_disable_unprepare(phy_dwc3->xo_clk);
270 +
271 + return ret;
272 +}
273 +
274 +static int qcom_dwc3_phy_power_off(struct phy *phy)
275 +{
276 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
277 +
278 + clk_disable_unprepare(phy_dwc3->ref_clk);
279 + clk_disable_unprepare(phy_dwc3->xo_clk);
280 +
281 + return 0;
282 +}
283 +
284 +static int qcom_dwc3_hs_phy_init(struct phy *phy)
285 +{
286 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
287 + u32 val;
288 +
289 + /*
290 + * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
291 + * enable clamping, and disable RETENTION (power-on default is ENABLED)
292 + */
293 + val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
294 + HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
295 + HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
296 + HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
297 + HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
298 +
299 + /* use core clock if external reference is not present */
300 + if (!phy_dwc3->xo_clk)
301 + val |= HSUSB_CTRL_USE_CLKCORE;
302 +
303 + writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
304 + usleep_range(2000, 2200);
305 +
306 + /* Disable (bypass) VBUS and ID filters */
307 + writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
308 +
309 + return 0;
310 +}
311 +
312 +static int qcom_dwc3_ss_phy_init(struct phy *phy)
313 +{
314 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
315 + int ret;
316 + u32 data = 0;
317 +
318 + /* reset phy */
319 + data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
320 + writel(data | SSUSB_CTRL_SS_PHY_RESET,
321 + phy_dwc3->base + SSUSB_PHY_CTRL_REG);
322 + usleep_range(2000, 2200);
323 + writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
324 +
325 + /* clear REF_PAD if we don't have XO clk */
326 + if (!phy_dwc3->xo_clk)
327 + data &= ~SSUSB_CTRL_REF_USE_PAD;
328 + else
329 + data |= SSUSB_CTRL_REF_USE_PAD;
330 +
331 + writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
332 +
333 + /* wait for ref clk to become stable, this can take up to 30ms */
334 + msleep(30);
335 +
336 + data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
337 + writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
338 +
339 + /*
340 + * Fix RX Equalization setting as follows
341 + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
342 + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
343 + * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
344 + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
345 + */
346 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
347 + SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
348 + if (ret)
349 + goto err_phy_trans;
350 +
351 + data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
352 + data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
353 + data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
354 + data |= 0x3 << RX_OVRD_IN_HI_RX_EQ_SHIFT;
355 + data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
356 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
357 + SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
358 + if (ret)
359 + goto err_phy_trans;
360 +
361 + /*
362 + * Set EQ and TX launch amplitudes as follows
363 + * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
364 + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
365 + * LANE0.TX_OVRD_DRV_LO.EN set to 1.
366 + */
367 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
368 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
369 + if (ret)
370 + goto err_phy_trans;
371 +
372 + data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
373 + data |= 0x16 << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
374 + data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
375 + data |= 0x7f;
376 + data |= TX_OVRD_DRV_LO_EN;
377 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
378 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
379 + if (ret)
380 + goto err_phy_trans;
381 +
382 + /*
383 + * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
384 + * TX_FULL_SWING [26:20] amplitude to 127
385 + * TX_DEEMPH_3_5DB [13:8] to 22
386 + * LOS_BIAS [2:0] to 0x5
387 + */
388 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
389 + 0x07f03f07, 0x07f01605);
390 +
391 +err_phy_trans:
392 + return ret;
393 +}
394 +
395 +static int qcom_dwc3_ss_phy_exit(struct phy *phy)
396 +{
397 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
398 +
399 + /* Sequence to put SSPHY in low power state:
400 + * 1. Clear REF_PHY_EN in PHY_CTRL_REG
401 + * 2. Clear REF_USE_PAD in PHY_CTRL_REG
402 + * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
403 + */
404 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
405 + SSUSB_CTRL_SS_PHY_EN, 0x0);
406 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
407 + SSUSB_CTRL_REF_USE_PAD, 0x0);
408 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
409 + 0x0, SSUSB_CTRL_TEST_POWERDOWN);
410 +
411 + return 0;
412 +}
413 +
414 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
415 + .ops = {
416 + .init = qcom_dwc3_hs_phy_init,
417 + .power_on = qcom_dwc3_phy_power_on,
418 + .power_off = qcom_dwc3_phy_power_off,
419 + .owner = THIS_MODULE,
420 + },
421 + .clk_rate = 60000000,
422 +};
423 +
424 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = {
425 + .ops = {
426 + .init = qcom_dwc3_ss_phy_init,
427 + .exit = qcom_dwc3_ss_phy_exit,
428 + .power_on = qcom_dwc3_phy_power_on,
429 + .power_off = qcom_dwc3_phy_power_off,
430 + .owner = THIS_MODULE,
431 + },
432 + .clk_rate = 125000000,
433 +};
434 +
435 +static const struct of_device_id qcom_dwc3_phy_table[] = {
436 + { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata },
437 + { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata },
438 + { /* Sentinel */ }
439 +};
440 +MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
441 +
442 +static int qcom_dwc3_phy_probe(struct platform_device *pdev)
443 +{
444 + struct qcom_dwc3_usb_phy *phy_dwc3;
445 + struct phy_provider *phy_provider;
446 + struct phy *generic_phy;
447 + struct resource *res;
448 + const struct of_device_id *match;
449 + const struct qcom_dwc3_phy_drvdata *data;
450 +
451 + phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
452 + if (!phy_dwc3)
453 + return -ENOMEM;
454 +
455 + match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node);
456 + data = match->data;
457 +
458 + phy_dwc3->dev = &pdev->dev;
459 +
460 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
461 + phy_dwc3->base = devm_ioremap_resource(phy_dwc3->dev, res);
462 + if (IS_ERR(phy_dwc3->base))
463 + return PTR_ERR(phy_dwc3->base);
464 +
465 + phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
466 + if (IS_ERR(phy_dwc3->ref_clk)) {
467 + dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
468 + return PTR_ERR(phy_dwc3->ref_clk);
469 + }
470 +
471 + clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
472 +
473 + phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
474 + if (IS_ERR(phy_dwc3->xo_clk)) {
475 + dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
476 + phy_dwc3->xo_clk = NULL;
477 + }
478 +
479 + generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node,
480 + &data->ops);
481 +
482 + if (IS_ERR(generic_phy))
483 + return PTR_ERR(generic_phy);
484 +
485 + phy_set_drvdata(generic_phy, phy_dwc3);
486 + platform_set_drvdata(pdev, phy_dwc3);
487 +
488 + phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
489 + of_phy_simple_xlate);
490 +
491 + if (IS_ERR(phy_provider))
492 + return PTR_ERR(phy_provider);
493 +
494 + return 0;
495 +}
496 +
497 +static struct platform_driver qcom_dwc3_phy_driver = {
498 + .probe = qcom_dwc3_phy_probe,
499 + .driver = {
500 + .name = "qcom-dwc3-usb-phy",
501 + .owner = THIS_MODULE,
502 + .of_match_table = qcom_dwc3_phy_table,
503 + },
504 +};
505 +
506 +module_platform_driver(qcom_dwc3_phy_driver);
507 +
508 +MODULE_ALIAS("platform:phy-qcom-dwc3");
509 +MODULE_LICENSE("GPL v2");
510 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
511 +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
512 +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");