ipq806x: fix pcie reset gpios
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.4 / 112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Tue, 21 Apr 2015 19:01:42 -0700
4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
5
6 qcom-pcie driver now supports version 0 of the controller. This change
7 adds the corresponding entries to the IPQ806x dtsi file and
8 corresponding platform (AP148).
9
10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
11 ---
12 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
13 arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
14 2 files changed, 154 insertions(+)
15
16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 @@ -116,5 +116,15 @@
19 usb30@1 {
20 status = "ok";
21 };
22 +
23 + pcie0: pci@1b500000 {
24 + status = "ok";
25 + phy-tx0-term-offset = <7>;
26 + };
27 +
28 + pcie1: pci@1b700000 {
29 + status = "ok";
30 + phy-tx0-term-offset = <7>;
31 + };
32 };
33 };
34 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
35 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
36 @@ -128,5 +128,17 @@
37 usb30@1 {
38 status = "ok";
39 };
40 +
41 + pcie0: pci@1b500000 {
42 + status = "ok";
43 + };
44 +
45 + pcie1: pci@1b700000 {
46 + status = "ok";
47 + };
48 +
49 + pcie2: pci@1b900000 {
50 + status = "ok";
51 + };
52 };
53 };
54 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
55 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
56 @@ -4,6 +4,9 @@
57 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
58 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
59 #include <dt-bindings/soc/qcom,gsbi.h>
60 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
61 +#include <dt-bindings/interrupt-controller/arm-gic.h>
62 +#include <dt-bindings/gpio/gpio.h>
63
64 / {
65 model = "Qualcomm IPQ8064";
66 @@ -99,6 +102,33 @@
67 interrupt-controller;
68 #interrupt-cells = <2>;
69 interrupts = <0 16 0x4>;
70 +
71 + pcie0_pins: pcie0_pinmux {
72 + mux {
73 + pins = "gpio3";
74 + function = "pcie1_rst";
75 + drive-strength = <12>;
76 + bias-disable;
77 + };
78 + };
79 +
80 + pcie1_pins: pcie1_pinmux {
81 + mux {
82 + pins = "gpio48";
83 + function = "pcie2_rst";
84 + drive-strength = <12>;
85 + bias-disable;
86 + };
87 + };
88 +
89 + pcie2_pins: pcie2_pinmux {
90 + mux {
91 + pins = "gpio63";
92 + function = "pcie3_rst";
93 + drive-strength = <12>;
94 + bias-disable;
95 + };
96 + };
97 };
98
99 intc: interrupt-controller@2000000 {
100 @@ -417,6 +447,144 @@
101 dr_mode = "host";
102 };
103 };
104 +
105 + pcie0: pci@1b500000 {
106 + compatible = "qcom,pcie-v0";
107 + reg = <0x1b500000 0x1000
108 + 0x1b502000 0x80
109 + 0x1b600000 0x100
110 + 0x0ff00000 0x100000>;
111 + reg-names = "dbi", "elbi", "parf", "config";
112 + device_type = "pci";
113 + linux,pci-domain = <0>;
114 + bus-range = <0x00 0xff>;
115 + num-lanes = <1>;
116 + #address-cells = <3>;
117 + #size-cells = <2>;
118 +
119 + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
120 + 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
121 +
122 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
123 + interrupt-names = "msi";
124 + #interrupt-cells = <1>;
125 + interrupt-map-mask = <0 0 0 0x7>;
126 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
127 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
128 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
129 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
130 +
131 + clocks = <&gcc PCIE_A_CLK>,
132 + <&gcc PCIE_H_CLK>,
133 + <&gcc PCIE_PHY_CLK>;
134 + clock-names = "core", "iface", "phy";
135 +
136 + resets = <&gcc PCIE_ACLK_RESET>,
137 + <&gcc PCIE_HCLK_RESET>,
138 + <&gcc PCIE_POR_RESET>,
139 + <&gcc PCIE_PCI_RESET>,
140 + <&gcc PCIE_PHY_RESET>;
141 + reset-names = "axi", "ahb", "por", "pci", "phy";
142 +
143 + pinctrl-0 = <&pcie0_pins>;
144 + pinctrl-names = "default";
145 +
146 + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
147 +
148 + status = "disabled";
149 + };
150 +
151 + pcie1: pci@1b700000 {
152 + compatible = "qcom,pcie-v0";
153 + reg = <0x1b700000 0x1000
154 + 0x1b702000 0x80
155 + 0x1b800000 0x100
156 + 0x31f00000 0x100000>;
157 + reg-names = "dbi", "elbi", "parf", "config";
158 + device_type = "pci";
159 + linux,pci-domain = <1>;
160 + bus-range = <0x00 0xff>;
161 + num-lanes = <1>;
162 + #address-cells = <3>;
163 + #size-cells = <2>;
164 +
165 + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
166 + 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
167 +
168 + interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
169 + interrupt-names = "msi";
170 + #interrupt-cells = <1>;
171 + interrupt-map-mask = <0 0 0 0x7>;
172 + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
173 + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
174 + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
175 + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
176 +
177 + clocks = <&gcc PCIE_1_A_CLK>,
178 + <&gcc PCIE_1_H_CLK>,
179 + <&gcc PCIE_1_PHY_CLK>;
180 + clock-names = "core", "iface", "phy";
181 +
182 + resets = <&gcc PCIE_1_ACLK_RESET>,
183 + <&gcc PCIE_1_HCLK_RESET>,
184 + <&gcc PCIE_1_POR_RESET>,
185 + <&gcc PCIE_1_PCI_RESET>,
186 + <&gcc PCIE_1_PHY_RESET>;
187 + reset-names = "axi", "ahb", "por", "pci", "phy";
188 +
189 + pinctrl-0 = <&pcie1_pins>;
190 + pinctrl-names = "default";
191 +
192 + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
193 +
194 + status = "disabled";
195 + };
196 +
197 + pcie2: pci@1b900000 {
198 + compatible = "qcom,pcie-v0";
199 + reg = <0x1b900000 0x1000
200 + 0x1b902000 0x80
201 + 0x1ba00000 0x100
202 + 0x35f00000 0x100000>;
203 + reg-names = "dbi", "elbi", "parf", "config";
204 + device_type = "pci";
205 + linux,pci-domain = <2>;
206 + bus-range = <0x00 0xff>;
207 + num-lanes = <1>;
208 + #address-cells = <3>;
209 + #size-cells = <2>;
210 +
211 + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
212 + 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
213 +
214 + interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
215 + interrupt-names = "msi";
216 + #interrupt-cells = <1>;
217 + interrupt-map-mask = <0 0 0 0x7>;
218 + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
219 + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
220 + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
221 + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
222 +
223 + clocks = <&gcc PCIE_2_A_CLK>,
224 + <&gcc PCIE_2_H_CLK>,
225 + <&gcc PCIE_2_PHY_CLK>;
226 + clock-names = "core", "iface", "phy";
227 +
228 + resets = <&gcc PCIE_2_ACLK_RESET>,
229 + <&gcc PCIE_2_HCLK_RESET>,
230 + <&gcc PCIE_2_POR_RESET>,
231 + <&gcc PCIE_2_PCI_RESET>,
232 + <&gcc PCIE_2_PHY_RESET>;
233 + reset-names = "axi", "ahb", "por", "pci", "phy";
234 +
235 + pinctrl-0 = <&pcie2_pins>;
236 + pinctrl-names = "default";
237 +
238 + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
239 +
240 + status = "disabled";
241 + };
242 };
243
244 sfpb_mutex: sfpb-mutex {