target/linux/ipq806x/patches-4.4/134-clk-mux-Split-out-register-accessors-for-reuse.patch

   1 From 4c28a15ea536281c8d619e5c6716ade914c79a6e Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:21 -0700
   4 Subject: [PATCH 1/2] clk: mux: Split out register accessors for reuse
   5
   6 We want to reuse the logic in clk-mux.c for other clock drivers
   7 that don't use readl as register accessors. Fortunately, there
   8 really isn't much to the mux code besides the table indirection
   9 and quirk flags if you assume any bit shifting and masking has
  10 been done already. Pull that logic out into reusable functions
  11 that operate on an optional table and some flags so that other
  12 drivers can use the same logic.
  13
  14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  15 Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
  16 ---
  17  drivers/clk/clk-mux.c        | 74 +++++++++++++++++++++++++++-----------------
  18  include/linux/clk-provider.h |  9 ++++--
  19  2 files changed, 53 insertions(+), 30 deletions(-)
  20
  21 --- a/drivers/clk/clk-mux.c
  22 +++ b/drivers/clk/clk-mux.c
  23 @@ -28,35 +28,24 @@
  24
  25  #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
  26
  27 -static u8 clk_mux_get_parent(struct clk_hw *hw)
  28 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
  29 +                               unsigned int *table, unsigned long flags)
  30  {
  31 -       struct clk_mux *mux = to_clk_mux(hw);
  32         int num_parents = clk_hw_get_num_parents(hw);
  33 -       u32 val;
  34
  35 -       /*
  36 -        * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  37 -        * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  38 -        * to 0x7 (index starts at one)
  39 -        * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  40 -        * val = 0x4 really means "bit 2, index starts at bit 0"
  41 -        */
  42 -       val = clk_readl(mux->reg) >> mux->shift;
  43 -       val &= mux->mask;
  44 -
  45 -       if (mux->table) {
  46 +       if (table) {
  47                 int i;
  48
  49                 for (i = 0; i < num_parents; i++)
  50 -                       if (mux->table[i] == val)
  51 +                       if (table[i] == val)
  52                                 return i;
  53                 return -EINVAL;
  54         }
  55
  56 -       if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  57 +       if (val && (flags & CLK_MUX_INDEX_BIT))
  58                 val = ffs(val) - 1;
  59
  60 -       if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  61 +       if (val && (flags & CLK_MUX_INDEX_ONE))
  62                 val--;
  63
  64         if (val >= num_parents)
  65 @@ -64,24 +53,53 @@ static u8 clk_mux_get_parent(struct clk_
  66
  67         return val;
  68  }
  69 +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
  70
  71 -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
  72 +static u8 _clk_mux_get_parent(struct clk_hw *hw)
  73  {
  74         struct clk_mux *mux = to_clk_mux(hw);
  75         u32 val;
  76 -       unsigned long flags = 0;
  77
  78 -       if (mux->table)
  79 -               index = mux->table[index];
  80 +       /*
  81 +       * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  82 +       * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  83 +       * to 0x7 (index starts at one)
  84 +       * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  85 +       * val = 0x4 really means "bit 2, index starts at bit 0"
  86 +       */
  87 +       val = clk_readl(mux->reg) >> mux->shift;
  88 +       val &= mux->mask;
  89
  90 -       else {
  91 -               if (mux->flags & CLK_MUX_INDEX_BIT)
  92 -                       index = 1 << index;
  93 +       return clk_mux_get_parent(hw, val, mux->table, mux->flags);
  94 +}
  95 +
  96 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
  97 +                           unsigned long flags)
  98 +{
  99 +       unsigned int val = index;
 100
 101 -               if (mux->flags & CLK_MUX_INDEX_ONE)
 102 -                       index++;
 103 +       if (table) {
 104 +               val = table[val];
 105 +       } else {
 106 +               if (flags & CLK_MUX_INDEX_BIT)
 107 +                       val = 1 << index;
 108 +
 109 +       if (flags & CLK_MUX_INDEX_ONE)
 110 +               val++;
 111         }
 112
 113 +       return val;
 114 +}
 115 +EXPORT_SYMBOL_GPL(clk_mux_reindex);
 116 +
 117 +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 118 +{
 119 +       struct clk_mux *mux = to_clk_mux(hw);
 120 +       u32 val;
 121 +       unsigned long flags = 0;
 122 +
 123 +       index = clk_mux_reindex(index, mux->table, mux->flags);
 124 +
 125         if (mux->lock)
 126                 spin_lock_irqsave(mux->lock, flags);
 127         else
 128 @@ -105,7 +123,7 @@ static int clk_mux_set_parent(struct clk
 129  }
 130
 131  const struct clk_ops clk_mux_ops = {
 132 -       .get_parent = clk_mux_get_parent,
 133 +       .get_parent = _clk_mux_get_parent,
 134         .set_parent = clk_mux_set_parent,
 135         .determine_rate = __clk_mux_determine_rate,
 136  };
 137 @@ -120,7 +138,7 @@ struct clk *clk_register_mux_table(struc
 138                 const char * const *parent_names, u8 num_parents,
 139                 unsigned long flags,
 140                 void __iomem *reg, u8 shift, u32 mask,
 141 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock)
 142 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
 143  {
 144         struct clk_mux *mux;
 145         struct clk *clk;
 146 --- a/include/linux/clk-provider.h
 147 +++ b/include/linux/clk-provider.h
 148 @@ -433,7 +433,7 @@ void clk_unregister_divider(struct clk *
 149  struct clk_mux {
 150         struct clk_hw   hw;
 151         void __iomem    *reg;
 152 -       u32             *table;
 153 +       unsigned int    *table;
 154         u32             mask;
 155         u8              shift;
 156         u8              flags;
 157 @@ -449,6 +449,11 @@ struct clk_mux {
 158  extern const struct clk_ops clk_mux_ops;
 159  extern const struct clk_ops clk_mux_ro_ops;
 160
 161 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
 162 +                               unsigned int *table, unsigned long flags);
 163 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
 164 +                           unsigned long flags);
 165 +
 166  struct clk *clk_register_mux(struct device *dev, const char *name,
 167                 const char * const *parent_names, u8 num_parents,
 168                 unsigned long flags,
 169 @@ -459,7 +464,7 @@ struct clk *clk_register_mux_table(struc
 170                 const char * const *parent_names, u8 num_parents,
 171                 unsigned long flags,
 172                 void __iomem *reg, u8 shift, u32 mask,
 173 -               u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 174 +               u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
 175
 176  void clk_unregister_mux(struct clk *clk);
 177