target/linux/ipq806x/patches-4.4/135-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch

   1 From 39d42ce5031d2a4f92fa203b87acfbab340b15a2 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:22 -0700
   4 Subject: [PATCH 2/2] clk: Avoid sending high rates to downstream clocks during
   5  set_rate
   6
   7 If a clock is on and we call clk_set_rate() on it we may get into
   8 a situation where the clock temporarily increases in rate
   9 dramatically while we walk the tree and call .set_rate() ops. For
  10 example, consider a case where a PLL feeds into a divider.
  11 Initially the divider is set to divide by 1 and the PLL is
  12 running fairly slow (100MHz). The downstream consumer of the
  13 divider output can only handle rates =< 400 MHz, but the divider
  14 can only choose between divisors of 1 and 4.
  15
  16  +-----+   +----------------+
  17  | PLL |-->| div 1 or div 4 |---> consumer device
  18  +-----+   +----------------+
  19
  20 To achieve a rate of 400MHz on the output of the divider, we
  21 would have to set the rate of the PLL to 1.6 GHz and then divide
  22 it by 4. The current code would set the PLL to 1.6GHz first while
  23 the divider is still set to 1, thus causing the downstream
  24 consumer of the clock to receive a few clock cycles of 1.6GHz
  25 clock (far beyond it's maximum acceptable rate). We should be
  26 changing the divider first before increasing the PLL rate to
  27 avoid this problem.
  28
  29 Therefore, set the rate of any child clocks that are increasing
  30 in rate from their current rate so that they can increase their
  31 dividers if necessary. We assume that there isn't such a thing as
  32 minimum rate requirements.
  33
  34 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  35 Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
  36 ---
  37  drivers/clk/clk.c | 34 ++++++++++++++++++++++------------
  38  1 file changed, 22 insertions(+), 12 deletions(-)
  39
  40 diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
  41 index f13c3f4..8404c3c 100644
  42 --- a/drivers/clk/clk.c
  43 +++ b/drivers/clk/clk.c
  44 @@ -1427,21 +1427,24 @@ static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
  45   * walk down a subtree and set the new rates notifying the rate
  46   * change on the way
  47   */
  48 -static void clk_change_rate(struct clk_core *core)
  49 +static void
  50 +clk_change_rate(struct clk_core *core, unsigned long best_parent_rate)
  51  {
  52         struct clk_core *child;
  53         struct hlist_node *tmp;
  54         unsigned long old_rate;
  55 -       unsigned long best_parent_rate = 0;
  56         bool skip_set_rate = false;
  57         struct clk_core *old_parent;
  58
  59 -       old_rate = core->rate;
  60 +       hlist_for_each_entry(child, &core->children, child_node) {
  61 +               /* Skip children who will be reparented to another clock */
  62 +               if (child->new_parent && child->new_parent != core)
  63 +                       continue;
  64 +               if (child->new_rate > child->rate)
  65 +                       clk_change_rate(child, core->new_rate);
  66 +       }
  67
  68 -       if (core->new_parent)
  69 -               best_parent_rate = core->new_parent->rate;
  70 -       else if (core->parent)
  71 -               best_parent_rate = core->parent->rate;
  72 +       old_rate = core->rate;
  73
  74         if (core->new_parent && core->new_parent != core->parent) {
  75                 old_parent = __clk_set_parent_before(core, core->new_parent);
  76 @@ -1467,7 +1470,7 @@ static void clk_change_rate(struct clk_core *core)
  77
  78         trace_clk_set_rate_complete(core, core->new_rate);
  79
  80 -       core->rate = clk_recalc(core, best_parent_rate);
  81 +       core->rate = core->new_rate;
  82
  83         if (core->notifier_count && old_rate != core->rate)
  84                 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
  85 @@ -1483,12 +1486,13 @@ static void clk_change_rate(struct clk_core *core)
  86                 /* Skip children who will be reparented to another clock */
  87                 if (child->new_parent && child->new_parent != core)
  88                         continue;
  89 -               clk_change_rate(child);
  90 +               if (child->new_rate != child->rate)
  91 +                       clk_change_rate(child, core->new_rate);
  92         }
  93
  94         /* handle the new child who might not be in core->children yet */
  95 -       if (core->new_child)
  96 -               clk_change_rate(core->new_child);
  97 +       if (core->new_child && core->new_child->new_rate != core->new_child->rate)
  98 +               clk_change_rate(core->new_child, core->new_rate);
  99  }
 100
 101  static int clk_core_set_rate_nolock(struct clk_core *core,
 102 @@ -1497,6 +1501,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
 103         struct clk_core *top, *fail_clk;
 104         unsigned long rate = req_rate;
 105         int ret = 0;
 106 +       unsigned long parent_rate;
 107
 108         if (!core)
 109                 return 0;
 110 @@ -1522,8 +1527,13 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
 111                 return -EBUSY;
 112         }
 113
 114 +       if (top->parent)
 115 +               parent_rate = top->parent->rate;
 116 +       else
 117 +               parent_rate = 0;
 118 +
 119         /* change the rates */
 120 -       clk_change_rate(top);
 121 +       clk_change_rate(top, parent_rate);
 122
 123         core->req_rate = req_rate;
 124
 125 --
 126 2.7.2
 127