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kernel: update kernel 4.4 to version 4.4.47
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.4 / 400-dsa-add-qca.patch
1 From patchwork Fri May 29 01:42:16 2015
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 Subject: [1/7] net: dsa: add new driver for ar8xxx family
6 From: Mathieu Olivari <mathieu@codeaurora.org>
7 X-Patchwork-Id: 477523
8 X-Patchwork-Delegate: davem@davemloft.net
9 Message-Id: <1432863742-18427-2-git-send-email-mathieu@codeaurora.org>
10 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
11 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
12 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
13 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
14 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
15 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
16 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
17 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
18 netdev@vger.kernel.org
19 Date: Thu, 28 May 2015 18:42:16 -0700
20
21 This patch contains initial init & registration code for QCA8337. It
22 will detect a QCA8337 switch, if present and declared in DT/platform.
23
24 Each port will be represented through a standalone net_device interface,
25 as for other DSA switches. CPU can communicate with any of the ports by
26 setting an IP@ on ethN interface. Ports cannot communicate with each
27 other just yet.
28
29 Link status will be reported through polling, and we don't use any
30 encapsulation.
31
32 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
33 ---
34 drivers/net/dsa/Kconfig | 7 ++
35 drivers/net/dsa/Makefile | 1 +
36 drivers/net/dsa/ar8xxx.c | 303 +++++++++++++++++++++++++++++++++++++++++++++++
37 drivers/net/dsa/ar8xxx.h | 82 +++++++++++++
38 net/dsa/dsa.c | 1 +
39 5 files changed, 394 insertions(+)
40 create mode 100644 drivers/net/dsa/ar8xxx.c
41 create mode 100644 drivers/net/dsa/ar8xxx.h
42
43 --- a/drivers/net/dsa/Kconfig
44 +++ b/drivers/net/dsa/Kconfig
45 @@ -65,4 +65,13 @@ config NET_DSA_BCM_SF2
46 This enables support for the Broadcom Starfighter 2 Ethernet
47 switch chips.
48
49 +config NET_DSA_AR8XXX
50 + tristate "Qualcomm Atheros AR8XXX Ethernet switch family support"
51 + depends on NET_DSA
52 + select NET_DSA_TAG_QCA
53 + select REGMAP
54 + ---help---
55 + This enables support for the Qualcomm Atheros AR8XXX Ethernet
56 + switch chips.
57 +
58 endmenu
59 --- a/drivers/net/dsa/Makefile
60 +++ b/drivers/net/dsa/Makefile
61 @@ -14,3 +14,4 @@ ifdef CONFIG_NET_DSA_MV88E6171
62 mv88e6xxx_drv-y += mv88e6171.o
63 endif
64 obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm_sf2.o
65 +obj-$(CONFIG_NET_DSA_AR8XXX) += ar8xxx.o
66 --- /dev/null
67 +++ b/drivers/net/dsa/ar8xxx.c
68 @@ -0,0 +1,529 @@
69 +/*
70 + * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
71 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
72 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
73 + *
74 + * This program is free software; you can redistribute it and/or modify
75 + * it under the terms of the GNU General Public License version 2 and
76 + * only version 2 as published by the Free Software Foundation.
77 + *
78 + * This program is distributed in the hope that it will be useful,
79 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
80 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
81 + * GNU General Public License for more details.
82 + */
83 +
84 +#include <linux/module.h>
85 +#include <linux/phy.h>
86 +#include <linux/netdevice.h>
87 +#include <net/dsa.h>
88 +#include <linux/phy.h>
89 +#include <linux/of_net.h>
90 +#include <linux/of_platform.h>
91 +
92 +#include "ar8xxx.h"
93 +
94 +#define MIB_DESC(_s, _o, _n) \
95 + { \
96 + .size = (_s), \
97 + .offset = (_o), \
98 + .name = (_n), \
99 + }
100 +
101 +static const struct ar8xxx_mib_desc ar8327_mib[] = {
102 + MIB_DESC(1, 0x00, "RxBroad"),
103 + MIB_DESC(1, 0x04, "RxPause"),
104 + MIB_DESC(1, 0x08, "RxMulti"),
105 + MIB_DESC(1, 0x0c, "RxFcsErr"),
106 + MIB_DESC(1, 0x10, "RxAlignErr"),
107 + MIB_DESC(1, 0x14, "RxRunt"),
108 + MIB_DESC(1, 0x18, "RxFragment"),
109 + MIB_DESC(1, 0x1c, "Rx64Byte"),
110 + MIB_DESC(1, 0x20, "Rx128Byte"),
111 + MIB_DESC(1, 0x24, "Rx256Byte"),
112 + MIB_DESC(1, 0x28, "Rx512Byte"),
113 + MIB_DESC(1, 0x2c, "Rx1024Byte"),
114 + MIB_DESC(1, 0x30, "Rx1518Byte"),
115 + MIB_DESC(1, 0x34, "RxMaxByte"),
116 + MIB_DESC(1, 0x38, "RxTooLong"),
117 + MIB_DESC(2, 0x3c, "RxGoodByte"),
118 + MIB_DESC(2, 0x44, "RxBadByte"),
119 + MIB_DESC(1, 0x4c, "RxOverFlow"),
120 + MIB_DESC(1, 0x50, "Filtered"),
121 + MIB_DESC(1, 0x54, "TxBroad"),
122 + MIB_DESC(1, 0x58, "TxPause"),
123 + MIB_DESC(1, 0x5c, "TxMulti"),
124 + MIB_DESC(1, 0x60, "TxUnderRun"),
125 + MIB_DESC(1, 0x64, "Tx64Byte"),
126 + MIB_DESC(1, 0x68, "Tx128Byte"),
127 + MIB_DESC(1, 0x6c, "Tx256Byte"),
128 + MIB_DESC(1, 0x70, "Tx512Byte"),
129 + MIB_DESC(1, 0x74, "Tx1024Byte"),
130 + MIB_DESC(1, 0x78, "Tx1518Byte"),
131 + MIB_DESC(1, 0x7c, "TxMaxByte"),
132 + MIB_DESC(1, 0x80, "TxOverSize"),
133 + MIB_DESC(2, 0x84, "TxByte"),
134 + MIB_DESC(1, 0x8c, "TxCollision"),
135 + MIB_DESC(1, 0x90, "TxAbortCol"),
136 + MIB_DESC(1, 0x94, "TxMultiCol"),
137 + MIB_DESC(1, 0x98, "TxSingleCol"),
138 + MIB_DESC(1, 0x9c, "TxExcDefer"),
139 + MIB_DESC(1, 0xa0, "TxDefer"),
140 + MIB_DESC(1, 0xa4, "TxLateCol"),
141 +};
142 +
143 +u32
144 +ar8xxx_mii_read32(struct mii_bus *bus, int phy_id, int regnum)
145 +{
146 + u16 lo, hi;
147 +
148 + lo = bus->read(bus, phy_id, regnum);
149 + hi = bus->read(bus, phy_id, regnum + 1);
150 +
151 + return (hi << 16) | lo;
152 +}
153 +
154 +void
155 +ar8xxx_mii_write32(struct mii_bus *bus, int phy_id, int regnum, u32 val)
156 +{
157 + u16 lo, hi;
158 +
159 + lo = val & 0xffff;
160 + hi = (u16)(val >> 16);
161 +
162 + bus->write(bus, phy_id, regnum, lo);
163 + bus->write(bus, phy_id, regnum + 1, hi);
164 +}
165 +
166 +u32 ar8xxx_read(struct dsa_switch *ds, int reg)
167 +{
168 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
169 + u16 r1, r2, page;
170 + u32 val;
171 +
172 + split_addr((u32)reg, &r1, &r2, &page);
173 +
174 + mutex_lock(&bus->mdio_lock);
175 +
176 + bus->write(bus, 0x18, 0, page);
177 + wait_for_page_switch();
178 + val = ar8xxx_mii_read32(bus, 0x10 | r2, r1);
179 +
180 + mutex_unlock(&bus->mdio_lock);
181 +
182 + return val;
183 +}
184 +
185 +void ar8xxx_write(struct dsa_switch *ds, int reg, u32 val)
186 +{
187 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
188 + u16 r1, r2, page;
189 +
190 + split_addr((u32)reg, &r1, &r2, &page);
191 +
192 + mutex_lock(&bus->mdio_lock);
193 +
194 + bus->write(bus, 0x18, 0, page);
195 + wait_for_page_switch();
196 + ar8xxx_mii_write32(bus, 0x10 | r2, r1, val);
197 +
198 + mutex_unlock(&bus->mdio_lock);
199 +}
200 +
201 +u32
202 +ar8xxx_rmw(struct dsa_switch *ds, int reg, u32 mask, u32 val)
203 +{
204 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
205 + u16 r1, r2, page;
206 + u32 ret;
207 +
208 + split_addr((u32)reg, &r1, &r2, &page);
209 +
210 + mutex_lock(&bus->mdio_lock);
211 +
212 + bus->write(bus, 0x18, 0, page);
213 + wait_for_page_switch();
214 +
215 + ret = ar8xxx_mii_read32(bus, 0x10 | r2, r1);
216 + ret &= ~mask;
217 + ret |= val;
218 + ar8xxx_mii_write32(bus, 0x10 | r2, r1, ret);
219 +
220 + mutex_unlock(&bus->mdio_lock);
221 +
222 + return ret;
223 +}
224 +
225 +static char *ar8xxx_probe(struct device *host_dev, int sw_addr)
226 +{
227 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
228 + u32 phy_id;
229 +
230 + if (!bus)
231 + return NULL;
232 +
233 + /* sw_addr is irrelevant as the switch occupies the MDIO bus from
234 + * addresses 0 to 4 (PHYs) and 16-23 (for MDIO 32bits protocol). So
235 + * we'll probe address 0 to see if we see the right switch family.
236 + */
237 + phy_id = mdiobus_read(bus, 0, MII_PHYSID1) << 16;
238 + phy_id |= mdiobus_read(bus, 0, MII_PHYSID2);
239 +
240 + switch (phy_id) {
241 + case PHY_ID_QCA8337:
242 + return "QCA8337";
243 + default:
244 + return NULL;
245 + }
246 +}
247 +
248 +static int ar8xxx_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
249 +{
250 + struct dsa_switch *ds = (struct dsa_switch *)ctx;
251 +
252 + *val = ar8xxx_read(ds, reg);
253 +
254 + return 0;
255 +}
256 +
257 +static int ar8xxx_regmap_write(void *ctx, uint32_t reg, uint32_t val)
258 +{
259 + struct dsa_switch *ds = (struct dsa_switch *)ctx;
260 +
261 + ar8xxx_write(ds, reg, val);
262 +
263 + return 0;
264 +}
265 +
266 +static const struct regmap_range ar8xxx_readable_ranges[] = {
267 + regmap_reg_range(0x0000, 0x00e4), /* Global control */
268 + regmap_reg_range(0x0100, 0x0168), /* EEE control */
269 + regmap_reg_range(0x0200, 0x0270), /* Parser control */
270 + regmap_reg_range(0x0400, 0x0454), /* ACL */
271 + regmap_reg_range(0x0600, 0x0718), /* Lookup */
272 + regmap_reg_range(0x0800, 0x0b70), /* QM */
273 + regmap_reg_range(0x0C00, 0x0c80), /* PKT */
274 + regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
275 + regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
276 + regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
277 + regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
278 + regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
279 + regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
280 + regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
281 +
282 +};
283 +
284 +static struct regmap_access_table ar8xxx_readable_table = {
285 + .yes_ranges = ar8xxx_readable_ranges,
286 + .n_yes_ranges = ARRAY_SIZE(ar8xxx_readable_ranges),
287 +};
288 +
289 +struct regmap_config ar8xxx_regmap_config = {
290 + .reg_bits = 16,
291 + .val_bits = 32,
292 + .reg_stride = 4,
293 + .max_register = 0x16ac, /* end MIB - Port6 range */
294 + .reg_read = ar8xxx_regmap_read,
295 + .reg_write = ar8xxx_regmap_write,
296 + .rd_table = &ar8xxx_readable_table,
297 +};
298 +
299 +static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
300 +{
301 + int reg;
302 +
303 + switch (port) {
304 + case 0:
305 + reg = AR8327_REG_PORT0_PAD_CTRL;
306 + break;
307 + case 6:
308 + reg = AR8327_REG_PORT6_PAD_CTRL;
309 + break;
310 + default:
311 + pr_err("Can't set PAD_CTRL on port %d\n", port);
312 + return -EINVAL;
313 + }
314 +
315 + /* DSA only supports 1 CPU port for now, so we'll take the assumption
316 + * that P0 is connected to the CPU master_dev.
317 + */
318 + switch (mode) {
319 + case PHY_INTERFACE_MODE_RGMII:
320 + ar8xxx_write(ds, reg,
321 + AR8327_PORT_PAD_RGMII_EN |
322 + AR8327_PORT_PAD_RGMII_TX_DELAY(3) |
323 + AR8327_PORT_PAD_RGMII_RX_DELAY(3));
324 +
325 + /* According to the datasheet, RGMII delay is enabled through
326 + * PORT5_PAD_CTRL for all ports, rather than individual port
327 + * registers
328 + */
329 + ar8xxx_write(ds, AR8327_REG_PORT5_PAD_CTRL,
330 + AR8327_PORT_PAD_RGMII_RX_DELAY_EN);
331 + break;
332 + case PHY_INTERFACE_MODE_SGMII:
333 + ar8xxx_write(ds, reg, AR8327_PORT_PAD_SGMII_EN);
334 + break;
335 + default:
336 + pr_err("xMII mode %d not supported\n", mode);
337 + return -EINVAL;
338 + }
339 +
340 + return 0;
341 +}
342 +
343 +static int ar8xxx_of_setup(struct dsa_switch *ds)
344 +{
345 + struct device_node *dn = ds->pd->of_node;
346 + const char *s_phymode;
347 + int ret, mode;
348 + u32 phy_id, ctrl;
349 +
350 + /* If port6-phy-mode property exists, configure it accordingly */
351 + if (!of_property_read_string(dn, "qca,port6-phy-mode", &s_phymode)) {
352 + for (mode = 0; mode < PHY_INTERFACE_MODE_MAX; mode++)
353 + if (!strcasecmp(s_phymode, phy_modes(mode)))
354 + break;
355 +
356 + if (mode == PHY_INTERFACE_MODE_MAX)
357 + pr_err("Unknown phy-mode: \"%s\"\n", s_phymode);
358 +
359 + ret = ar8xxx_set_pad_ctrl(ds, 6, mode);
360 + if (ret < 0)
361 + return ret;
362 + }
363 +
364 + /* If a phy ID is specified for PORT6 mac, connect them together */
365 + if (!of_property_read_u32(dn, "qca,port6-phy-id", &phy_id)) {
366 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(6),
367 + AR8327_PORT_LOOKUP_MEMBER, BIT(phy_to_port(phy_id)));
368 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(phy_id)),
369 + AR8327_PORT_LOOKUP_MEMBER, BIT(6));
370 +
371 + /* We want the switch to be pass-through and act like a PHY on
372 + * these ports. So BC/MC/UC & IGMP frames need to be accepted
373 + */
374 + ctrl = BIT(phy_to_port(phy_id)) | BIT(6);
375 + ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL1,
376 + ctrl << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
377 + ctrl << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
378 + ctrl << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
379 + ctrl << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
380 + }
381 +
382 + return 0;
383 +}
384 +
385 +static int ar8xxx_setup(struct dsa_switch *ds)
386 +{
387 + struct ar8xxx_priv *priv = ds_to_priv(ds);
388 + struct net_device *netdev = ds->dst->pd->of_netdev;
389 + int ret, i, phy_mode;
390 +
391 + /* Start by setting up the register mapping */
392 + priv->regmap = devm_regmap_init(ds->master_dev, NULL, ds,
393 + &ar8xxx_regmap_config);
394 +
395 + if (IS_ERR(priv->regmap))
396 + pr_warn("regmap initialization failed");
397 +
398 + /* Initialize CPU port pad mode (xMII type, delays...) */
399 + phy_mode = of_get_phy_mode(netdev->dev.parent->of_node);
400 + if (phy_mode < 0) {
401 + pr_err("Can't find phy-mode for master device\n");
402 + return phy_mode;
403 + }
404 +
405 + ret = ar8xxx_set_pad_ctrl(ds, 0, phy_mode);
406 + if (ret < 0)
407 + return ret;
408 +
409 + /* Enable CPU Port */
410 + ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL0,
411 + AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN);
412 +
413 + /* Enable MIB counters */
414 + ar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);
415 + ar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);
416 +
417 + /* Enable QCA header mode on Port 0 */
418 + ar8xxx_write(ds, AR8327_REG_PORT_HDR_CTRL(0),
419 + AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_TX_S |
420 + AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_RX_S);
421 +
422 + /* Disable forwarding by default on all ports */
423 + for (i = 0; i < AR8327_NUM_PORTS; i++)
424 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),
425 + AR8327_PORT_LOOKUP_MEMBER, 0);
426 +
427 + /* Forward all unknown frames to CPU port for Linux processing */
428 + ar8xxx_write(ds, AR8327_REG_GLOBAL_FW_CTRL1,
429 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
430 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
431 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
432 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
433 +
434 + /* Setup connection between CPU ports & PHYs */
435 + for (i = 0; i < DSA_MAX_PORTS; i++) {
436 + /* CPU port gets connected to all PHYs in the switch */
437 + if (dsa_is_cpu_port(ds, i)) {
438 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(0),
439 + AR8327_PORT_LOOKUP_MEMBER,
440 + ds->phys_port_mask << 1);
441 + }
442 +
443 + /* Invividual PHYs gets connected to CPU port only */
444 + if (ds->phys_port_mask & BIT(i)) {
445 + int phy = phy_to_port(i);
446 +
447 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy),
448 + AR8327_PORT_LOOKUP_MEMBER, BIT(0));
449 +
450 + /* Disable Auto-learning by default so the switch
451 + * doesn't try to forward the frame to another port
452 + */
453 + ar8xxx_reg_clear(ds, AR8327_PORT_LOOKUP_CTRL(phy),
454 + AR8327_PORT_LOOKUP_LEARN);
455 + }
456 + }
457 +
458 + ret = ar8xxx_of_setup(ds);
459 + if (ret < 0)
460 + return ret;
461 +
462 + return 0;
463 +}
464 +
465 +static int ar8xxx_set_addr(struct dsa_switch *ds, u8 *addr)
466 +{
467 + return 0;
468 +}
469 +
470 +static int ar8xxx_phy_read(struct dsa_switch *ds, int phy, int regnum)
471 +{
472 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
473 +
474 + return mdiobus_read(bus, phy, regnum);
475 +}
476 +
477 +static int
478 +ar8xxx_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)
479 +{
480 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
481 +
482 + return mdiobus_write(bus, phy, regnum, val);
483 +}
484 +
485 +static void ar8xxx_get_strings(struct dsa_switch *ds, int phy, uint8_t *data)
486 +{
487 + int i;
488 +
489 + for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
490 + strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
491 + ETH_GSTRING_LEN);
492 + }
493 +}
494 +
495 +static void ar8xxx_get_ethtool_stats(struct dsa_switch *ds, int phy,
496 + uint64_t *data)
497 +{
498 + const struct ar8xxx_mib_desc *mib;
499 + uint32_t reg, i, port;
500 + u64 hi;
501 +
502 + port = phy_to_port(phy);
503 +
504 + for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
505 + mib = &ar8327_mib[i];
506 + reg = AR8327_PORT_MIB_COUNTER(port) + mib->offset;
507 +
508 + data[i] = ar8xxx_read(ds, reg);
509 + if (mib->size == 2) {
510 + hi = ar8xxx_read(ds, reg + 4);
511 + data[i] |= hi << 32;
512 + }
513 + }
514 +}
515 +
516 +static int ar8xxx_get_sset_count(struct dsa_switch *ds)
517 +{
518 + return ARRAY_SIZE(ar8327_mib);
519 +}
520 +
521 +static void ar8xxx_poll_link(struct dsa_switch *ds)
522 +{
523 + int i = 0;
524 + struct net_device *dev;
525 +
526 + while ((dev = ds->ports[i++]) != NULL) {
527 + u32 status;
528 + int link;
529 + int speed;
530 + int duplex;
531 +
532 + status = ar8xxx_read(ds, AR8327_REG_PORT_STATUS(i));
533 + link = !!(status & AR8XXX_PORT_STATUS_LINK_UP);
534 + duplex = !!(status & AR8XXX_PORT_STATUS_DUPLEX);
535 +
536 + switch (status & AR8XXX_PORT_STATUS_SPEED) {
537 + case AR8XXX_PORT_SPEED_10M:
538 + speed = 10;
539 + break;
540 + case AR8XXX_PORT_SPEED_100M:
541 + speed = 100;
542 + break;
543 + case AR8XXX_PORT_SPEED_1000M:
544 + speed = 1000;
545 + break;
546 + default:
547 + speed = 0;
548 + }
549 +
550 + if (!link) {
551 + /* This poll happens every ~1s, so we don't want to
552 + * print the status every time. Only when the device
553 + * transitions from Link UP to Link DOWN
554 + */
555 + if (netif_carrier_ok(dev))
556 + netif_carrier_off(dev);
557 + continue;
558 + } else {
559 + /* Same thing here. But we detect a Link UP event */
560 + if (!netif_carrier_ok(dev))
561 + netif_carrier_on(dev);
562 + continue;
563 + }
564 + }
565 +}
566 +
567 +static struct dsa_switch_driver ar8xxx_switch_driver = {
568 + .tag_protocol = DSA_TAG_PROTO_QCA,
569 + .priv_size = sizeof(struct ar8xxx_priv),
570 + .probe = ar8xxx_probe,
571 + .setup = ar8xxx_setup,
572 + .set_addr = ar8xxx_set_addr,
573 + .poll_link = ar8xxx_poll_link,
574 + .phy_read = ar8xxx_phy_read,
575 + .phy_write = ar8xxx_phy_write,
576 + .get_strings = ar8xxx_get_strings,
577 + .get_ethtool_stats = ar8xxx_get_ethtool_stats,
578 + .get_sset_count = ar8xxx_get_sset_count,
579 +};
580 +
581 +static int __init ar8xxx_init(void)
582 +{
583 + register_switch_driver(&ar8xxx_switch_driver);
584 + return 0;
585 +}
586 +module_init(ar8xxx_init);
587 +
588 +static void __exit ar8xxx_cleanup(void)
589 +{
590 + unregister_switch_driver(&ar8xxx_switch_driver);
591 +}
592 +module_exit(ar8xxx_cleanup);
593 +
594 +MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
595 +MODULE_DESCRIPTION("Driver for AR8XXX ethernet switch family");
596 +MODULE_LICENSE("GPL");
597 +MODULE_ALIAS("platform:ar8xxx");
598 --- /dev/null
599 +++ b/drivers/net/dsa/ar8xxx.h
600 @@ -0,0 +1,156 @@
601 +/*
602 + * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
603 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
604 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
605 + *
606 + * This program is free software; you can redistribute it and/or modify
607 + * it under the terms of the GNU General Public License version 2 and
608 + * only version 2 as published by the Free Software Foundation.
609 + *
610 + * This program is distributed in the hope that it will be useful,
611 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
612 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
613 + * GNU General Public License for more details.
614 + */
615 +
616 +#ifndef __AR8XXX_H
617 +#define __AR8XXX_H
618 +
619 +#include <linux/delay.h>
620 +#include <linux/regmap.h>
621 +
622 +struct ar8xxx_priv {
623 + struct regmap *regmap;
624 +};
625 +
626 +struct ar8xxx_mib_desc {
627 + unsigned int size;
628 + unsigned int offset;
629 + const char *name;
630 +};
631 +
632 +#define AR8327_NUM_PORTS 7
633 +
634 +#define PHY_ID_QCA8337 0x004dd036
635 +
636 +#define AR8327_REG_PORT0_PAD_CTRL 0x004
637 +#define AR8327_REG_PORT5_PAD_CTRL 0x008
638 +#define AR8327_REG_PORT6_PAD_CTRL 0x00c
639 +#define AR8327_PORT_PAD_RGMII_EN BIT(26)
640 +#define AR8327_PORT_PAD_RGMII_TX_DELAY(x) ((0x8 + (x & 0x3)) << 22)
641 +#define AR8327_PORT_PAD_RGMII_RX_DELAY(x) ((0x10 + (x & 0x3)) << 20)
642 +#define AR8327_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
643 +#define AR8327_PORT_PAD_SGMII_EN BIT(7)
644 +
645 +#define AR8327_REG_MODULE_EN 0x030
646 +#define AR8327_MODULE_EN_MIB BIT(0)
647 +#define AR8327_MODULE_EN_ACL BIT(1)
648 +#define AR8327_MODULE_EN_L3 BIT(2)
649 +
650 +#define AR8327_REG_MIB 0x034
651 +#define AR8327_MIB_CPU_KEEP BIT(20)
652 +
653 +#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
654 +#define AR8XXX_PORT_STATUS_SPEED GENMASK(2, 0)
655 +#define AR8XXX_PORT_STATUS_SPEED_S 0
656 +#define AR8XXX_PORT_STATUS_TXMAC BIT(2)
657 +#define AR8XXX_PORT_STATUS_RXMAC BIT(3)
658 +#define AR8XXX_PORT_STATUS_TXFLOW BIT(4)
659 +#define AR8XXX_PORT_STATUS_RXFLOW BIT(5)
660 +#define AR8XXX_PORT_STATUS_DUPLEX BIT(6)
661 +#define AR8XXX_PORT_STATUS_LINK_UP BIT(8)
662 +#define AR8XXX_PORT_STATUS_LINK_AUTO BIT(9)
663 +#define AR8XXX_PORT_STATUS_LINK_PAUSE BIT(10)
664 +
665 +#define AR8327_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
666 +#define AR8327_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
667 +#define AR8327_PORT_HDR_CTRL_RX_S 2
668 +#define AR8327_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
669 +#define AR8327_PORT_HDR_CTRL_TX_S 0
670 +#define AR8327_PORT_HDR_CTRL_ALL 2
671 +#define AR8327_PORT_HDR_CTRL_MGMT 1
672 +#define AR8327_PORT_HDR_CTRL_NONE 0
673 +
674 +#define AR8327_REG_GLOBAL_FW_CTRL0 0x620
675 +#define AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
676 +
677 +#define AR8327_REG_GLOBAL_FW_CTRL1 0x624
678 +#define AR8327_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
679 +#define AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S 24
680 +#define AR8327_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
681 +#define AR8327_GLOBAL_FW_CTRL1_BC_DP_S 16
682 +#define AR8327_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
683 +#define AR8327_GLOBAL_FW_CTRL1_MC_DP_S 8
684 +#define AR8327_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
685 +#define AR8327_GLOBAL_FW_CTRL1_UC_DP_S 0
686 +
687 +#define AR8327_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
688 +#define AR8327_PORT_LOOKUP_MEMBER GENMASK(6, 0)
689 +#define AR8327_PORT_LOOKUP_IN_MODE GENMASK(9, 8)
690 +#define AR8327_PORT_LOOKUP_IN_MODE_S 8
691 +#define AR8327_PORT_LOOKUP_STATE GENMASK(18, 16)
692 +#define AR8327_PORT_LOOKUP_STATE_S 16
693 +#define AR8327_PORT_LOOKUP_LEARN BIT(20)
694 +#define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
695 +
696 +#define AR8327_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
697 +
698 +/* port speed */
699 +enum {
700 + AR8XXX_PORT_SPEED_10M = 0,
701 + AR8XXX_PORT_SPEED_100M = 1,
702 + AR8XXX_PORT_SPEED_1000M = 2,
703 + AR8XXX_PORT_SPEED_ERR = 3,
704 +};
705 +
706 +static inline int port_to_phy(int port)
707 +{
708 + if (port >= 1 && port <= 6)
709 + return port - 1;
710 +
711 + return -1;
712 +}
713 +
714 +static inline int phy_to_port(int phy)
715 +{
716 + if (phy < 5)
717 + return phy + 1;
718 +
719 + return -1;
720 +}
721 +
722 +u32
723 +ar8xxx_rmw(struct dsa_switch *ds, int reg, u32 mask, u32 val);
724 +
725 +static inline void
726 +split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
727 +{
728 + regaddr >>= 1;
729 + *r1 = regaddr & 0x1e;
730 +
731 + regaddr >>= 5;
732 + *r2 = regaddr & 0x7;
733 +
734 + regaddr >>= 3;
735 + *page = regaddr & 0x1ff;
736 +}
737 +
738 +static inline void
739 +wait_for_page_switch(void)
740 +{
741 + udelay(5);
742 +}
743 +
744 +static inline void
745 +ar8xxx_reg_set(struct dsa_switch *ds, int reg, u32 val)
746 +{
747 + ar8xxx_rmw(ds, reg, 0, val);
748 +}
749 +
750 +static inline void
751 +ar8xxx_reg_clear(struct dsa_switch *ds, int reg, u32 val)
752 +{
753 + ar8xxx_rmw(ds, reg, val, 0);
754 +}
755 +
756 +#endif /* __AR8XXX_H */
757 --- a/net/dsa/dsa.c
758 +++ b/net/dsa/dsa.c
759 @@ -285,6 +285,11 @@ static int dsa_switch_setup_one(struct d
760 dst->rcv = brcm_netdev_ops.rcv;
761 break;
762 #endif
763 +#ifdef CONFIG_NET_DSA_TAG_QCA
764 + case DSA_TAG_PROTO_QCA:
765 + dst->rcv = qca_netdev_ops.rcv;
766 + break;
767 +#endif
768 case DSA_TAG_PROTO_NONE:
769 break;
770 default:
771 @@ -1041,6 +1046,7 @@ static SIMPLE_DEV_PM_OPS(dsa_pm_ops, dsa
772
773 static const struct of_device_id dsa_of_match_table[] = {
774 { .compatible = "brcm,bcm7445-switch-v4.0" },
775 + { .compatible = "qca,ar8xxx", },
776 { .compatible = "marvell,dsa", },
777 {}
778 };
779 --- a/include/net/dsa.h
780 +++ b/include/net/dsa.h
781 @@ -26,6 +26,7 @@ enum dsa_tag_protocol {
782 DSA_TAG_PROTO_TRAILER,
783 DSA_TAG_PROTO_EDSA,
784 DSA_TAG_PROTO_BRCM,
785 + DSA_TAG_PROTO_QCA,
786 };
787
788 #define DSA_MAX_SWITCHES 4
789 --- a/net/dsa/Kconfig
790 +++ b/net/dsa/Kconfig
791 @@ -26,6 +26,9 @@ config NET_DSA_HWMON
792 via the hwmon sysfs interface and exposes the onboard sensors.
793
794 # tagging formats
795 +config NET_DSA_TAG_QCA
796 + bool
797 +
798 config NET_DSA_TAG_BRCM
799 bool
800
801 --- a/net/dsa/Makefile
802 +++ b/net/dsa/Makefile
803 @@ -3,6 +3,7 @@ obj-$(CONFIG_NET_DSA) += dsa_core.o
804 dsa_core-y += dsa.o slave.o
805
806 # tagging formats
807 +dsa_core-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
808 dsa_core-$(CONFIG_NET_DSA_TAG_BRCM) += tag_brcm.o
809 dsa_core-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
810 dsa_core-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
811 --- a/net/dsa/dsa_priv.h
812 +++ b/net/dsa/dsa_priv.h
813 @@ -78,5 +78,7 @@ extern const struct dsa_device_ops trail
814 /* tag_brcm.c */
815 extern const struct dsa_device_ops brcm_netdev_ops;
816
817 +/* tag_qca.c */
818 +extern const struct dsa_device_ops qca_netdev_ops;
819
820 #endif
821 --- a/net/dsa/slave.c
822 +++ b/net/dsa/slave.c
823 @@ -1182,6 +1182,11 @@ int dsa_slave_create(struct dsa_switch *
824 p->xmit = brcm_netdev_ops.xmit;
825 break;
826 #endif
827 +#ifdef CONFIG_NET_DSA_TAG_QCA
828 + case DSA_TAG_PROTO_QCA:
829 + p->xmit = qca_netdev_ops.xmit;
830 + break;
831 +#endif
832 default:
833 p->xmit = dsa_slave_notag_xmit;
834 break;
835 --- /dev/null
836 +++ b/net/dsa/tag_qca.c
837 @@ -0,0 +1,158 @@
838 +/*
839 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
840 + *
841 + * This program is free software; you can redistribute it and/or modify
842 + * it under the terms of the GNU General Public License version 2 and
843 + * only version 2 as published by the Free Software Foundation.
844 + *
845 + * This program is distributed in the hope that it will be useful,
846 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
847 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
848 + * GNU General Public License for more details.
849 + */
850 +
851 +#include <linux/etherdevice.h>
852 +#include "dsa_priv.h"
853 +
854 +#define QCA_HDR_LEN 2
855 +#define QCA_HDR_VERSION 0x2
856 +
857 +#define QCA_HDR_RECV_VERSION_MASK GENMASK(15, 14)
858 +#define QCA_HDR_RECV_VERSION_S 14
859 +#define QCA_HDR_RECV_PRIORITY_MASK GENMASK(13, 11)
860 +#define QCA_HDR_RECV_PRIORITY_S 11
861 +#define QCA_HDR_RECV_TYPE_MASK GENMASK(10, 6)
862 +#define QCA_HDR_RECV_TYPE_S 6
863 +#define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3)
864 +#define QCA_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)
865 +
866 +#define QCA_HDR_XMIT_VERSION_MASK GENMASK(15, 14)
867 +#define QCA_HDR_XMIT_VERSION_S 14
868 +#define QCA_HDR_XMIT_PRIORITY_MASK GENMASK(13, 11)
869 +#define QCA_HDR_XMIT_PRIORITY_S 11
870 +#define QCA_HDR_XMIT_CONTROL_MASK GENMASK(10, 8)
871 +#define QCA_HDR_XMIT_CONTROL_S 8
872 +#define QCA_HDR_XMIT_FROM_CPU BIT(7)
873 +#define QCA_HDR_XMIT_DP_BIT_MASK GENMASK(6, 0)
874 +
875 +static inline int reg_to_port(int reg)
876 +{
877 + if (reg < 5)
878 + return reg + 1;
879 +
880 + return -1;
881 +}
882 +
883 +static inline int port_to_reg(int port)
884 +{
885 + if (port >= 1 && port <= 6)
886 + return port - 1;
887 +
888 + return -1;
889 +}
890 +
891 +static netdev_tx_t qca_tag_xmit(struct sk_buff *skb, struct net_device *dev)
892 +{
893 + struct dsa_slave_priv *p = netdev_priv(dev);
894 + u16 *phdr, hdr;
895 +
896 + dev->stats.tx_packets++;
897 + dev->stats.tx_bytes += skb->len;
898 +
899 + if (skb_cow_head(skb, 0) < 0)
900 + goto out_free;
901 +
902 + skb_push(skb, QCA_HDR_LEN);
903 +
904 + memmove(skb->data, skb->data + QCA_HDR_LEN, 2 * ETH_ALEN);
905 + phdr = (u16 *)(skb->data + 2 * ETH_ALEN);
906 +
907 + /* Set the version field, and set destination port information */
908 + hdr = QCA_HDR_VERSION << QCA_HDR_XMIT_VERSION_S |
909 + QCA_HDR_XMIT_FROM_CPU |
910 + 1 << reg_to_port(p->port);
911 +
912 + *phdr = htons(hdr);
913 +
914 + skb->dev = p->parent->dst->master_netdev;
915 + dev_queue_xmit(skb);
916 +
917 + return NETDEV_TX_OK;
918 +
919 +out_free:
920 + kfree_skb(skb);
921 + return NETDEV_TX_OK;
922 +}
923 +
924 +static int qca_tag_rcv(struct sk_buff *skb, struct net_device *dev,
925 + struct packet_type *pt, struct net_device *orig_dev)
926 +{
927 + struct dsa_switch_tree *dst = dev->dsa_ptr;
928 + struct dsa_switch *ds;
929 + u8 ver;
930 + int port, phy;
931 + __be16 *phdr, hdr;
932 +
933 + if (unlikely(!dst))
934 + goto out_drop;
935 +
936 + skb = skb_unshare(skb, GFP_ATOMIC);
937 + if (!skb)
938 + goto out;
939 +
940 + if (unlikely(!pskb_may_pull(skb, QCA_HDR_LEN)))
941 + goto out_drop;
942 +
943 + /* Ethernet is added by the switch between src addr and Ethertype
944 + * At this point, skb->data points to ethertype so header should be
945 + * right before
946 + */
947 + phdr = (__be16 *)(skb->data - 2);
948 + hdr = ntohs(*phdr);
949 +
950 + /* Make sure the version is correct */
951 + ver = (hdr & QCA_HDR_RECV_VERSION_MASK) >> QCA_HDR_RECV_VERSION_S;
952 + if (unlikely(ver != QCA_HDR_VERSION))
953 + goto out_drop;
954 +
955 + /* Remove QCA tag and recalculate checksum */
956 + skb_pull_rcsum(skb, QCA_HDR_LEN);
957 + memmove(skb->data - ETH_HLEN, skb->data - ETH_HLEN - QCA_HDR_LEN,
958 + ETH_HLEN - QCA_HDR_LEN);
959 +
960 + /* This protocol doesn't support cascading multiple switches so it's
961 + * safe to assume the switch is first in the tree
962 + */
963 + ds = dst->ds[0];
964 + if (!ds)
965 + goto out_drop;
966 +
967 + /* Get source port information */
968 + port = (hdr & QCA_HDR_RECV_SOURCE_PORT_MASK);
969 + phy = port_to_reg(port);
970 + if (unlikely(phy < 0) || !ds->ports[phy])
971 + goto out_drop;
972 +
973 + /* Update skb & forward the frame accordingly */
974 + skb_push(skb, ETH_HLEN);
975 + skb->pkt_type = PACKET_HOST;
976 + skb->dev = ds->ports[phy];
977 + skb->protocol = eth_type_trans(skb, skb->dev);
978 +
979 + skb->dev->stats.rx_packets++;
980 + skb->dev->stats.rx_bytes += skb->len;
981 +
982 + netif_receive_skb(skb);
983 +
984 + return 0;
985 +
986 +out_drop:
987 + kfree_skb(skb);
988 +out:
989 + return 0;
990 +}
991 +
992 +const struct dsa_device_ops qca_netdev_ops = {
993 + .xmit = qca_tag_xmit,
994 + .rcv = qca_tag_rcv,
995 +};
996 --- /dev/null
997 +++ b/Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt
998 @@ -0,0 +1,70 @@
999 +* Qualcomm Atheros AR8xxx switch family
1000 +
1001 +Required properties:
1002 +
1003 +- compatible: should be "qca,ar8xxx"
1004 +- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
1005 +- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt
1006 +- #size-cells: must be 0
1007 +- #address-cells: must be 2, see dsa/dsa.txt
1008 +
1009 +Subnodes:
1010 +
1011 +The integrated switch subnode should be specified according to the binding
1012 +described in dsa/dsa.txt.
1013 +
1014 +Optional properties:
1015 +
1016 +- qca,port6-phy-mode: if specified, the driver will configure Port 6 in the
1017 + given phy-mode. See Documentation/devicetree/bindings/net/ethernet.txt for
1018 + the list of valid phy-mode.
1019 +
1020 +- qca,port6-phy-id: if specified, the driver will connect Port 6 to the PHY
1021 + given as a parameter. In this case, Port6 and the corresponding PHY will be
1022 + isolated from the rest of the switch. From a system perspective, they will
1023 + act as a regular PHY.
1024 +
1025 +Example:
1026 +
1027 + dsa@0 {
1028 + compatible = "qca,ar8xxx";
1029 + #address-cells = <2>;
1030 + #size-cells = <0>;
1031 +
1032 + dsa,ethernet = <&ethernet0>;
1033 + dsa,mii-bus = <&mii_bus0>;
1034 +
1035 + switch@0 {
1036 + #address-cells = <1>;
1037 + #size-cells = <0>;
1038 + reg = <0 0>; /* MDIO address 0, switch 0 in tree */
1039 +
1040 + qca,port6-phy-mode = "sgmii";
1041 + qca,port6-phy-id = <4>;
1042 +
1043 + port@0 {
1044 + reg = <11>;
1045 + label = "cpu";
1046 + };
1047 +
1048 + port@1 {
1049 + reg = <0>;
1050 + label = "lan1";
1051 + };
1052 +
1053 + port@2 {
1054 + reg = <1>;
1055 + label = "lan2";
1056 + };
1057 +
1058 + port@3 {
1059 + reg = <2>;
1060 + label = "lan3";
1061 + };
1062 +
1063 + port@4 {
1064 + reg = <3>;
1065 + label = "lan4";
1066 + };
1067 + };
1068 + };
OpenWrt Source Repository