projects / openwrt / openwrt.git / blob
? search:


9457e1d8ad0e60b7309d0190acc0c8a411921adf
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.4 / 400-dsa-add-qca.patch
1 From patchwork Fri May 29 01:42:16 2015
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 Subject: [1/7] net: dsa: add new driver for ar8xxx family
6 From: Mathieu Olivari <mathieu@codeaurora.org>
7 X-Patchwork-Id: 477523
8 X-Patchwork-Delegate: davem@davemloft.net
9 Message-Id: <1432863742-18427-2-git-send-email-mathieu@codeaurora.org>
10 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
11 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
12 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
13 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
14 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
15 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
16 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
17 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
18 netdev@vger.kernel.org
19 Date: Thu, 28 May 2015 18:42:16 -0700
20
21 This patch contains initial init & registration code for QCA8337. It
22 will detect a QCA8337 switch, if present and declared in DT/platform.
23
24 Each port will be represented through a standalone net_device interface,
25 as for other DSA switches. CPU can communicate with any of the ports by
26 setting an IP@ on ethN interface. Ports cannot communicate with each
27 other just yet.
28
29 Link status will be reported through polling, and we don't use any
30 encapsulation.
31
32 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
33 ---
34 drivers/net/dsa/Kconfig | 7 ++
35 drivers/net/dsa/Makefile | 1 +
36 drivers/net/dsa/ar8xxx.c | 303 +++++++++++++++++++++++++++++++++++++++++++++++
37 drivers/net/dsa/ar8xxx.h | 82 +++++++++++++
38 net/dsa/dsa.c | 1 +
39 5 files changed, 394 insertions(+)
40 create mode 100644 drivers/net/dsa/ar8xxx.c
41 create mode 100644 drivers/net/dsa/ar8xxx.h
42
43 diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
44 index 7ad0a4d..2aae541 100644
45 --- a/drivers/net/dsa/Kconfig
46 +++ b/drivers/net/dsa/Kconfig
47 @@ -65,4 +65,11 @@ config NET_DSA_BCM_SF2
48 This enables support for the Broadcom Starfighter 2 Ethernet
49 switch chips.
50
51 +config NET_DSA_AR8XXX
52 + tristate "Qualcomm Atheros AR8XXX Ethernet switch family support"
53 + depends on NET_DSA
54 + ---help---
55 + This enables support for the Qualcomm Atheros AR8XXX Ethernet
56 + switch chips.
57 +
58 endmenu
59 diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
60 index e2d51c4..7647687 100644
61 --- a/drivers/net/dsa/Makefile
62 +++ b/drivers/net/dsa/Makefile
63 @@ -14,3 +14,4 @@ ifdef CONFIG_NET_DSA_MV88E6171
64 mv88e6xxx_drv-y += mv88e6171.o
65 endif
66 obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm_sf2.o
67 +obj-$(CONFIG_NET_DSA_AR8XXX) += ar8xxx.o
68 diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
69 new file mode 100644
70 index 0000000..4ce3ffc
71 --- /dev/null
72 +++ b/drivers/net/dsa/ar8xxx.c
73 @@ -0,0 +1,303 @@
74 +/*
75 + * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
76 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
77 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
78 + *
79 + * This program is free software; you can redistribute it and/or modify
80 + * it under the terms of the GNU General Public License version 2 and
81 + * only version 2 as published by the Free Software Foundation.
82 + *
83 + * This program is distributed in the hope that it will be useful,
84 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
85 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
86 + * GNU General Public License for more details.
87 + */
88 +
89 +#include <linux/module.h>
90 +#include <linux/phy.h>
91 +#include <linux/netdevice.h>
92 +#include <net/dsa.h>
93 +#include <linux/phy.h>
94 +#include <linux/of_net.h>
95 +
96 +#include "ar8xxx.h"
97 +
98 +u32
99 +ar8xxx_mii_read32(struct mii_bus *bus, int phy_id, int regnum)
100 +{
101 + u16 lo, hi;
102 +
103 + lo = bus->read(bus, phy_id, regnum);
104 + hi = bus->read(bus, phy_id, regnum + 1);
105 +
106 + return (hi << 16) | lo;
107 +}
108 +
109 +void
110 +ar8xxx_mii_write32(struct mii_bus *bus, int phy_id, int regnum, u32 val)
111 +{
112 + u16 lo, hi;
113 +
114 + lo = val & 0xffff;
115 + hi = (u16)(val >> 16);
116 +
117 + bus->write(bus, phy_id, regnum, lo);
118 + bus->write(bus, phy_id, regnum + 1, hi);
119 +}
120 +
121 +u32 ar8xxx_read(struct dsa_switch *ds, int reg)
122 +{
123 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
124 + u16 r1, r2, page;
125 + u32 val;
126 +
127 + split_addr((u32)reg, &r1, &r2, &page);
128 +
129 + mutex_lock(&bus->mdio_lock);
130 +
131 + bus->write(bus, 0x18, 0, page);
132 + wait_for_page_switch();
133 + val = ar8xxx_mii_read32(bus, 0x10 | r2, r1);
134 +
135 + mutex_unlock(&bus->mdio_lock);
136 +
137 + return val;
138 +}
139 +
140 +void ar8xxx_write(struct dsa_switch *ds, int reg, u32 val)
141 +{
142 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
143 + u16 r1, r2, page;
144 +
145 + split_addr((u32)reg, &r1, &r2, &page);
146 +
147 + mutex_lock(&bus->mdio_lock);
148 +
149 + bus->write(bus, 0x18, 0, page);
150 + wait_for_page_switch();
151 + ar8xxx_mii_write32(bus, 0x10 | r2, r1, val);
152 +
153 + mutex_unlock(&bus->mdio_lock);
154 +}
155 +
156 +u32
157 +ar8xxx_rmw(struct dsa_switch *ds, int reg, u32 mask, u32 val)
158 +{
159 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
160 + u16 r1, r2, page;
161 + u32 ret;
162 +
163 + split_addr((u32)reg, &r1, &r2, &page);
164 +
165 + mutex_lock(&bus->mdio_lock);
166 +
167 + bus->write(bus, 0x18, 0, page);
168 + wait_for_page_switch();
169 +
170 + ret = ar8xxx_mii_read32(bus, 0x10 | r2, r1);
171 + ret &= ~mask;
172 + ret |= val;
173 + ar8xxx_mii_write32(bus, 0x10 | r2, r1, ret);
174 +
175 + mutex_unlock(&bus->mdio_lock);
176 +
177 + return ret;
178 +}
179 +
180 +static char *ar8xxx_probe(struct device *host_dev, int sw_addr)
181 +{
182 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
183 + u32 phy_id;
184 +
185 + if (!bus)
186 + return NULL;
187 +
188 + /* sw_addr is irrelevant as the switch occupies the MDIO bus from
189 + * addresses 0 to 4 (PHYs) and 16-23 (for MDIO 32bits protocol). So
190 + * we'll probe address 0 to see if we see the right switch family.
191 + */
192 + phy_id = mdiobus_read(bus, 0, MII_PHYSID1) << 16;
193 + phy_id |= mdiobus_read(bus, 0, MII_PHYSID2);
194 +
195 + switch (phy_id) {
196 + case PHY_ID_QCA8337:
197 + return "QCA8337";
198 + default:
199 + return NULL;
200 + }
201 +}
202 +
203 +static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
204 +{
205 + int reg;
206 +
207 + switch (port) {
208 + case 0:
209 + reg = AR8327_REG_PORT0_PAD_CTRL;
210 + break;
211 + case 6:
212 + reg = AR8327_REG_PORT6_PAD_CTRL;
213 + break;
214 + default:
215 + pr_err("Can't set PAD_CTRL on port %d\n", port);
216 + return -EINVAL;
217 + }
218 +
219 + /* DSA only supports 1 CPU port for now, so we'll take the assumption
220 + * that P0 is connected to the CPU master_dev.
221 + */
222 + switch (mode) {
223 + case PHY_INTERFACE_MODE_RGMII:
224 + ar8xxx_write(ds, reg,
225 + AR8327_PORT_PAD_RGMII_EN |
226 + AR8327_PORT_PAD_RGMII_TX_DELAY(3) |
227 + AR8327_PORT_PAD_RGMII_RX_DELAY(3));
228 +
229 + /* According to the datasheet, RGMII delay is enabled through
230 + * PORT5_PAD_CTRL for all ports, rather than individual port
231 + * registers
232 + */
233 + ar8xxx_write(ds, AR8327_REG_PORT5_PAD_CTRL,
234 + AR8327_PORT_PAD_RGMII_RX_DELAY_EN);
235 + break;
236 + default:
237 + pr_err("xMII mode %d not supported\n", mode);
238 + return -EINVAL;
239 + }
240 +
241 + return 0;
242 +}
243 +
244 +static int ar8xxx_setup(struct dsa_switch *ds)
245 +{
246 + struct net_device *netdev = ds->dst->pd->of_netdev;
247 + int ret, i, phy_mode;
248 +
249 + /* Initialize CPU port pad mode (xMII type, delays...) */
250 + phy_mode = of_get_phy_mode(netdev->dev.parent->of_node);
251 + if (phy_mode < 0) {
252 + pr_err("Can't find phy-mode for master device\n");
253 + return phy_mode;
254 + }
255 +
256 + ret = ar8xxx_set_pad_ctrl(ds, 0, phy_mode);
257 + if (ret < 0)
258 + return ret;
259 +
260 + /* Disable forwarding by default on all ports */
261 + for (i = 0; i < AR8327_NUM_PORTS; i++)
262 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),
263 + AR8327_PORT_LOOKUP_MEMBER, 0);
264 +
265 + /* Setup connection between CPU ports & PHYs */
266 + for (i = 0; i < DSA_MAX_PORTS; i++) {
267 + /* CPU port gets connected to all PHYs in the switch */
268 + if (dsa_is_cpu_port(ds, i)) {
269 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(0),
270 + AR8327_PORT_LOOKUP_MEMBER,
271 + ds->phys_port_mask << 1);
272 + }
273 +
274 + /* Invividual PHYs gets connected to CPU port only */
275 + if (ds->phys_port_mask & BIT(i)) {
276 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(i)),
277 + AR8327_PORT_LOOKUP_MEMBER, BIT(0));
278 + }
279 + }
280 +
281 + return 0;
282 +}
283 +
284 +static int ar8xxx_set_addr(struct dsa_switch *ds, u8 *addr)
285 +{
286 + return 0;
287 +}
288 +
289 +static int ar8xxx_phy_read(struct dsa_switch *ds, int phy, int regnum)
290 +{
291 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
292 +
293 + return mdiobus_read(bus, phy, regnum);
294 +}
295 +
296 +static int
297 +ar8xxx_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)
298 +{
299 + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
300 +
301 + return mdiobus_write(bus, phy, regnum, val);
302 +}
303 +
304 +static void ar8xxx_poll_link(struct dsa_switch *ds)
305 +{
306 + int i = 0;
307 + struct net_device *dev;
308 +
309 + while ((dev = ds->ports[i++]) != NULL) {
310 + u32 status;
311 + int link;
312 + int speed;
313 + int duplex;
314 +
315 + status = ar8xxx_read(ds, AR8327_REG_PORT_STATUS(i));
316 + link = !!(status & AR8XXX_PORT_STATUS_LINK_UP);
317 + duplex = !!(status & AR8XXX_PORT_STATUS_DUPLEX);
318 +
319 + switch (status & AR8XXX_PORT_STATUS_SPEED) {
320 + case AR8XXX_PORT_SPEED_10M:
321 + speed = 10;
322 + break;
323 + case AR8XXX_PORT_SPEED_100M:
324 + speed = 100;
325 + break;
326 + case AR8XXX_PORT_SPEED_1000M:
327 + speed = 1000;
328 + break;
329 + default:
330 + speed = 0;
331 + }
332 +
333 + if (!link) {
334 + /* This poll happens every ~1s, so we don't want to
335 + * print the status every time. Only when the device
336 + * transitions from Link UP to Link DOWN
337 + */
338 + if (netif_carrier_ok(dev))
339 + netif_carrier_off(dev);
340 + continue;
341 + } else {
342 + /* Same thing here. But we detect a Link UP event */
343 + if (!netif_carrier_ok(dev))
344 + netif_carrier_on(dev);
345 + continue;
346 + }
347 + }
348 +}
349 +
350 +static struct dsa_switch_driver ar8xxx_switch_driver = {
351 + .tag_protocol = DSA_TAG_PROTO_NONE,
352 + .probe = ar8xxx_probe,
353 + .setup = ar8xxx_setup,
354 + .set_addr = ar8xxx_set_addr,
355 + .poll_link = ar8xxx_poll_link,
356 + .phy_read = ar8xxx_phy_read,
357 + .phy_write = ar8xxx_phy_write,
358 +};
359 +
360 +static int __init ar8xxx_init(void)
361 +{
362 + register_switch_driver(&ar8xxx_switch_driver);
363 + return 0;
364 +}
365 +module_init(ar8xxx_init);
366 +
367 +static void __exit ar8xxx_cleanup(void)
368 +{
369 + unregister_switch_driver(&ar8xxx_switch_driver);
370 +}
371 +module_exit(ar8xxx_cleanup);
372 +
373 +MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
374 +MODULE_DESCRIPTION("Driver for AR8XXX ethernet switch family");
375 +MODULE_LICENSE("GPL");
376 +MODULE_ALIAS("platform:ar8xxx");
377 diff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h
378 new file mode 100644
379 index 0000000..a29b6d3
380 --- /dev/null
381 +++ b/drivers/net/dsa/ar8xxx.h
382 @@ -0,0 +1,82 @@
383 +/*
384 + * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
385 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
386 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
387 + *
388 + * This program is free software; you can redistribute it and/or modify
389 + * it under the terms of the GNU General Public License version 2 and
390 + * only version 2 as published by the Free Software Foundation.
391 + *
392 + * This program is distributed in the hope that it will be useful,
393 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
394 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
395 + * GNU General Public License for more details.
396 + */
397 +
398 +#ifndef __AR8XXX_H
399 +#define __AR8XXX_H
400 +
401 +#include <linux/delay.h>
402 +
403 +#define AR8327_NUM_PORTS 7
404 +
405 +#define PHY_ID_QCA8337 0x004dd036
406 +
407 +#define AR8327_REG_PORT0_PAD_CTRL 0x004
408 +#define AR8327_REG_PORT5_PAD_CTRL 0x008
409 +#define AR8327_REG_PORT6_PAD_CTRL 0x00c
410 +#define AR8327_PORT_PAD_RGMII_EN BIT(26)
411 +#define AR8327_PORT_PAD_RGMII_TX_DELAY(x) ((0x8 + (x & 0x3)) << 22)
412 +#define AR8327_PORT_PAD_RGMII_RX_DELAY(x) ((0x10 + (x & 0x3)) << 20)
413 +#define AR8327_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
414 +#define AR8327_PORT_PAD_SGMII_EN BIT(7)
415 +
416 +#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
417 +#define AR8XXX_PORT_STATUS_SPEED GENMASK(2, 0)
418 +#define AR8XXX_PORT_STATUS_SPEED_S 0
419 +#define AR8XXX_PORT_STATUS_TXMAC BIT(2)
420 +#define AR8XXX_PORT_STATUS_RXMAC BIT(3)
421 +#define AR8XXX_PORT_STATUS_TXFLOW BIT(4)
422 +#define AR8XXX_PORT_STATUS_RXFLOW BIT(5)
423 +#define AR8XXX_PORT_STATUS_DUPLEX BIT(6)
424 +#define AR8XXX_PORT_STATUS_LINK_UP BIT(8)
425 +#define AR8XXX_PORT_STATUS_LINK_AUTO BIT(9)
426 +#define AR8XXX_PORT_STATUS_LINK_PAUSE BIT(10)
427 +
428 +#define AR8327_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
429 +#define AR8327_PORT_LOOKUP_MEMBER GENMASK(6, 0)
430 +#define AR8327_PORT_LOOKUP_IN_MODE GENMASK(9, 8)
431 +#define AR8327_PORT_LOOKUP_IN_MODE_S 8
432 +#define AR8327_PORT_LOOKUP_STATE GENMASK(18, 16)
433 +#define AR8327_PORT_LOOKUP_STATE_S 16
434 +#define AR8327_PORT_LOOKUP_LEARN BIT(20)
435 +#define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
436 +
437 +/* port speed */
438 +enum {
439 + AR8XXX_PORT_SPEED_10M = 0,
440 + AR8XXX_PORT_SPEED_100M = 1,
441 + AR8XXX_PORT_SPEED_1000M = 2,
442 + AR8XXX_PORT_SPEED_ERR = 3,
443 +};
444 +
445 +static inline void
446 +split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
447 +{
448 + regaddr >>= 1;
449 + *r1 = regaddr & 0x1e;
450 +
451 + regaddr >>= 5;
452 + *r2 = regaddr & 0x7;
453 +
454 + regaddr >>= 3;
455 + *page = regaddr & 0x1ff;
456 +}
457 +
458 +static inline void
459 +wait_for_page_switch(void)
460 +{
461 + udelay(5);
462 +}
463 +
464 +#endif /* __AR8XXX_H */
465 diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
466 index e6f6cc3..fffb9aa 100644
467 --- a/net/dsa/dsa.c
468 +++ b/net/dsa/dsa.c
469 @@ -893,6 +893,7 @@ static SIMPLE_DEV_PM_OPS(dsa_pm_ops, dsa_suspend, dsa_resume);
470
471 static const struct of_device_id dsa_of_match_table[] = {
472 { .compatible = "brcm,bcm7445-switch-v4.0" },
473 + { .compatible = "qca,ar8xxx", },
474 { .compatible = "marvell,dsa", },
475 {}
476 };
477
478 From patchwork Fri May 29 01:42:17 2015
479 Content-Type: text/plain; charset="utf-8"
480 MIME-Version: 1.0
481 Content-Transfer-Encoding: 7bit
482 Subject: [2/7] net: dsa: ar8xxx: add ethtool hw statistics support
483 From: Mathieu Olivari <mathieu@codeaurora.org>
484 X-Patchwork-Id: 477524
485 X-Patchwork-Delegate: davem@davemloft.net
486 Message-Id: <1432863742-18427-3-git-send-email-mathieu@codeaurora.org>
487 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
488 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
489 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
490 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
491 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
492 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
493 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
494 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
495 netdev@vger.kernel.org
496 Date: Thu, 28 May 2015 18:42:17 -0700
497
498 MIB counters can now be reported through each switch port by using
499 "ethtool -S".
500
501 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
502 ---
503 drivers/net/dsa/ar8xxx.c | 106 +++++++++++++++++++++++++++++++++++++++++++----
504 drivers/net/dsa/ar8xxx.h | 47 +++++++++++++++++++++
505 2 files changed, 146 insertions(+), 7 deletions(-)
506
507 diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
508 index 4ce3ffc..2f0fa4d 100644
509 --- a/drivers/net/dsa/ar8xxx.c
510 +++ b/drivers/net/dsa/ar8xxx.c
511 @@ -22,6 +22,55 @@
512
513 #include "ar8xxx.h"
514
515 +#define MIB_DESC(_s, _o, _n) \
516 + { \
517 + .size = (_s), \
518 + .offset = (_o), \
519 + .name = (_n), \
520 + }
521 +
522 +static const struct ar8xxx_mib_desc ar8327_mib[] = {
523 + MIB_DESC(1, 0x00, "RxBroad"),
524 + MIB_DESC(1, 0x04, "RxPause"),
525 + MIB_DESC(1, 0x08, "RxMulti"),
526 + MIB_DESC(1, 0x0c, "RxFcsErr"),
527 + MIB_DESC(1, 0x10, "RxAlignErr"),
528 + MIB_DESC(1, 0x14, "RxRunt"),
529 + MIB_DESC(1, 0x18, "RxFragment"),
530 + MIB_DESC(1, 0x1c, "Rx64Byte"),
531 + MIB_DESC(1, 0x20, "Rx128Byte"),
532 + MIB_DESC(1, 0x24, "Rx256Byte"),
533 + MIB_DESC(1, 0x28, "Rx512Byte"),
534 + MIB_DESC(1, 0x2c, "Rx1024Byte"),
535 + MIB_DESC(1, 0x30, "Rx1518Byte"),
536 + MIB_DESC(1, 0x34, "RxMaxByte"),
537 + MIB_DESC(1, 0x38, "RxTooLong"),
538 + MIB_DESC(2, 0x3c, "RxGoodByte"),
539 + MIB_DESC(2, 0x44, "RxBadByte"),
540 + MIB_DESC(1, 0x4c, "RxOverFlow"),
541 + MIB_DESC(1, 0x50, "Filtered"),
542 + MIB_DESC(1, 0x54, "TxBroad"),
543 + MIB_DESC(1, 0x58, "TxPause"),
544 + MIB_DESC(1, 0x5c, "TxMulti"),
545 + MIB_DESC(1, 0x60, "TxUnderRun"),
546 + MIB_DESC(1, 0x64, "Tx64Byte"),
547 + MIB_DESC(1, 0x68, "Tx128Byte"),
548 + MIB_DESC(1, 0x6c, "Tx256Byte"),
549 + MIB_DESC(1, 0x70, "Tx512Byte"),
550 + MIB_DESC(1, 0x74, "Tx1024Byte"),
551 + MIB_DESC(1, 0x78, "Tx1518Byte"),
552 + MIB_DESC(1, 0x7c, "TxMaxByte"),
553 + MIB_DESC(1, 0x80, "TxOverSize"),
554 + MIB_DESC(2, 0x84, "TxByte"),
555 + MIB_DESC(1, 0x8c, "TxCollision"),
556 + MIB_DESC(1, 0x90, "TxAbortCol"),
557 + MIB_DESC(1, 0x94, "TxMultiCol"),
558 + MIB_DESC(1, 0x98, "TxSingleCol"),
559 + MIB_DESC(1, 0x9c, "TxExcDefer"),
560 + MIB_DESC(1, 0xa0, "TxDefer"),
561 + MIB_DESC(1, 0xa4, "TxLateCol"),
562 +};
563 +
564 u32
565 ar8xxx_mii_read32(struct mii_bus *bus, int phy_id, int regnum)
566 {
567 @@ -184,6 +233,10 @@ static int ar8xxx_setup(struct dsa_switch *ds)
568 if (ret < 0)
569 return ret;
570
571 + /* Enable MIB counters */
572 + ar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);
573 + ar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);
574 +
575 /* Disable forwarding by default on all ports */
576 for (i = 0; i < AR8327_NUM_PORTS; i++)
577 ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),
578 @@ -228,6 +281,42 @@ ar8xxx_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)
579 return mdiobus_write(bus, phy, regnum, val);
580 }
581
582 +static void ar8xxx_get_strings(struct dsa_switch *ds, int phy, uint8_t *data)
583 +{
584 + int i;
585 +
586 + for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
587 + strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
588 + ETH_GSTRING_LEN);
589 + }
590 +}
591 +
592 +static void ar8xxx_get_ethtool_stats(struct dsa_switch *ds, int phy,
593 + uint64_t *data)
594 +{
595 + const struct ar8xxx_mib_desc *mib;
596 + uint32_t reg, i, port;
597 + u64 hi;
598 +
599 + port = phy_to_port(phy);
600 +
601 + for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
602 + mib = &ar8327_mib[i];
603 + reg = AR8327_PORT_MIB_COUNTER(port) + mib->offset;
604 +
605 + data[i] = ar8xxx_read(ds, reg);
606 + if (mib->size == 2) {
607 + hi = ar8xxx_read(ds, reg + 4);
608 + data[i] |= hi << 32;
609 + }
610 + }
611 +}
612 +
613 +static int ar8xxx_get_sset_count(struct dsa_switch *ds)
614 +{
615 + return ARRAY_SIZE(ar8327_mib);
616 +}
617 +
618 static void ar8xxx_poll_link(struct dsa_switch *ds)
619 {
620 int i = 0;
621 @@ -275,13 +364,16 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
622 }
623
624 static struct dsa_switch_driver ar8xxx_switch_driver = {
625 - .tag_protocol = DSA_TAG_PROTO_NONE,
626 - .probe = ar8xxx_probe,
627 - .setup = ar8xxx_setup,
628 - .set_addr = ar8xxx_set_addr,
629 - .poll_link = ar8xxx_poll_link,
630 - .phy_read = ar8xxx_phy_read,
631 - .phy_write = ar8xxx_phy_write,
632 + .tag_protocol = DSA_TAG_PROTO_NONE,
633 + .probe = ar8xxx_probe,
634 + .setup = ar8xxx_setup,
635 + .set_addr = ar8xxx_set_addr,
636 + .poll_link = ar8xxx_poll_link,
637 + .phy_read = ar8xxx_phy_read,
638 + .phy_write = ar8xxx_phy_write,
639 + .get_strings = ar8xxx_get_strings,
640 + .get_ethtool_stats = ar8xxx_get_ethtool_stats,
641 + .get_sset_count = ar8xxx_get_sset_count,
642 };
643
644 static int __init ar8xxx_init(void)
645 diff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h
646 index a29b6d3..7c7a125 100644
647 --- a/drivers/net/dsa/ar8xxx.h
648 +++ b/drivers/net/dsa/ar8xxx.h
649 @@ -18,6 +18,12 @@
650
651 #include <linux/delay.h>
652
653 +struct ar8xxx_mib_desc {
654 + unsigned int size;
655 + unsigned int offset;
656 + const char *name;
657 +};
658 +
659 #define AR8327_NUM_PORTS 7
660
661 #define PHY_ID_QCA8337 0x004dd036
662 @@ -31,6 +37,14 @@
663 #define AR8327_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
664 #define AR8327_PORT_PAD_SGMII_EN BIT(7)
665
666 +#define AR8327_REG_MODULE_EN 0x030
667 +#define AR8327_MODULE_EN_MIB BIT(0)
668 +#define AR8327_MODULE_EN_ACL BIT(1)
669 +#define AR8327_MODULE_EN_L3 BIT(2)
670 +
671 +#define AR8327_REG_MIB 0x034
672 +#define AR8327_MIB_CPU_KEEP BIT(20)
673 +
674 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
675 #define AR8XXX_PORT_STATUS_SPEED GENMASK(2, 0)
676 #define AR8XXX_PORT_STATUS_SPEED_S 0
677 @@ -52,6 +66,8 @@
678 #define AR8327_PORT_LOOKUP_LEARN BIT(20)
679 #define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
680
681 +#define AR8327_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
682 +
683 /* port speed */
684 enum {
685 AR8XXX_PORT_SPEED_10M = 0,
686 @@ -60,6 +76,25 @@ enum {
687 AR8XXX_PORT_SPEED_ERR = 3,
688 };
689
690 +static inline int port_to_phy(int port)
691 +{
692 + if (port >= 1 && port <= 6)
693 + return port - 1;
694 +
695 + return -1;
696 +}
697 +
698 +static inline int phy_to_port(int phy)
699 +{
700 + if (phy < 5)
701 + return phy + 1;
702 +
703 + return -1;
704 +}
705 +
706 +u32
707 +ar8xxx_rmw(struct dsa_switch *ds, int reg, u32 mask, u32 val);
708 +
709 static inline void
710 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
711 {
712 @@ -79,4 +114,16 @@ wait_for_page_switch(void)
713 udelay(5);
714 }
715
716 +static inline void
717 +ar8xxx_reg_set(struct dsa_switch *ds, int reg, u32 val)
718 +{
719 + ar8xxx_rmw(ds, reg, 0, val);
720 +}
721 +
722 +static inline void
723 +ar8xxx_reg_clear(struct dsa_switch *ds, int reg, u32 val)
724 +{
725 + ar8xxx_rmw(ds, reg, val, 0);
726 +}
727 +
728 #endif /* __AR8XXX_H */
729
730 From patchwork Fri May 29 01:42:18 2015
731 Content-Type: text/plain; charset="utf-8"
732 MIME-Version: 1.0
733 Content-Transfer-Encoding: 7bit
734 Subject: [3/7] net: dsa: ar8xxx: add regmap support
735 From: Mathieu Olivari <mathieu@codeaurora.org>
736 X-Patchwork-Id: 477522
737 X-Patchwork-Delegate: davem@davemloft.net
738 Message-Id: <1432863742-18427-4-git-send-email-mathieu@codeaurora.org>
739 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
740 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
741 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
742 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
743 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
744 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
745 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
746 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
747 netdev@vger.kernel.org
748 Date: Thu, 28 May 2015 18:42:18 -0700
749
750 All switch registers can now be dumped using regmap/debugfs.
751
752 \# cat /sys/kernel/debug/regmap/<mdiobus>/registers
753 0000: 00001302
754 0004: ...
755 ...
756
757 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
758 ---
759 drivers/net/dsa/Kconfig | 1 +
760 drivers/net/dsa/ar8xxx.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++
761 drivers/net/dsa/ar8xxx.h | 5 ++++
762 3 files changed, 66 insertions(+)
763
764 diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
765 index 2aae541..17fb296 100644
766 --- a/drivers/net/dsa/Kconfig
767 +++ b/drivers/net/dsa/Kconfig
768 @@ -68,6 +68,7 @@ config NET_DSA_BCM_SF2
769 config NET_DSA_AR8XXX
770 tristate "Qualcomm Atheros AR8XXX Ethernet switch family support"
771 depends on NET_DSA
772 + select REGMAP
773 ---help---
774 This enables support for the Qualcomm Atheros AR8XXX Ethernet
775 switch chips.
776 diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
777 index 2f0fa4d..327abd4 100644
778 --- a/drivers/net/dsa/ar8xxx.c
779 +++ b/drivers/net/dsa/ar8xxx.c
780 @@ -176,6 +176,57 @@ static char *ar8xxx_probe(struct device *host_dev, int sw_addr)
781 }
782 }
783
784 +static int ar8xxx_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
785 +{
786 + struct dsa_switch *ds = (struct dsa_switch *)ctx;
787 +
788 + *val = ar8xxx_read(ds, reg);
789 +
790 + return 0;
791 +}
792 +
793 +static int ar8xxx_regmap_write(void *ctx, uint32_t reg, uint32_t val)
794 +{
795 + struct dsa_switch *ds = (struct dsa_switch *)ctx;
796 +
797 + ar8xxx_write(ds, reg, val);
798 +
799 + return 0;
800 +}
801 +
802 +static const struct regmap_range ar8xxx_readable_ranges[] = {
803 + regmap_reg_range(0x0000, 0x00e4), /* Global control */
804 + regmap_reg_range(0x0100, 0x0168), /* EEE control */
805 + regmap_reg_range(0x0200, 0x0270), /* Parser control */
806 + regmap_reg_range(0x0400, 0x0454), /* ACL */
807 + regmap_reg_range(0x0600, 0x0718), /* Lookup */
808 + regmap_reg_range(0x0800, 0x0b70), /* QM */
809 + regmap_reg_range(0x0C00, 0x0c80), /* PKT */
810 + regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
811 + regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
812 + regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
813 + regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
814 + regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
815 + regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
816 + regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
817 +
818 +};
819 +
820 +static struct regmap_access_table ar8xxx_readable_table = {
821 + .yes_ranges = ar8xxx_readable_ranges,
822 + .n_yes_ranges = ARRAY_SIZE(ar8xxx_readable_ranges),
823 +};
824 +
825 +struct regmap_config ar8xxx_regmap_config = {
826 + .reg_bits = 16,
827 + .val_bits = 32,
828 + .reg_stride = 4,
829 + .max_register = 0x16ac, /* end MIB - Port6 range */
830 + .reg_read = ar8xxx_regmap_read,
831 + .reg_write = ar8xxx_regmap_write,
832 + .rd_table = &ar8xxx_readable_table,
833 +};
834 +
835 static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
836 {
837 int reg;
838 @@ -219,9 +270,17 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
839
840 static int ar8xxx_setup(struct dsa_switch *ds)
841 {
842 + struct ar8xxx_priv *priv = ds_to_priv(ds);
843 struct net_device *netdev = ds->dst->pd->of_netdev;
844 int ret, i, phy_mode;
845
846 + /* Start by setting up the register mapping */
847 + priv->regmap = devm_regmap_init(ds->master_dev, NULL, ds,
848 + &ar8xxx_regmap_config);
849 +
850 + if (IS_ERR(priv->regmap))
851 + pr_warn("regmap initialization failed");
852 +
853 /* Initialize CPU port pad mode (xMII type, delays...) */
854 phy_mode = of_get_phy_mode(netdev->dev.parent->of_node);
855 if (phy_mode < 0) {
856 @@ -365,6 +424,7 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
857
858 static struct dsa_switch_driver ar8xxx_switch_driver = {
859 .tag_protocol = DSA_TAG_PROTO_NONE,
860 + .priv_size = sizeof(struct ar8xxx_priv),
861 .probe = ar8xxx_probe,
862 .setup = ar8xxx_setup,
863 .set_addr = ar8xxx_set_addr,
864 diff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h
865 index 7c7a125..98cc7ed 100644
866 --- a/drivers/net/dsa/ar8xxx.h
867 +++ b/drivers/net/dsa/ar8xxx.h
868 @@ -17,6 +17,11 @@
869 #define __AR8XXX_H
870
871 #include <linux/delay.h>
872 +#include <linux/regmap.h>
873 +
874 +struct ar8xxx_priv {
875 + struct regmap *regmap;
876 +};
877
878 struct ar8xxx_mib_desc {
879 unsigned int size;
880
881 From patchwork Fri May 29 01:42:19 2015
882 Content-Type: text/plain; charset="utf-8"
883 MIME-Version: 1.0
884 Content-Transfer-Encoding: 7bit
885 Subject: [4/7] net: dsa: add QCA tag support
886 From: Mathieu Olivari <mathieu@codeaurora.org>
887 X-Patchwork-Id: 477521
888 X-Patchwork-Delegate: davem@davemloft.net
889 Message-Id: <1432863742-18427-5-git-send-email-mathieu@codeaurora.org>
890 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
891 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
892 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
893 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
894 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
895 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
896 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
897 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
898 netdev@vger.kernel.org
899 Date: Thu, 28 May 2015 18:42:19 -0700
900
901 QCA tags are used on QCA ar8xxx switch family. This change adds support
902 for encap/decap using 2 bytes header mode.
903
904 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
905 ---
906 include/net/dsa.h | 1 +
907 net/dsa/Kconfig | 3 +
908 net/dsa/Makefile | 1 +
909 net/dsa/dsa.c | 5 ++
910 net/dsa/dsa_priv.h | 2 +
911 net/dsa/slave.c | 5 ++
912 net/dsa/tag_qca.c | 158 +++++++++++++++++++++++++++++++++++++++++++++++++++++
913 7 files changed, 175 insertions(+)
914 create mode 100644 net/dsa/tag_qca.c
915
916 diff --git a/include/net/dsa.h b/include/net/dsa.h
917 index fbca63b..64ddf6f 100644
918 --- a/include/net/dsa.h
919 +++ b/include/net/dsa.h
920 @@ -26,6 +26,7 @@ enum dsa_tag_protocol {
921 DSA_TAG_PROTO_TRAILER,
922 DSA_TAG_PROTO_EDSA,
923 DSA_TAG_PROTO_BRCM,
924 + DSA_TAG_PROTO_QCA,
925 };
926
927 #define DSA_MAX_SWITCHES 4
928 diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
929 index ff7736f..4f3cce1 100644
930 --- a/net/dsa/Kconfig
931 +++ b/net/dsa/Kconfig
932 @@ -26,6 +26,9 @@ config NET_DSA_HWMON
933 via the hwmon sysfs interface and exposes the onboard sensors.
934
935 # tagging formats
936 +config NET_DSA_TAG_QCA
937 + bool
938 +
939 config NET_DSA_TAG_BRCM
940 bool
941
942 diff --git a/net/dsa/Makefile b/net/dsa/Makefile
943 index da06ed1..9feb86c 100644
944 --- a/net/dsa/Makefile
945 +++ b/net/dsa/Makefile
946 @@ -3,6 +3,7 @@ obj-$(CONFIG_NET_DSA) += dsa_core.o
947 dsa_core-y += dsa.o slave.o
948
949 # tagging formats
950 +dsa_core-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
951 dsa_core-$(CONFIG_NET_DSA_TAG_BRCM) += tag_brcm.o
952 dsa_core-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
953 dsa_core-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
954 diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
955 index fffb9aa..6010a7d 100644
956 --- a/net/dsa/dsa.c
957 +++ b/net/dsa/dsa.c
958 @@ -249,6 +249,11 @@ static int dsa_switch_setup_one(struct dsa_switch *ds, struct device *parent)
959 dst->rcv = brcm_netdev_ops.rcv;
960 break;
961 #endif
962 +#ifdef CONFIG_NET_DSA_TAG_QCA
963 + case DSA_TAG_PROTO_QCA:
964 + dst->rcv = qca_netdev_ops.rcv;
965 + break;
966 +#endif
967 case DSA_TAG_PROTO_NONE:
968 break;
969 default:
970 diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
971 index d5f1f9b..350c94b 100644
972 --- a/net/dsa/dsa_priv.h
973 +++ b/net/dsa/dsa_priv.h
974 @@ -74,5 +74,7 @@ extern const struct dsa_device_ops trailer_netdev_ops;
975 /* tag_brcm.c */
976 extern const struct dsa_device_ops brcm_netdev_ops;
977
978 +/* tag_qca.c */
979 +extern const struct dsa_device_ops qca_netdev_ops;
980
981 #endif
982 diff --git a/net/dsa/slave.c b/net/dsa/slave.c
983 index 04ffad3..cd8f552 100644
984 --- a/net/dsa/slave.c
985 +++ b/net/dsa/slave.c
986 @@ -925,6 +925,11 @@ int dsa_slave_create(struct dsa_switch *ds, struct device *parent,
987 p->xmit = brcm_netdev_ops.xmit;
988 break;
989 #endif
990 +#ifdef CONFIG_NET_DSA_TAG_QCA
991 + case DSA_TAG_PROTO_QCA:
992 + p->xmit = qca_netdev_ops.xmit;
993 + break;
994 +#endif
995 default:
996 p->xmit = dsa_slave_notag_xmit;
997 break;
998 diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c
999 new file mode 100644
1000 index 0000000..8f02196
1001 --- /dev/null
1002 +++ b/net/dsa/tag_qca.c
1003 @@ -0,0 +1,158 @@
1004 +/*
1005 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
1006 + *
1007 + * This program is free software; you can redistribute it and/or modify
1008 + * it under the terms of the GNU General Public License version 2 and
1009 + * only version 2 as published by the Free Software Foundation.
1010 + *
1011 + * This program is distributed in the hope that it will be useful,
1012 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1013 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1014 + * GNU General Public License for more details.
1015 + */
1016 +
1017 +#include <linux/etherdevice.h>
1018 +#include "dsa_priv.h"
1019 +
1020 +#define QCA_HDR_LEN 2
1021 +#define QCA_HDR_VERSION 0x2
1022 +
1023 +#define QCA_HDR_RECV_VERSION_MASK GENMASK(15, 14)
1024 +#define QCA_HDR_RECV_VERSION_S 14
1025 +#define QCA_HDR_RECV_PRIORITY_MASK GENMASK(13, 11)
1026 +#define QCA_HDR_RECV_PRIORITY_S 11
1027 +#define QCA_HDR_RECV_TYPE_MASK GENMASK(10, 6)
1028 +#define QCA_HDR_RECV_TYPE_S 6
1029 +#define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3)
1030 +#define QCA_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)
1031 +
1032 +#define QCA_HDR_XMIT_VERSION_MASK GENMASK(15, 14)
1033 +#define QCA_HDR_XMIT_VERSION_S 14
1034 +#define QCA_HDR_XMIT_PRIORITY_MASK GENMASK(13, 11)
1035 +#define QCA_HDR_XMIT_PRIORITY_S 11
1036 +#define QCA_HDR_XMIT_CONTROL_MASK GENMASK(10, 8)
1037 +#define QCA_HDR_XMIT_CONTROL_S 8
1038 +#define QCA_HDR_XMIT_FROM_CPU BIT(7)
1039 +#define QCA_HDR_XMIT_DP_BIT_MASK GENMASK(6, 0)
1040 +
1041 +static inline int reg_to_port(int reg)
1042 +{
1043 + if (reg < 5)
1044 + return reg + 1;
1045 +
1046 + return -1;
1047 +}
1048 +
1049 +static inline int port_to_reg(int port)
1050 +{
1051 + if (port >= 1 && port <= 6)
1052 + return port - 1;
1053 +
1054 + return -1;
1055 +}
1056 +
1057 +static netdev_tx_t qca_tag_xmit(struct sk_buff *skb, struct net_device *dev)
1058 +{
1059 + struct dsa_slave_priv *p = netdev_priv(dev);
1060 + u16 *phdr, hdr;
1061 +
1062 + dev->stats.tx_packets++;
1063 + dev->stats.tx_bytes += skb->len;
1064 +
1065 + if (skb_cow_head(skb, 0) < 0)
1066 + goto out_free;
1067 +
1068 + skb_push(skb, QCA_HDR_LEN);
1069 +
1070 + memmove(skb->data, skb->data + QCA_HDR_LEN, 2 * ETH_ALEN);
1071 + phdr = (u16 *)(skb->data + 2 * ETH_ALEN);
1072 +
1073 + /* Set the version field, and set destination port information */
1074 + hdr = QCA_HDR_VERSION << QCA_HDR_XMIT_VERSION_S |
1075 + QCA_HDR_XMIT_FROM_CPU |
1076 + 1 << reg_to_port(p->port);
1077 +
1078 + *phdr = htons(hdr);
1079 +
1080 + skb->dev = p->parent->dst->master_netdev;
1081 + dev_queue_xmit(skb);
1082 +
1083 + return NETDEV_TX_OK;
1084 +
1085 +out_free:
1086 + kfree_skb(skb);
1087 + return NETDEV_TX_OK;
1088 +}
1089 +
1090 +static int qca_tag_rcv(struct sk_buff *skb, struct net_device *dev,
1091 + struct packet_type *pt, struct net_device *orig_dev)
1092 +{
1093 + struct dsa_switch_tree *dst = dev->dsa_ptr;
1094 + struct dsa_switch *ds;
1095 + u8 ver;
1096 + int port, phy;
1097 + __be16 *phdr, hdr;
1098 +
1099 + if (unlikely(!dst))
1100 + goto out_drop;
1101 +
1102 + skb = skb_unshare(skb, GFP_ATOMIC);
1103 + if (!skb)
1104 + goto out;
1105 +
1106 + if (unlikely(!pskb_may_pull(skb, QCA_HDR_LEN)))
1107 + goto out_drop;
1108 +
1109 + /* Ethernet is added by the switch between src addr and Ethertype
1110 + * At this point, skb->data points to ethertype so header should be
1111 + * right before
1112 + */
1113 + phdr = (__be16 *)(skb->data - 2);
1114 + hdr = ntohs(*phdr);
1115 +
1116 + /* Make sure the version is correct */
1117 + ver = (hdr & QCA_HDR_RECV_VERSION_MASK) >> QCA_HDR_RECV_VERSION_S;
1118 + if (unlikely(ver != QCA_HDR_VERSION))
1119 + goto out_drop;
1120 +
1121 + /* Remove QCA tag and recalculate checksum */
1122 + skb_pull_rcsum(skb, QCA_HDR_LEN);
1123 + memmove(skb->data - ETH_HLEN, skb->data - ETH_HLEN - QCA_HDR_LEN,
1124 + ETH_HLEN - QCA_HDR_LEN);
1125 +
1126 + /* This protocol doesn't support cascading multiple switches so it's
1127 + * safe to assume the switch is first in the tree
1128 + */
1129 + ds = dst->ds[0];
1130 + if (!ds)
1131 + goto out_drop;
1132 +
1133 + /* Get source port information */
1134 + port = (hdr & QCA_HDR_RECV_SOURCE_PORT_MASK);
1135 + phy = port_to_reg(port);
1136 + if (unlikely(phy < 0) || !ds->ports[phy])
1137 + goto out_drop;
1138 +
1139 + /* Update skb & forward the frame accordingly */
1140 + skb_push(skb, ETH_HLEN);
1141 + skb->pkt_type = PACKET_HOST;
1142 + skb->dev = ds->ports[phy];
1143 + skb->protocol = eth_type_trans(skb, skb->dev);
1144 +
1145 + skb->dev->stats.rx_packets++;
1146 + skb->dev->stats.rx_bytes += skb->len;
1147 +
1148 + netif_receive_skb(skb);
1149 +
1150 + return 0;
1151 +
1152 +out_drop:
1153 + kfree_skb(skb);
1154 +out:
1155 + return 0;
1156 +}
1157 +
1158 +const struct dsa_device_ops qca_netdev_ops = {
1159 + .xmit = qca_tag_xmit,
1160 + .rcv = qca_tag_rcv,
1161 +};
1162
1163 From patchwork Fri May 29 01:42:20 2015
1164 Content-Type: text/plain; charset="utf-8"
1165 MIME-Version: 1.0
1166 Content-Transfer-Encoding: 7bit
1167 Subject: [5/7] net: dsa: ar8xxx: enable QCA header support on AR8xxx
1168 From: Mathieu Olivari <mathieu@codeaurora.org>
1169 X-Patchwork-Id: 477527
1170 X-Patchwork-Delegate: davem@davemloft.net
1171 Message-Id: <1432863742-18427-6-git-send-email-mathieu@codeaurora.org>
1172 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
1173 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
1174 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
1175 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
1176 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
1177 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
1178 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
1179 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
1180 netdev@vger.kernel.org
1181 Date: Thu, 28 May 2015 18:42:20 -0700
1182
1183 This change enable support for the QCA headers in QCA83337 driver.
1184 A 2 bytes header will be added by the switch on every incoming packet
1185 to identify the ingress port, and the DSA tagging code will add a
1186 similar 2 bytes header to control which port is used to send a
1187 particular packet.
1188
1189 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
1190 ---
1191 drivers/net/dsa/Kconfig | 1 +
1192 drivers/net/dsa/ar8xxx.c | 28 ++++++++++++++++++++++++++--
1193 drivers/net/dsa/ar8xxx.h | 22 ++++++++++++++++++++++
1194 3 files changed, 49 insertions(+), 2 deletions(-)
1195
1196 diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
1197 index 17fb296..fa8b484 100644
1198 --- a/drivers/net/dsa/Kconfig
1199 +++ b/drivers/net/dsa/Kconfig
1200 @@ -68,6 +68,7 @@ config NET_DSA_BCM_SF2
1201 config NET_DSA_AR8XXX
1202 tristate "Qualcomm Atheros AR8XXX Ethernet switch family support"
1203 depends on NET_DSA
1204 + select NET_DSA_TAG_QCA
1205 select REGMAP
1206 ---help---
1207 This enables support for the Qualcomm Atheros AR8XXX Ethernet
1208 diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
1209 index 327abd4..4044614 100644
1210 --- a/drivers/net/dsa/ar8xxx.c
1211 +++ b/drivers/net/dsa/ar8xxx.c
1212 @@ -292,15 +292,31 @@ static int ar8xxx_setup(struct dsa_switch *ds)
1213 if (ret < 0)
1214 return ret;
1215
1216 + /* Enable CPU Port */
1217 + ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL0,
1218 + AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1219 +
1220 /* Enable MIB counters */
1221 ar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);
1222 ar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);
1223
1224 + /* Enable QCA header mode on Port 0 */
1225 + ar8xxx_write(ds, AR8327_REG_PORT_HDR_CTRL(0),
1226 + AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_TX_S |
1227 + AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_RX_S);
1228 +
1229 /* Disable forwarding by default on all ports */
1230 for (i = 0; i < AR8327_NUM_PORTS; i++)
1231 ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),
1232 AR8327_PORT_LOOKUP_MEMBER, 0);
1233
1234 + /* Forward all unknown frames to CPU port for Linux processing */
1235 + ar8xxx_write(ds, AR8327_REG_GLOBAL_FW_CTRL1,
1236 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
1237 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
1238 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
1239 + BIT(0) << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
1240 +
1241 /* Setup connection between CPU ports & PHYs */
1242 for (i = 0; i < DSA_MAX_PORTS; i++) {
1243 /* CPU port gets connected to all PHYs in the switch */
1244 @@ -312,8 +328,16 @@ static int ar8xxx_setup(struct dsa_switch *ds)
1245
1246 /* Invividual PHYs gets connected to CPU port only */
1247 if (ds->phys_port_mask & BIT(i)) {
1248 - ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(i)),
1249 + int phy = phy_to_port(i);
1250 +
1251 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy),
1252 AR8327_PORT_LOOKUP_MEMBER, BIT(0));
1253 +
1254 + /* Disable Auto-learning by default so the switch
1255 + * doesn't try to forward the frame to another port
1256 + */
1257 + ar8xxx_reg_clear(ds, AR8327_PORT_LOOKUP_CTRL(phy),
1258 + AR8327_PORT_LOOKUP_LEARN);
1259 }
1260 }
1261
1262 @@ -423,7 +447,7 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
1263 }
1264
1265 static struct dsa_switch_driver ar8xxx_switch_driver = {
1266 - .tag_protocol = DSA_TAG_PROTO_NONE,
1267 + .tag_protocol = DSA_TAG_PROTO_QCA,
1268 .priv_size = sizeof(struct ar8xxx_priv),
1269 .probe = ar8xxx_probe,
1270 .setup = ar8xxx_setup,
1271 diff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h
1272 index 98cc7ed..e68b92a 100644
1273 --- a/drivers/net/dsa/ar8xxx.h
1274 +++ b/drivers/net/dsa/ar8xxx.h
1275 @@ -62,6 +62,28 @@ struct ar8xxx_mib_desc {
1276 #define AR8XXX_PORT_STATUS_LINK_AUTO BIT(9)
1277 #define AR8XXX_PORT_STATUS_LINK_PAUSE BIT(10)
1278
1279 +#define AR8327_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
1280 +#define AR8327_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
1281 +#define AR8327_PORT_HDR_CTRL_RX_S 2
1282 +#define AR8327_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
1283 +#define AR8327_PORT_HDR_CTRL_TX_S 0
1284 +#define AR8327_PORT_HDR_CTRL_ALL 2
1285 +#define AR8327_PORT_HDR_CTRL_MGMT 1
1286 +#define AR8327_PORT_HDR_CTRL_NONE 0
1287 +
1288 +#define AR8327_REG_GLOBAL_FW_CTRL0 0x620
1289 +#define AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
1290 +
1291 +#define AR8327_REG_GLOBAL_FW_CTRL1 0x624
1292 +#define AR8327_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
1293 +#define AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S 24
1294 +#define AR8327_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
1295 +#define AR8327_GLOBAL_FW_CTRL1_BC_DP_S 16
1296 +#define AR8327_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
1297 +#define AR8327_GLOBAL_FW_CTRL1_MC_DP_S 8
1298 +#define AR8327_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
1299 +#define AR8327_GLOBAL_FW_CTRL1_UC_DP_S 0
1300 +
1301 #define AR8327_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
1302 #define AR8327_PORT_LOOKUP_MEMBER GENMASK(6, 0)
1303 #define AR8327_PORT_LOOKUP_IN_MODE GENMASK(9, 8)
1304
1305 From patchwork Fri May 29 01:42:21 2015
1306 Content-Type: text/plain; charset="utf-8"
1307 MIME-Version: 1.0
1308 Content-Transfer-Encoding: 7bit
1309 Subject: [6/7] net: dsa: ar8xxx: add support for second xMII interfaces
1310 through DT
1311 From: Mathieu Olivari <mathieu@codeaurora.org>
1312 X-Patchwork-Id: 477525
1313 X-Patchwork-Delegate: davem@davemloft.net
1314 Message-Id: <1432863742-18427-7-git-send-email-mathieu@codeaurora.org>
1315 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
1316 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
1317 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
1318 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
1319 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
1320 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
1321 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
1322 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
1323 netdev@vger.kernel.org
1324 Date: Thu, 28 May 2015 18:42:21 -0700
1325
1326 This patch is adding support for port6 specific options to device tree.
1327 They can be used to setup the second xMII interface, and connect it to
1328 one of the switch port.
1329
1330 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
1331 ---
1332 drivers/net/dsa/ar8xxx.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
1333 1 file changed, 50 insertions(+)
1334
1335 diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
1336 index 4044614..7559249 100644
1337 --- a/drivers/net/dsa/ar8xxx.c
1338 +++ b/drivers/net/dsa/ar8xxx.c
1339 @@ -19,6 +19,7 @@
1340 #include <net/dsa.h>
1341 #include <linux/phy.h>
1342 #include <linux/of_net.h>
1343 +#include <linux/of_platform.h>
1344
1345 #include "ar8xxx.h"
1346
1347 @@ -260,6 +261,9 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
1348 ar8xxx_write(ds, AR8327_REG_PORT5_PAD_CTRL,
1349 AR8327_PORT_PAD_RGMII_RX_DELAY_EN);
1350 break;
1351 + case PHY_INTERFACE_MODE_SGMII:
1352 + ar8xxx_write(ds, reg, AR8327_PORT_PAD_SGMII_EN);
1353 + break;
1354 default:
1355 pr_err("xMII mode %d not supported\n", mode);
1356 return -EINVAL;
1357 @@ -268,6 +272,48 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
1358 return 0;
1359 }
1360
1361 +static int ar8xxx_of_setup(struct dsa_switch *ds)
1362 +{
1363 + struct device_node *dn = ds->pd->of_node;
1364 + const char *s_phymode;
1365 + int ret, mode;
1366 + u32 phy_id, ctrl;
1367 +
1368 + /* If port6-phy-mode property exists, configure it accordingly */
1369 + if (!of_property_read_string(dn, "qca,port6-phy-mode", &s_phymode)) {
1370 + for (mode = 0; mode < PHY_INTERFACE_MODE_MAX; mode++)
1371 + if (!strcasecmp(s_phymode, phy_modes(mode)))
1372 + break;
1373 +
1374 + if (mode == PHY_INTERFACE_MODE_MAX)
1375 + pr_err("Unknown phy-mode: \"%s\"\n", s_phymode);
1376 +
1377 + ret = ar8xxx_set_pad_ctrl(ds, 6, mode);
1378 + if (ret < 0)
1379 + return ret;
1380 + }
1381 +
1382 + /* If a phy ID is specified for PORT6 mac, connect them together */
1383 + if (!of_property_read_u32(dn, "qca,port6-phy-id", &phy_id)) {
1384 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(6),
1385 + AR8327_PORT_LOOKUP_MEMBER, BIT(phy_to_port(phy_id)));
1386 + ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(phy_id)),
1387 + AR8327_PORT_LOOKUP_MEMBER, BIT(6));
1388 +
1389 + /* We want the switch to be pass-through and act like a PHY on
1390 + * these ports. So BC/MC/UC & IGMP frames need to be accepted
1391 + */
1392 + ctrl = BIT(phy_to_port(phy_id)) | BIT(6);
1393 + ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL1,
1394 + ctrl << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
1395 + ctrl << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
1396 + ctrl << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
1397 + ctrl << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
1398 + }
1399 +
1400 + return 0;
1401 +}
1402 +
1403 static int ar8xxx_setup(struct dsa_switch *ds)
1404 {
1405 struct ar8xxx_priv *priv = ds_to_priv(ds);
1406 @@ -341,6 +387,10 @@ static int ar8xxx_setup(struct dsa_switch *ds)
1407 }
1408 }
1409
1410 + ret = ar8xxx_of_setup(ds);
1411 + if (ret < 0)
1412 + return ret;
1413 +
1414 return 0;
1415 }
1416
1417
1418 From patchwork Fri May 29 01:42:22 2015
1419 Content-Type: text/plain; charset="utf-8"
1420 MIME-Version: 1.0
1421 Content-Transfer-Encoding: 7bit
1422 Subject: [7/7] Documentation: devicetree: add ar8xxx binding
1423 From: Mathieu Olivari <mathieu@codeaurora.org>
1424 X-Patchwork-Id: 477528
1425 X-Patchwork-Delegate: davem@davemloft.net
1426 Message-Id: <1432863742-18427-8-git-send-email-mathieu@codeaurora.org>
1427 To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
1428 ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
1429 davem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,
1430 f.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,
1431 jiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,
1432 alexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,
1433 joe@perches.com, sfeldma@gmail.com, nbd@nbd.name, juhosg@openwrt.org
1434 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
1435 netdev@vger.kernel.org
1436 Date: Thu, 28 May 2015 18:42:22 -0700
1437
1438 Add device-tree binding for ar8xxx switch families.
1439
1440 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
1441 ---
1442 .../devicetree/bindings/net/dsa/qca-ar8xxx.txt | 70 ++++++++++++++++++++++
1443 1 file changed, 70 insertions(+)
1444 create mode 100644 Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt
1445
1446 diff --git a/Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt b/Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt
1447 new file mode 100644
1448 index 0000000..f4fd3f1
1449 --- /dev/null
1450 +++ b/Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt
1451 @@ -0,0 +1,70 @@
1452 +* Qualcomm Atheros AR8xxx switch family
1453 +
1454 +Required properties:
1455 +
1456 +- compatible: should be "qca,ar8xxx"
1457 +- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
1458 +- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt
1459 +- #size-cells: must be 0
1460 +- #address-cells: must be 2, see dsa/dsa.txt
1461 +
1462 +Subnodes:
1463 +
1464 +The integrated switch subnode should be specified according to the binding
1465 +described in dsa/dsa.txt.
1466 +
1467 +Optional properties:
1468 +
1469 +- qca,port6-phy-mode: if specified, the driver will configure Port 6 in the
1470 + given phy-mode. See Documentation/devicetree/bindings/net/ethernet.txt for
1471 + the list of valid phy-mode.
1472 +
1473 +- qca,port6-phy-id: if specified, the driver will connect Port 6 to the PHY
1474 + given as a parameter. In this case, Port6 and the corresponding PHY will be
1475 + isolated from the rest of the switch. From a system perspective, they will
1476 + act as a regular PHY.
1477 +
1478 +Example:
1479 +
1480 + dsa@0 {
1481 + compatible = "qca,ar8xxx";
1482 + #address-cells = <2>;
1483 + #size-cells = <0>;
1484 +
1485 + dsa,ethernet = <&ethernet0>;
1486 + dsa,mii-bus = <&mii_bus0>;
1487 +
1488 + switch@0 {
1489 + #address-cells = <1>;
1490 + #size-cells = <0>;
1491 + reg = <0 0>; /* MDIO address 0, switch 0 in tree */
1492 +
1493 + qca,port6-phy-mode = "sgmii";
1494 + qca,port6-phy-id = <4>;
1495 +
1496 + port@0 {
1497 + reg = <11>;
1498 + label = "cpu";
1499 + };
1500 +
1501 + port@1 {
1502 + reg = <0>;
1503 + label = "lan1";
1504 + };
1505 +
1506 + port@2 {
1507 + reg = <1>;
1508 + label = "lan2";
1509 + };
1510 +
1511 + port@3 {
1512 + reg = <2>;
1513 + label = "lan3";
1514 + };
1515 +
1516 + port@4 {
1517 + reg = <3>;
1518 + label = "lan4";
1519 + };
1520 + };
1521 + };
OpenWrt Source Repository