target/linux/ipq806x/patches-4.9/0012-spi-qup-refactor-spi_qup_io_config-in-two-functions.patch

   1 From ef00ad56d728618203358d9eba7ca8e7eb48e701 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Tue, 26 Apr 2016 12:57:46 -0500
   4 Subject: [PATCH 12/37] spi: qup: refactor spi_qup_io_config in two functions
   5
   6 This is preparation for handling transactions larger than 64K-1 bytes in
   7 block mode which is currently unsupported quietly fails.
   8
   9 We need to break these into two functions 1) prep is called once per
  10 spi_message and 2) io_config is calle once per spi-qup bus transaction
  11
  12 This is just refactoring, there should be no functional change
  13
  14 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  15 ---
  16  drivers/spi/spi-qup.c |  141 ++++++++++++++++++++++++++++++-------------------
  17  1 file changed, 86 insertions(+), 55 deletions(-)
  18
  19 --- a/drivers/spi/spi-qup.c
  20 +++ b/drivers/spi/spi-qup.c
  21 @@ -585,12 +585,11 @@ static irqreturn_t spi_qup_qup_irq(int i
  22         return IRQ_HANDLED;
  23  }
  24
  25 -/* set clock freq ... bits per word */
  26 -static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  27 +/* set clock freq ... bits per word, determine mode */
  28 +static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
  29  {
  30         struct spi_qup *controller = spi_master_get_devdata(spi->master);
  31 -       u32 config, iomode, control;
  32 -       int ret, n_words;
  33 +       int ret;
  34
  35         if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
  36                 dev_err(controller->dev, "too big size for loopback %d > %d\n",
  37 @@ -605,56 +604,94 @@ static int spi_qup_io_config(struct spi_
  38                 return -EIO;
  39         }
  40
  41 -       if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
  42 -               dev_err(controller->dev, "cannot set RESET state\n");
  43 -               return -EIO;
  44 -       }
  45 -
  46         controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
  47         controller->n_words = xfer->len / controller->w_size;
  48 -       n_words = controller->n_words;
  49
  50 -       if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
  51 +       if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
  52                 controller->mode = QUP_IO_M_MODE_FIFO;
  53 -               writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
  54 -               writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
  55 -               /* must be zero for FIFO */
  56 -               writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
  57 -               writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
  58 -       } else if (spi->master->can_dma &&
  59 -           spi->master->can_dma(spi->master, spi, xfer) &&
  60 -           spi->master->cur_msg_mapped) {
  61 +       else if (spi->master->can_dma &&
  62 +                spi->master->can_dma(spi->master, spi, xfer) &&
  63 +                spi->master->cur_msg_mapped)
  64                 controller->mode = QUP_IO_M_MODE_BAM;
  65 -               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
  66 -               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
  67 -               /* must be zero for BLOCK and BAM */
  68 -               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
  69 -               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
  70 +       else
  71 +               controller->mode = QUP_IO_M_MODE_BLOCK;
  72
  73 -               if (!controller->qup_v1) {
  74 -                       void __iomem *input_cnt;
  75 +       return 0;
  76 +}
  77
  78 -                       input_cnt = controller->base + QUP_MX_INPUT_CNT;
  79 -                       /*
  80 -                        * for DMA transfers, both QUP_MX_INPUT_CNT and
  81 -                        * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
  82 -                        * That case is a non-balanced transfer when there is
  83 -                        * only a rx_buf.
  84 -                        */
  85 -                       if (xfer->tx_buf)
  86 -                               writel_relaxed(0, input_cnt);
  87 -                       else
  88 -                               writel_relaxed(n_words, input_cnt);
  89 +/* prep qup for another spi transaction of specific type */
  90 +static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  91 +{
  92 +       struct spi_qup *controller = spi_master_get_devdata(spi->master);
  93 +       u32 config, iomode, control;
  94 +       unsigned long flags;
  95
  96 +       reinit_completion(&controller->done);
  97 +       reinit_completion(&controller->dma_tx_done);
  98 +
  99 +       spin_lock_irqsave(&controller->lock, flags);
 100 +       controller->xfer     = xfer;
 101 +       controller->error    = 0;
 102 +       controller->rx_bytes = 0;
 103 +       controller->tx_bytes = 0;
 104 +       spin_unlock_irqrestore(&controller->lock, flags);
 105 +
 106 +
 107 +       if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
 108 +               dev_err(controller->dev, "cannot set RESET state\n");
 109 +               return -EIO;
 110 +       }
 111 +
 112 +       switch (controller->mode) {
 113 +               case QUP_IO_M_MODE_FIFO:
 114 +                       writel_relaxed(controller->n_words,
 115 +                                      controller->base + QUP_MX_READ_CNT);
 116 +                       writel_relaxed(controller->n_words,
 117 +                                      controller->base + QUP_MX_WRITE_CNT);
 118 +                       /* must be zero for FIFO */
 119 +                       writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 120                         writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 121 -               }
 122 -       } else {
 123 -               controller->mode = QUP_IO_M_MODE_BLOCK;
 124 -               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 125 -               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 126 -               /* must be zero for BLOCK and BAM */
 127 -               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 128 -               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 129 +                       break;
 130 +               case QUP_IO_M_MODE_BAM:
 131 +                       writel_relaxed(controller->n_words,
 132 +                                      controller->base + QUP_MX_INPUT_CNT);
 133 +                       writel_relaxed(controller->n_words,
 134 +                                      controller->base + QUP_MX_OUTPUT_CNT);
 135 +                       /* must be zero for BLOCK and BAM */
 136 +                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 137 +                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 138 +                       if (!controller->qup_v1) {
 139 +                               void __iomem *input_cnt;
 140 +
 141 +                               input_cnt = controller->base + QUP_MX_INPUT_CNT;
 142 +                               /*
 143 +                                * for DMA transfers, both QUP_MX_INPUT_CNT and
 144 +                                * QUP_MX_OUTPUT_CNT must be zero to all cases
 145 +                                * but one. That case is a non-balanced
 146 +                                * transfer when there is only a rx_buf.
 147 +                                */
 148 +                               if (xfer->tx_buf)
 149 +                                       writel_relaxed(0, input_cnt);
 150 +                               else
 151 +                                       writel_relaxed(controller->n_words,
 152 +                                                      input_cnt);
 153 +
 154 +                               writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 155 +                       }
 156 +                       break;
 157 +               case QUP_IO_M_MODE_BLOCK:
 158 +                       writel_relaxed(controller->n_words,
 159 +                                      controller->base + QUP_MX_INPUT_CNT);
 160 +                       writel_relaxed(controller->n_words,
 161 +                                      controller->base + QUP_MX_OUTPUT_CNT);
 162 +                       /* must be zero for BLOCK and BAM */
 163 +                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 164 +                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 165 +                       break;
 166 +               default:
 167 +                       dev_err(controller->dev, "unknown mode = %d\n",
 168 +                                       controller->mode);
 169 +                       return -EIO;
 170         }
 171
 172         iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 173 @@ -743,6 +780,10 @@ static int spi_qup_transfer_one(struct s
 174         unsigned long timeout, flags;
 175         int ret = -EIO;
 176
 177 +       ret = spi_qup_io_prep(spi, xfer);
 178 +       if (ret)
 179 +               return ret;
 180 +
 181         ret = spi_qup_io_config(spi, xfer);
 182         if (ret)
 183                 return ret;
 184 @@ -751,16 +792,6 @@ static int spi_qup_transfer_one(struct s
 185         timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
 186         timeout = 100 * msecs_to_jiffies(timeout);
 187
 188 -       reinit_completion(&controller->done);
 189 -       reinit_completion(&controller->dma_tx_done);
 190 -
 191 -       spin_lock_irqsave(&controller->lock, flags);
 192 -       controller->xfer     = xfer;
 193 -       controller->error    = 0;
 194 -       controller->rx_bytes = 0;
 195 -       controller->tx_bytes = 0;
 196 -       spin_unlock_irqrestore(&controller->lock, flags);
 197 -
 198         if (spi_qup_is_dma_xfer(controller->mode))
 199                 ret = spi_qup_do_dma(master, xfer, timeout);
 200         else