ipq806x: refresh patches
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 0014-spi-qup-allow-block-mode-to-generate-multiple-transa.patch
1 From 05a08cc5620df0fcf8e260feee04b9671705723e Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Tue, 26 Apr 2016 15:46:24 -0500
4 Subject: [PATCH 14/37] spi: qup: allow block mode to generate multiple
5 transactions
6
7 This let's you write more to the SPI bus than 64K-1 which is important
8 if the block size of a SPI device is >= 64K or some other device wants
9 to something larger.
10
11 This has the benefit of completly removing spi_message from the spi-qup
12 transactions
13
14 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
15 ---
16 drivers/spi/spi-qup.c | 120 ++++++++++++++++++++++++++++++-------------------
17 1 file changed, 75 insertions(+), 45 deletions(-)
18
19 --- a/drivers/spi/spi-qup.c
20 +++ b/drivers/spi/spi-qup.c
21 @@ -120,7 +120,7 @@
22
23 #define SPI_NUM_CHIPSELECTS 4
24
25 -#define SPI_MAX_DMA_XFER (SZ_64K - 64)
26 +#define SPI_MAX_XFER (SZ_64K - 64)
27
28 /* high speed mode is when bus rate is greater then 26MHz */
29 #define SPI_HS_MIN_RATE 26000000
30 @@ -150,6 +150,8 @@ struct spi_qup {
31 int n_words;
32 int tx_bytes;
33 int rx_bytes;
34 + const u8 *tx_buf;
35 + u8 *rx_buf;
36 int qup_v1;
37
38 int mode;
39 @@ -172,6 +174,12 @@ static inline bool spi_qup_is_dma_xfer(i
40 return false;
41 }
42
43 +/* get's the transaction size length */
44 +static inline unsigned spi_qup_len(struct spi_qup *controller)
45 +{
46 + return controller->n_words * controller->w_size;
47 +}
48 +
49 static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
50 {
51 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
52 @@ -224,10 +232,9 @@ static int spi_qup_set_state(struct spi_
53 return 0;
54 }
55
56 -static void spi_qup_read_from_fifo(struct spi_qup *controller,
57 - struct spi_transfer *xfer, u32 num_words)
58 +static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
59 {
60 - u8 *rx_buf = xfer->rx_buf;
61 + u8 *rx_buf = controller->rx_buf;
62 int i, shift, num_bytes;
63 u32 word;
64
65 @@ -235,7 +242,7 @@ static void spi_qup_read_from_fifo(struc
66
67 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
68
69 - num_bytes = min_t(int, xfer->len - controller->rx_bytes,
70 + num_bytes = min_t(int, spi_qup_len(controller) - controller->rx_bytes,
71 controller->w_size);
72
73 if (!rx_buf) {
74 @@ -257,13 +264,12 @@ static void spi_qup_read_from_fifo(struc
75 }
76 }
77
78 -static void spi_qup_read(struct spi_qup *controller,
79 - struct spi_transfer *xfer)
80 +static void spi_qup_read(struct spi_qup *controller)
81 {
82 u32 remainder, words_per_block, num_words;
83 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
84
85 - remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes,
86 + remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
87 controller->w_size);
88 words_per_block = controller->in_blk_sz >> 2;
89
90 @@ -284,7 +290,7 @@ static void spi_qup_read(struct spi_qup
91 }
92
93 /* read up to the maximum transfer size available */
94 - spi_qup_read_from_fifo(controller, xfer, num_words);
95 + spi_qup_read_from_fifo(controller, num_words);
96
97 remainder -= num_words;
98
99 @@ -306,17 +312,16 @@ static void spi_qup_read(struct spi_qup
100
101 }
102
103 -static void spi_qup_write_to_fifo(struct spi_qup *controller,
104 - struct spi_transfer *xfer, u32 num_words)
105 +static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
106 {
107 - const u8 *tx_buf = xfer->tx_buf;
108 + const u8 *tx_buf = controller->tx_buf;
109 int i, num_bytes;
110 u32 word, data;
111
112 for (; num_words; num_words--) {
113 word = 0;
114
115 - num_bytes = min_t(int, xfer->len - controller->tx_bytes,
116 + num_bytes = min_t(int, spi_qup_len(controller) - controller->tx_bytes,
117 controller->w_size);
118 if (tx_buf)
119 for (i = 0; i < num_bytes; i++) {
120 @@ -337,13 +342,12 @@ static void spi_qup_dma_done(void *data)
121 complete(done);
122 }
123
124 -static void spi_qup_write(struct spi_qup *controller,
125 - struct spi_transfer *xfer)
126 +static void spi_qup_write(struct spi_qup *controller)
127 {
128 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
129 u32 remainder, words_per_block, num_words;
130
131 - remainder = DIV_ROUND_UP(xfer->len - controller->tx_bytes,
132 + remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
133 controller->w_size);
134 words_per_block = controller->out_blk_sz >> 2;
135
136 @@ -363,7 +367,7 @@ static void spi_qup_write(struct spi_qup
137 num_words = 1;
138 }
139
140 - spi_qup_write_to_fifo(controller, xfer, num_words);
141 + spi_qup_write_to_fifo(controller, num_words);
142
143 remainder -= num_words;
144
145 @@ -629,35 +633,61 @@ static int spi_qup_do_pio(struct spi_dev
146 {
147 struct spi_master *master = spi->master;
148 struct spi_qup *qup = spi_master_get_devdata(master);
149 - int ret;
150 + int ret, n_words, iterations, offset = 0;
151
152 - ret = spi_qup_io_config(spi, xfer);
153 - if (ret)
154 - return ret;
155 + n_words = qup->n_words;
156 + iterations = n_words / SPI_MAX_XFER; /* round down */
157
158 - ret = spi_qup_set_state(qup, QUP_STATE_RUN);
159 - if (ret) {
160 - dev_warn(qup->dev, "cannot set RUN state\n");
161 - return ret;
162 - }
163 + qup->rx_buf = xfer->rx_buf;
164 + qup->tx_buf = xfer->tx_buf;
165
166 - ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
167 - if (ret) {
168 - dev_warn(qup->dev, "cannot set PAUSE state\n");
169 - return ret;
170 - }
171 + do {
172 + if (iterations)
173 + qup->n_words = SPI_MAX_XFER;
174 + else
175 + qup->n_words = n_words % SPI_MAX_XFER;
176
177 - if (qup->mode == QUP_IO_M_MODE_FIFO)
178 - spi_qup_write(qup, xfer);
179 + if (qup->tx_buf && offset)
180 + qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER;
181
182 - ret = spi_qup_set_state(qup, QUP_STATE_RUN);
183 - if (ret) {
184 - dev_warn(qup->dev, "cannot set RUN state\n");
185 - return ret;
186 - }
187 + if (qup->rx_buf && offset)
188 + qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER;
189
190 - if (!wait_for_completion_timeout(&qup->done, timeout))
191 - return -ETIMEDOUT;
192 + /* if the transaction is small enough, we need
193 + * to fallback to FIFO mode */
194 + if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
195 + qup->mode = QUP_IO_M_MODE_FIFO;
196 +
197 + ret = spi_qup_io_config(spi, xfer);
198 + if (ret)
199 + return ret;
200 +
201 + ret = spi_qup_set_state(qup, QUP_STATE_RUN);
202 + if (ret) {
203 + dev_warn(qup->dev, "cannot set RUN state\n");
204 + return ret;
205 + }
206 +
207 + ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
208 + if (ret) {
209 + dev_warn(qup->dev, "cannot set PAUSE state\n");
210 + return ret;
211 + }
212 +
213 + if (qup->mode == QUP_IO_M_MODE_FIFO)
214 + spi_qup_write(qup);
215 +
216 + ret = spi_qup_set_state(qup, QUP_STATE_RUN);
217 + if (ret) {
218 + dev_warn(qup->dev, "cannot set RUN state\n");
219 + return ret;
220 + }
221 +
222 + if (!wait_for_completion_timeout(&qup->done, timeout))
223 + return -ETIMEDOUT;
224 +
225 + offset++;
226 + } while (iterations--);
227
228 return 0;
229 }
230 @@ -722,17 +752,17 @@ static irqreturn_t spi_qup_qup_irq(int i
231 complete(&controller->dma_tx_done);
232 } else {
233 if (opflags & QUP_OP_IN_SERVICE_FLAG)
234 - spi_qup_read(controller, xfer);
235 + spi_qup_read(controller);
236
237 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
238 - spi_qup_write(controller, xfer);
239 + spi_qup_write(controller);
240 }
241
242 /* re-read opflags as flags may have changed due to actions above */
243 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
244 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
245
246 - if ((controller->rx_bytes == xfer->len &&
247 + if ((controller->rx_bytes == spi_qup_len(controller) &&
248 (opflags & QUP_OP_MAX_INPUT_DONE_FLAG)) || error)
249 done = true;
250
251 @@ -794,7 +824,7 @@ static int spi_qup_transfer_one(struct s
252 return ret;
253
254 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
255 - timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
256 + timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER, xfer->len) * 8, timeout);
257 timeout = 100 * msecs_to_jiffies(timeout);
258
259 if (spi_qup_is_dma_xfer(controller->mode))
260 @@ -983,7 +1013,7 @@ static int spi_qup_probe(struct platform
261 master->dev.of_node = pdev->dev.of_node;
262 master->auto_runtime_pm = true;
263 master->dma_alignment = dma_get_cache_alignment();
264 - master->max_dma_len = SPI_MAX_DMA_XFER;
265 + master->max_dma_len = SPI_MAX_XFER;
266
267 platform_set_drvdata(pdev, master);
268