32c52b07ed9decc17085840ba50f6cff2a8c59b9
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch
1 From ec3e465ecf3f7dd26f2e22170e4c5f4b9979df5d Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Mon, 21 Mar 2016 15:55:21 -0500
4 Subject: [PATCH 26/69] dts: ipq4019: Add support for IPQ4019 DK04 board
5
6 This is pretty similiar to a DK01 but has a bit more IO. Some notable
7 differences are listed below however they are not in the device tree yet
8 as we continue adding more support
9
10 - second serial port
11 - PCIe
12 - NAND
13 - SD/EMMC
14
15 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
16 ---
17 arch/arm/boot/dts/Makefile | 1 +
18 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 12 +-
19 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 21 +++
20 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 163 ++++++++++++++++++++++++
21 4 files changed, 189 insertions(+), 8 deletions(-)
22 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
23 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
24
25 --- a/arch/arm/boot/dts/Makefile
26 +++ b/arch/arm/boot/dts/Makefile
27 @@ -617,6 +617,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
28 qcom-apq8084-ifc6540.dtb \
29 qcom-apq8084-mtp.dtb \
30 qcom-ipq4019-ap.dk01.1-c1.dtb \
31 + qcom-ipq4019-ap.dk04.1-c1.dtb \
32 qcom-ipq8064-ap148.dtb \
33 qcom-msm8660-surf.dtb \
34 qcom-msm8960-cdp.dtb \
35 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
36 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
37 @@ -109,11 +109,7 @@
38 status = "ok";
39 };
40
41 - usb3_ss_phy: ssphy@0 {
42 - status = "ok";
43 - };
44 -
45 - dummy_ss_phy: ssphy@1 {
46 + usb3_ss_phy: ssphy@9a000 {
47 status = "ok";
48 };
49
50 @@ -121,15 +117,15 @@
51 status = "ok";
52 };
53
54 - usb2_hs_phy: hsphy@a8000 {
55 + usb3@0 {
56 status = "ok";
57 };
58
59 - usb3: usb3@8a00000 {
60 + usb2_hs_phy: hsphy@a8000 {
61 status = "ok";
62 };
63
64 - usb2: usb2@6000000 {
65 + usb2@0{
66 status = "ok";
67 };
68 };
69 --- /dev/null
70 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
71 @@ -0,0 +1,21 @@
72 +/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
73 + *
74 + * Permission to use, copy, modify, and/or distribute this software for any
75 + * purpose with or without fee is hereby granted, provided that the above
76 + * copyright notice and this permission notice appear in all copies.
77 + *
78 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
79 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
80 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
81 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
82 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
83 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
84 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
85 + *
86 + */
87 +
88 +#include "qcom-ipq4019-ap.dk04.1.dtsi"
89 +
90 +/ {
91 + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
92 +};
93 --- /dev/null
94 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
95 @@ -0,0 +1,163 @@
96 +/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
97 + *
98 + * Permission to use, copy, modify, and/or distribute this software for any
99 + * purpose with or without fee is hereby granted, provided that the above
100 + * copyright notice and this permission notice appear in all copies.
101 + *
102 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
103 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
104 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
105 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
106 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
107 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
108 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
109 + *
110 + */
111 +
112 +#include "qcom-ipq4019.dtsi"
113 +
114 +/ {
115 + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
116 + compatible = "qcom,ipq4019";
117 +
118 + clocks {
119 + xo: xo {
120 + compatible = "fixed-clock";
121 + clock-frequency = <48000000>;
122 + #clock-cells = <0>;
123 + };
124 + };
125 +
126 + soc {
127 + timer {
128 + compatible = "arm,armv7-timer";
129 + interrupts = <1 2 0xf08>,
130 + <1 3 0xf08>,
131 + <1 4 0xf08>,
132 + <1 1 0xf08>;
133 + clock-frequency = <48000000>;
134 + };
135 +
136 + pinctrl@0x01000000 {
137 + serial_0_pins: serial_pinmux {
138 + mux {
139 + pins = "gpio16", "gpio17";
140 + function = "blsp_uart0";
141 + bias-disable;
142 + };
143 + };
144 +
145 + serial_1_pins: serial1_pinmux {
146 + mux {
147 + pins = "gpio8", "gpio9";
148 + function = "blsp_uart1";
149 + bias-disable;
150 + };
151 + };
152 +
153 + spi_0_pins: spi_0_pinmux {
154 + pinmux {
155 + function = "blsp_spi0";
156 + pins = "gpio13", "gpio14", "gpio15";
157 + };
158 + pinmux_cs {
159 + function = "gpio";
160 + pins = "gpio12";
161 + };
162 + pinconf {
163 + pins = "gpio13", "gpio14", "gpio15";
164 + drive-strength = <12>;
165 + bias-disable;
166 + };
167 + pinconf_cs {
168 + pins = "gpio12";
169 + drive-strength = <2>;
170 + bias-disable;
171 + output-high;
172 + };
173 + };
174 +
175 + i2c_0_pins: i2c_0_pinmux {
176 + pinmux {
177 + function = "blsp_i2c0";
178 + pins = "gpio10", "gpio11";
179 + };
180 + pinconf {
181 + pins = "gpio10", "gpio11";
182 + drive-strength = <16>;
183 + bias-disable;
184 + };
185 + };
186 + };
187 +
188 + blsp_dma: dma@7884000 {
189 + status = "ok";
190 + };
191 +
192 + spi_0: spi@78b5000 {
193 + pinctrl-0 = <&spi_0_pins>;
194 + pinctrl-names = "default";
195 + status = "ok";
196 + cs-gpios = <&tlmm 12 0>;
197 +
198 + mx25l25635e@0 {
199 + #address-cells = <1>;
200 + #size-cells = <1>;
201 + reg = <0>;
202 + compatible = "mx25l25635e";
203 + spi-max-frequency = <24000000>;
204 + };
205 + };
206 +
207 + i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
208 + pinctrl-0 = <&i2c_0_pins>;
209 + pinctrl-names = "default";
210 +
211 + status = "ok";
212 + };
213 +
214 + serial@78af000 {
215 + pinctrl-0 = <&serial_0_pins>;
216 + pinctrl-names = "default";
217 + status = "ok";
218 + };
219 +
220 + serial@78b0000 {
221 + pinctrl-0 = <&serial_1_pins>;
222 + pinctrl-names = "default";
223 + status = "ok";
224 + };
225 +
226 + usb3_ss_phy: ssphy@9a000 {
227 + status = "ok";
228 + };
229 +
230 + usb3_hs_phy: hsphy@a6000 {
231 + status = "ok";
232 + };
233 +
234 + usb3: usb3@0 {
235 + status = "ok";
236 + };
237 +
238 + usb2_hs_phy: hsphy@a8000 {
239 + status = "ok";
240 + };
241 +
242 + usb2: usb2@6000000 {
243 + status = "ok";
244 + };
245 +
246 + cryptobam: dma@8e04000 {
247 + status = "ok";
248 + };
249 +
250 + crypto@8e3a000 {
251 + status = "ok";
252 + };
253 +
254 + watchdog@b017000 {
255 + status = "ok";
256 + };
257 + };
258 +};