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ipq806x: switch to linux 4.14
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 0028-clk-qcom-Add-support-for-RPM-Clocks.patch
1 From 21e7116c9d639f3283d4cec286fed1e703832b43 Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <georgi.djakov@linaro.org>
3 Date: Wed, 2 Nov 2016 17:56:57 +0200
4 Subject: [PATCH 28/69] clk: qcom: Add support for RPM Clocks
5
6 This adds initial support for clocks controlled by the Resource
7 Power Manager (RPM) processor on some Qualcomm SoCs, which use
8 the qcom_rpm driver to communicate with RPM.
9 Such platforms are apq8064 and msm8960.
10
11 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
12 Acked-by: Rob Herring <robh@kernel.org>
13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 ---
15 .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
16 drivers/clk/qcom/Kconfig | 13 +
17 drivers/clk/qcom/Makefile | 1 +
18 drivers/clk/qcom/clk-rpm.c | 489 +++++++++++++++++++++
19 include/dt-bindings/clock/qcom,rpmcc.h | 24 +
20 5 files changed, 528 insertions(+)
21 create mode 100644 drivers/clk/qcom/clk-rpm.c
22
23 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
24 +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
25 @@ -11,6 +11,7 @@ Required properties :
26 compatible "qcom,rpmcc" should be also included.
27
28 "qcom,rpmcc-msm8916", "qcom,rpmcc"
29 + "qcom,rpmcc-apq8064", "qcom,rpmcc"
30
31 - #clock-cells : shall contain 1
32
33 --- a/drivers/clk/qcom/Kconfig
34 +++ b/drivers/clk/qcom/Kconfig
35 @@ -12,6 +12,19 @@ config COMMON_CLK_QCOM
36 select REGMAP_MMIO
37 select RESET_CONTROLLER
38
39 +config QCOM_CLK_RPM
40 + tristate "RPM based Clock Controller"
41 + depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
42 + select QCOM_RPMCC
43 + help
44 + The RPM (Resource Power Manager) is a dedicated hardware engine for
45 + managing the shared SoC resources in order to keep the lowest power
46 + profile. It communicates with other hardware subsystems via shared
47 + memory and accepts clock requests, aggregates the requests and turns
48 + the clocks on/off or scales them on demand.
49 + Say Y if you want to support the clocks exposed by the RPM on
50 + platforms such as ipq806x, msm8660, msm8960 etc.
51 +
52 config QCOM_CLK_SMD_RPM
53 tristate "RPM over SMD based Clock Controller"
54 depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
55 --- a/drivers/clk/qcom/Makefile
56 +++ b/drivers/clk/qcom/Makefile
57 @@ -29,4 +29,5 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm896
58 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
59 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
60 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
61 +obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
62 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
63 --- /dev/null
64 +++ b/drivers/clk/qcom/clk-rpm.c
65 @@ -0,0 +1,489 @@
66 +/*
67 + * Copyright (c) 2016, Linaro Limited
68 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
69 + *
70 + * This software is licensed under the terms of the GNU General Public
71 + * License version 2, as published by the Free Software Foundation, and
72 + * may be copied, distributed, and modified under those terms.
73 + *
74 + * This program is distributed in the hope that it will be useful,
75 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
76 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
77 + * GNU General Public License for more details.
78 + */
79 +
80 +#include <linux/clk-provider.h>
81 +#include <linux/err.h>
82 +#include <linux/export.h>
83 +#include <linux/init.h>
84 +#include <linux/kernel.h>
85 +#include <linux/module.h>
86 +#include <linux/mutex.h>
87 +#include <linux/mfd/qcom_rpm.h>
88 +#include <linux/of.h>
89 +#include <linux/of_device.h>
90 +#include <linux/platform_device.h>
91 +
92 +#include <dt-bindings/mfd/qcom-rpm.h>
93 +#include <dt-bindings/clock/qcom,rpmcc.h>
94 +
95 +#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
96 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2
97 +
98 +#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
99 + static struct clk_rpm _platform##_##_active; \
100 + static struct clk_rpm _platform##_##_name = { \
101 + .rpm_clk_id = (r_id), \
102 + .peer = &_platform##_##_active, \
103 + .rate = INT_MAX, \
104 + .hw.init = &(struct clk_init_data){ \
105 + .ops = &clk_rpm_ops, \
106 + .name = #_name, \
107 + .parent_names = (const char *[]){ "pxo_board" }, \
108 + .num_parents = 1, \
109 + }, \
110 + }; \
111 + static struct clk_rpm _platform##_##_active = { \
112 + .rpm_clk_id = (r_id), \
113 + .peer = &_platform##_##_name, \
114 + .active_only = true, \
115 + .rate = INT_MAX, \
116 + .hw.init = &(struct clk_init_data){ \
117 + .ops = &clk_rpm_ops, \
118 + .name = #_active, \
119 + .parent_names = (const char *[]){ "pxo_board" }, \
120 + .num_parents = 1, \
121 + }, \
122 + }
123 +
124 +#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
125 + static struct clk_rpm _platform##_##_active; \
126 + static struct clk_rpm _platform##_##_name = { \
127 + .rpm_clk_id = (r_id), \
128 + .active_only = true, \
129 + .peer = &_platform##_##_active, \
130 + .rate = (r), \
131 + .branch = true, \
132 + .hw.init = &(struct clk_init_data){ \
133 + .ops = &clk_rpm_branch_ops, \
134 + .name = #_name, \
135 + .parent_names = (const char *[]){ "pxo_board" }, \
136 + .num_parents = 1, \
137 + }, \
138 + }; \
139 + static struct clk_rpm _platform##_##_active = { \
140 + .rpm_clk_id = (r_id), \
141 + .peer = &_platform##_##_name, \
142 + .rate = (r), \
143 + .branch = true, \
144 + .hw.init = &(struct clk_init_data){ \
145 + .ops = &clk_rpm_branch_ops, \
146 + .name = #_active, \
147 + .parent_names = (const char *[]){ "pxo_board" }, \
148 + .num_parents = 1, \
149 + }, \
150 + }
151 +
152 +#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
153 + static struct clk_rpm _platform##_##_active; \
154 + static struct clk_rpm _platform##_##_name = { \
155 + .rpm_clk_id = (r_id), \
156 + .peer = &_platform##_##_active, \
157 + .rate = (r), \
158 + .branch = true, \
159 + .hw.init = &(struct clk_init_data){ \
160 + .ops = &clk_rpm_branch_ops, \
161 + .name = #_name, \
162 + .parent_names = (const char *[]){ "cxo_board" }, \
163 + .num_parents = 1, \
164 + }, \
165 + }; \
166 + static struct clk_rpm _platform##_##_active = { \
167 + .rpm_clk_id = (r_id), \
168 + .active_only = true, \
169 + .peer = &_platform##_##_name, \
170 + .rate = (r), \
171 + .branch = true, \
172 + .hw.init = &(struct clk_init_data){ \
173 + .ops = &clk_rpm_branch_ops, \
174 + .name = #_active, \
175 + .parent_names = (const char *[]){ "cxo_board" }, \
176 + .num_parents = 1, \
177 + }, \
178 + }
179 +
180 +#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
181 +
182 +struct clk_rpm {
183 + const int rpm_clk_id;
184 + const bool active_only;
185 + unsigned long rate;
186 + bool enabled;
187 + bool branch;
188 + struct clk_rpm *peer;
189 + struct clk_hw hw;
190 + struct qcom_rpm *rpm;
191 +};
192 +
193 +struct rpm_cc {
194 + struct qcom_rpm *rpm;
195 + struct clk_hw_onecell_data data;
196 + struct clk_hw *hws[];
197 +};
198 +
199 +struct rpm_clk_desc {
200 + struct clk_rpm **clks;
201 + size_t num_clks;
202 +};
203 +
204 +static DEFINE_MUTEX(rpm_clk_lock);
205 +
206 +static int clk_rpm_handoff(struct clk_rpm *r)
207 +{
208 + int ret;
209 + u32 value = INT_MAX;
210 +
211 + ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
212 + r->rpm_clk_id, &value, 1);
213 + if (ret)
214 + return ret;
215 + ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
216 + r->rpm_clk_id, &value, 1);
217 + if (ret)
218 + return ret;
219 +
220 + return 0;
221 +}
222 +
223 +static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
224 +{
225 + u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
226 +
227 + return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
228 + r->rpm_clk_id, &value, 1);
229 +}
230 +
231 +static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
232 +{
233 + u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
234 +
235 + return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
236 + r->rpm_clk_id, &value, 1);
237 +}
238 +
239 +static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
240 + unsigned long *active, unsigned long *sleep)
241 +{
242 + *active = rate;
243 +
244 + /*
245 + * Active-only clocks don't care what the rate is during sleep. So,
246 + * they vote for zero.
247 + */
248 + if (r->active_only)
249 + *sleep = 0;
250 + else
251 + *sleep = *active;
252 +}
253 +
254 +static int clk_rpm_prepare(struct clk_hw *hw)
255 +{
256 + struct clk_rpm *r = to_clk_rpm(hw);
257 + struct clk_rpm *peer = r->peer;
258 + unsigned long this_rate = 0, this_sleep_rate = 0;
259 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
260 + unsigned long active_rate, sleep_rate;
261 + int ret = 0;
262 +
263 + mutex_lock(&rpm_clk_lock);
264 +
265 + /* Don't send requests to the RPM if the rate has not been set. */
266 + if (!r->rate)
267 + goto out;
268 +
269 + to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
270 +
271 + /* Take peer clock's rate into account only if it's enabled. */
272 + if (peer->enabled)
273 + to_active_sleep(peer, peer->rate,
274 + &peer_rate, &peer_sleep_rate);
275 +
276 + active_rate = max(this_rate, peer_rate);
277 +
278 + if (r->branch)
279 + active_rate = !!active_rate;
280 +
281 + ret = clk_rpm_set_rate_active(r, active_rate);
282 + if (ret)
283 + goto out;
284 +
285 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
286 + if (r->branch)
287 + sleep_rate = !!sleep_rate;
288 +
289 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
290 + if (ret)
291 + /* Undo the active set vote and restore it */
292 + ret = clk_rpm_set_rate_active(r, peer_rate);
293 +
294 +out:
295 + if (!ret)
296 + r->enabled = true;
297 +
298 + mutex_unlock(&rpm_clk_lock);
299 +
300 + return ret;
301 +}
302 +
303 +static void clk_rpm_unprepare(struct clk_hw *hw)
304 +{
305 + struct clk_rpm *r = to_clk_rpm(hw);
306 + struct clk_rpm *peer = r->peer;
307 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
308 + unsigned long active_rate, sleep_rate;
309 + int ret;
310 +
311 + mutex_lock(&rpm_clk_lock);
312 +
313 + if (!r->rate)
314 + goto out;
315 +
316 + /* Take peer clock's rate into account only if it's enabled. */
317 + if (peer->enabled)
318 + to_active_sleep(peer, peer->rate, &peer_rate,
319 + &peer_sleep_rate);
320 +
321 + active_rate = r->branch ? !!peer_rate : peer_rate;
322 + ret = clk_rpm_set_rate_active(r, active_rate);
323 + if (ret)
324 + goto out;
325 +
326 + sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
327 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
328 + if (ret)
329 + goto out;
330 +
331 + r->enabled = false;
332 +
333 +out:
334 + mutex_unlock(&rpm_clk_lock);
335 +}
336 +
337 +static int clk_rpm_set_rate(struct clk_hw *hw,
338 + unsigned long rate, unsigned long parent_rate)
339 +{
340 + struct clk_rpm *r = to_clk_rpm(hw);
341 + struct clk_rpm *peer = r->peer;
342 + unsigned long active_rate, sleep_rate;
343 + unsigned long this_rate = 0, this_sleep_rate = 0;
344 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
345 + int ret = 0;
346 +
347 + mutex_lock(&rpm_clk_lock);
348 +
349 + if (!r->enabled)
350 + goto out;
351 +
352 + to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
353 +
354 + /* Take peer clock's rate into account only if it's enabled. */
355 + if (peer->enabled)
356 + to_active_sleep(peer, peer->rate,
357 + &peer_rate, &peer_sleep_rate);
358 +
359 + active_rate = max(this_rate, peer_rate);
360 + ret = clk_rpm_set_rate_active(r, active_rate);
361 + if (ret)
362 + goto out;
363 +
364 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
365 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
366 + if (ret)
367 + goto out;
368 +
369 + r->rate = rate;
370 +
371 +out:
372 + mutex_unlock(&rpm_clk_lock);
373 +
374 + return ret;
375 +}
376 +
377 +static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
378 + unsigned long *parent_rate)
379 +{
380 + /*
381 + * RPM handles rate rounding and we don't have a way to
382 + * know what the rate will be, so just return whatever
383 + * rate is requested.
384 + */
385 + return rate;
386 +}
387 +
388 +static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
389 + unsigned long parent_rate)
390 +{
391 + struct clk_rpm *r = to_clk_rpm(hw);
392 +
393 + /*
394 + * RPM handles rate rounding and we don't have a way to
395 + * know what the rate will be, so just return whatever
396 + * rate was set.
397 + */
398 + return r->rate;
399 +}
400 +
401 +static const struct clk_ops clk_rpm_ops = {
402 + .prepare = clk_rpm_prepare,
403 + .unprepare = clk_rpm_unprepare,
404 + .set_rate = clk_rpm_set_rate,
405 + .round_rate = clk_rpm_round_rate,
406 + .recalc_rate = clk_rpm_recalc_rate,
407 +};
408 +
409 +static const struct clk_ops clk_rpm_branch_ops = {
410 + .prepare = clk_rpm_prepare,
411 + .unprepare = clk_rpm_unprepare,
412 + .round_rate = clk_rpm_round_rate,
413 + .recalc_rate = clk_rpm_recalc_rate,
414 +};
415 +
416 +/* apq8064 */
417 +DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
418 +DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
419 +DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
420 +DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
421 +DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
422 +DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
423 +DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
424 +DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
425 +DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
426 +
427 +static struct clk_rpm *apq8064_clks[] = {
428 + [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
429 + [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
430 + [RPM_CFPB_CLK] = &apq8064_cfpb_clk,
431 + [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
432 + [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
433 + [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
434 + [RPM_EBI1_CLK] = &apq8064_ebi1_clk,
435 + [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
436 + [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
437 + [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
438 + [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
439 + [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
440 + [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
441 + [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
442 + [RPM_SFPB_CLK] = &apq8064_sfpb_clk,
443 + [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
444 + [RPM_QDSS_CLK] = &apq8064_qdss_clk,
445 + [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
446 +};
447 +
448 +static const struct rpm_clk_desc rpm_clk_apq8064 = {
449 + .clks = apq8064_clks,
450 + .num_clks = ARRAY_SIZE(apq8064_clks),
451 +};
452 +
453 +static const struct of_device_id rpm_clk_match_table[] = {
454 + { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
455 + { }
456 +};
457 +MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
458 +
459 +static int rpm_clk_probe(struct platform_device *pdev)
460 +{
461 + struct clk_hw **hws;
462 + struct rpm_cc *rcc;
463 + struct clk_hw_onecell_data *data;
464 + int ret;
465 + size_t num_clks, i;
466 + struct qcom_rpm *rpm;
467 + struct clk_rpm **rpm_clks;
468 + const struct rpm_clk_desc *desc;
469 +
470 + rpm = dev_get_drvdata(pdev->dev.parent);
471 + if (!rpm) {
472 + dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
473 + return -ENODEV;
474 + }
475 +
476 + desc = of_device_get_match_data(&pdev->dev);
477 + if (!desc)
478 + return -EINVAL;
479 +
480 + rpm_clks = desc->clks;
481 + num_clks = desc->num_clks;
482 +
483 + rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
484 + GFP_KERNEL);
485 + if (!rcc)
486 + return -ENOMEM;
487 +
488 + hws = rcc->hws;
489 + data = &rcc->data;
490 + data->num = num_clks;
491 +
492 + for (i = 0; i < num_clks; i++) {
493 + if (!rpm_clks[i])
494 + continue;
495 +
496 + rpm_clks[i]->rpm = rpm;
497 +
498 + ret = clk_rpm_handoff(rpm_clks[i]);
499 + if (ret)
500 + goto err;
501 + }
502 +
503 + for (i = 0; i < num_clks; i++) {
504 + if (!rpm_clks[i]) {
505 + data->hws[i] = ERR_PTR(-ENOENT);
506 + continue;
507 + }
508 +
509 + ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
510 + if (ret)
511 + goto err;
512 + }
513 +
514 + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
515 + data);
516 + if (ret)
517 + goto err;
518 +
519 + return 0;
520 +err:
521 + dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
522 + return ret;
523 +}
524 +
525 +static int rpm_clk_remove(struct platform_device *pdev)
526 +{
527 + of_clk_del_provider(pdev->dev.of_node);
528 + return 0;
529 +}
530 +
531 +static struct platform_driver rpm_clk_driver = {
532 + .driver = {
533 + .name = "qcom-clk-rpm",
534 + .of_match_table = rpm_clk_match_table,
535 + },
536 + .probe = rpm_clk_probe,
537 + .remove = rpm_clk_remove,
538 +};
539 +
540 +static int __init rpm_clk_init(void)
541 +{
542 + return platform_driver_register(&rpm_clk_driver);
543 +}
544 +core_initcall(rpm_clk_init);
545 +
546 +static void __exit rpm_clk_exit(void)
547 +{
548 + platform_driver_unregister(&rpm_clk_driver);
549 +}
550 +module_exit(rpm_clk_exit);
551 +
552 +MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
553 +MODULE_LICENSE("GPL v2");
554 +MODULE_ALIAS("platform:qcom-clk-rpm");
555 --- a/include/dt-bindings/clock/qcom,rpmcc.h
556 +++ b/include/dt-bindings/clock/qcom,rpmcc.h
557 @@ -14,6 +14,30 @@
558 #ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
559 #define _DT_BINDINGS_CLK_MSM_RPMCC_H
560
561 +/* apq8064 */
562 +#define RPM_PXO_CLK 0
563 +#define RPM_PXO_A_CLK 1
564 +#define RPM_CXO_CLK 2
565 +#define RPM_CXO_A_CLK 3
566 +#define RPM_APPS_FABRIC_CLK 4
567 +#define RPM_APPS_FABRIC_A_CLK 5
568 +#define RPM_CFPB_CLK 6
569 +#define RPM_CFPB_A_CLK 7
570 +#define RPM_QDSS_CLK 8
571 +#define RPM_QDSS_A_CLK 9
572 +#define RPM_DAYTONA_FABRIC_CLK 10
573 +#define RPM_DAYTONA_FABRIC_A_CLK 11
574 +#define RPM_EBI1_CLK 12
575 +#define RPM_EBI1_A_CLK 13
576 +#define RPM_MM_FABRIC_CLK 14
577 +#define RPM_MM_FABRIC_A_CLK 15
578 +#define RPM_MMFPB_CLK 16
579 +#define RPM_MMFPB_A_CLK 17
580 +#define RPM_SYS_FABRIC_CLK 18
581 +#define RPM_SYS_FABRIC_A_CLK 19
582 +#define RPM_SFPB_CLK 20
583 +#define RPM_SFPB_A_CLK 21
584 +
585 /* msm8916 */
586 #define RPM_SMD_XO_CLK_SRC 0
587 #define RPM_SMD_XO_A_CLK_SRC 1
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