target/linux/ipq806x/patches-4.9/0032-phy-add-qcom-dwc3-phy.patch

   1 From b9004f4fd23e4c614d71c972f3a9311665480e29 Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Thu, 9 Mar 2017 08:19:18 +0100
   4 Subject: [PATCH 32/69] phy: add qcom dwc3 phy
   5
   6 Signed-off-by: Andy Gross <agross@codeaurora.org>
   7 ---
   8  drivers/phy/Kconfig         |  12 +
   9  drivers/phy/Makefile        |   1 +
  10  drivers/phy/phy-qcom-dwc3.c | 575 ++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 588 insertions(+)
  12  create mode 100644 drivers/phy/phy-qcom-dwc3.c
  13
  14 --- a/drivers/phy/Kconfig
  15 +++ b/drivers/phy/Kconfig
  16 @@ -490,4 +490,16 @@ config PHY_NS2_PCIE
  17         help
  18           Enable this to support the Broadcom Northstar2 PCIe PHY.
  19           If unsure, say N.
  20 +
  21 +config PHY_QCOM_DWC3
  22 +       tristate "QCOM DWC3 USB PHY support"
  23 +       depends on ARCH_QCOM
  24 +       depends on HAS_IOMEM
  25 +       depends on OF
  26 +       select GENERIC_PHY
  27 +       help
  28 +         This option enables support for the Synopsis PHYs present inside the
  29 +         Qualcomm USB3.0 DWC3 controller.  This driver supports both HS and SS
  30 +         PHY controllers.
  31 +
  32  endmenu
  33 --- a/drivers/phy/Makefile
  34 +++ b/drivers/phy/Makefile
  35 @@ -60,3 +60,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB)               += phy-
  36  obj-$(CONFIG_PHY_CYGNUS_PCIE)          += phy-bcm-cygnus-pcie.o
  37  obj-$(CONFIG_ARCH_TEGRA) += tegra/
  38  obj-$(CONFIG_PHY_NS2_PCIE)             += phy-bcm-ns2-pcie.o
  39 +obj-$(CONFIG_PHY_QCOM_DWC3)            += phy-qcom-dwc3.o
  40 --- /dev/null
  41 +++ b/drivers/phy/phy-qcom-dwc3.c
  42 @@ -0,0 +1,575 @@
  43 +/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
  44 + *
  45 + * This program is free software; you can redistribute it and/or modify
  46 + * it under the terms of the GNU General Public License version 2 and
  47 + * only version 2 as published by the Free Software Foundation.
  48 + *
  49 +* This program is distributed in the hope that it will be useful,
  50 +* but WITHOUT ANY WARRANTY; without even the implied warranty of
  51 +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  52 +* GNU General Public License for more details.
  53 +*/
  54 +
  55 +#include <linux/clk.h>
  56 +#include <linux/err.h>
  57 +#include <linux/io.h>
  58 +#include <linux/module.h>
  59 +#include <linux/of.h>
  60 +#include <linux/phy/phy.h>
  61 +#include <linux/platform_device.h>
  62 +#include <linux/delay.h>
  63 +
  64 +/**
  65 + *  USB QSCRATCH Hardware registers
  66 + */
  67 +#define QSCRATCH_GENERAL_CFG           (0x08)
  68 +#define HSUSB_PHY_CTRL_REG             (0x10)
  69 +
  70 +/* PHY_CTRL_REG */
  71 +#define HSUSB_CTRL_DMSEHV_CLAMP                        BIT(24)
  72 +#define HSUSB_CTRL_USB2_SUSPEND                        BIT(23)
  73 +#define HSUSB_CTRL_UTMI_CLK_EN                 BIT(21)
  74 +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID         BIT(20)
  75 +#define HSUSB_CTRL_USE_CLKCORE                 BIT(18)
  76 +#define HSUSB_CTRL_DPSEHV_CLAMP                        BIT(17)
  77 +#define HSUSB_CTRL_COMMONONN                   BIT(11)
  78 +#define HSUSB_CTRL_ID_HV_CLAMP                 BIT(9)
  79 +#define HSUSB_CTRL_OTGSESSVLD_CLAMP            BIT(8)
  80 +#define HSUSB_CTRL_CLAMP_EN                    BIT(7)
  81 +#define HSUSB_CTRL_RETENABLEN                  BIT(1)
  82 +#define HSUSB_CTRL_POR                         BIT(0)
  83 +
  84 +/* QSCRATCH_GENERAL_CFG */
  85 +#define HSUSB_GCFG_XHCI_REV            BIT(2)
  86 +
  87 +/**
  88 + *  USB QSCRATCH Hardware registers
  89 + */
  90 +#define SSUSB_PHY_CTRL_REG             (0x00)
  91 +#define SSUSB_PHY_PARAM_CTRL_1         (0x04)
  92 +#define SSUSB_PHY_PARAM_CTRL_2         (0x08)
  93 +#define CR_PROTOCOL_DATA_IN_REG                (0x0c)
  94 +#define CR_PROTOCOL_DATA_OUT_REG       (0x10)
  95 +#define CR_PROTOCOL_CAP_ADDR_REG       (0x14)
  96 +#define CR_PROTOCOL_CAP_DATA_REG       (0x18)
  97 +#define CR_PROTOCOL_READ_REG           (0x1c)
  98 +#define CR_PROTOCOL_WRITE_REG          (0x20)
  99 +
 100 +/* PHY_CTRL_REG */
 101 +#define SSUSB_CTRL_REF_USE_PAD         BIT(28)
 102 +#define SSUSB_CTRL_TEST_POWERDOWN      BIT(27)
 103 +#define SSUSB_CTRL_LANE0_PWR_PRESENT   BIT(24)
 104 +#define SSUSB_CTRL_SS_PHY_EN           BIT(8)
 105 +#define SSUSB_CTRL_SS_PHY_RESET                BIT(7)
 106 +
 107 +/* SSPHY control registers */
 108 +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
 109 +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane)        (0x1002 + 0x100 * lane)
 110 +
 111 +/* SSPHY SoC version specific values */
 112 +#define SSPHY_RX_EQ_VALUE              4       /* Override value for rx_eq */
 113 +#define SSPHY_TX_DEEMPH_3_5DB          23      /* Override value for transmit
 114 +                                                  preemphasis */
 115 +#define SSPHY_MPLL_VALUE               0       /* Override value for mpll */
 116 +
 117 +/* QSCRATCH PHY_PARAM_CTRL1 fields */
 118 +#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK     0x07f00000u
 119 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK     0x000fc000u
 120 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK   0x00003f00u
 121 +#define PHY_PARAM_CTRL1_LOS_BIAS_MASK          0x000000f8u
 122 +
 123 +#define PHY_PARAM_CTRL1_MASK                           \
 124 +               (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK |   \
 125 +                PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK |   \
 126 +                PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
 127 +                PHY_PARAM_CTRL1_LOS_BIAS_MASK)
 128 +
 129 +#define PHY_PARAM_CTRL1_TX_FULL_SWING(x)       \
 130 +               (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
 131 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x)       \
 132 +               (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
 133 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x)     \
 134 +               (((x) <<  8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
 135 +#define PHY_PARAM_CTRL1_LOS_BIAS(x)    \
 136 +               (((x) <<  3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
 137 +
 138 +/* RX OVRD IN HI bits */
 139 +#define RX_OVRD_IN_HI_RX_RESET_OVRD            BIT(13)
 140 +#define RX_OVRD_IN_HI_RX_RX_RESET              BIT(12)
 141 +#define RX_OVRD_IN_HI_RX_EQ_OVRD               BIT(11)
 142 +#define RX_OVRD_IN_HI_RX_EQ_MASK               0x0700
 143 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT              8
 144 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD            BIT(7)
 145 +#define RX_OVRD_IN_HI_RX_EQ_EN                 BIT(6)
 146 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD       BIT(5)
 147 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK       0x0018
 148 +#define RX_OVRD_IN_HI_RX_RATE_OVRD             BIT(2)
 149 +#define RX_OVRD_IN_HI_RX_RATE_MASK             0x0003
 150 +
 151 +/* TX OVRD DRV LO register bits */
 152 +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK  0x007F
 153 +#define TX_OVRD_DRV_LO_PREEMPH_MASK    0x3F80
 154 +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT   7
 155 +#define TX_OVRD_DRV_LO_EN              BIT(14)
 156 +
 157 +/* SS CAP register bits */
 158 +#define SS_CR_CAP_ADDR_REG             BIT(0)
 159 +#define SS_CR_CAP_DATA_REG             BIT(0)
 160 +#define SS_CR_READ_REG                 BIT(0)
 161 +#define SS_CR_WRITE_REG                        BIT(0)
 162 +
 163 +struct qcom_dwc3_usb_phy {
 164 +       void __iomem            *base;
 165 +       struct device           *dev;
 166 +       struct clk              *xo_clk;
 167 +       struct clk              *ref_clk;
 168 +       u32                     rx_eq;
 169 +       u32                     tx_deamp_3_5db;
 170 +       u32                     mpll;
 171 +};
 172 +
 173 +struct qcom_dwc3_phy_drvdata {
 174 +       struct phy_ops  ops;
 175 +       u32             clk_rate;
 176 +};
 177 +
 178 +/**
 179 + * Write register and read back masked value to confirm it is written
 180 + *
 181 + * @base - QCOM DWC3 PHY base virtual address.
 182 + * @offset - register offset.
 183 + * @mask - register bitmask specifying what should be updated
 184 + * @val - value to write.
 185 + */
 186 +static inline void qcom_dwc3_phy_write_readback(
 187 +       struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
 188 +       const u32 mask, u32 val)
 189 +{
 190 +       u32 write_val, tmp = readl(phy_dwc3->base + offset);
 191 +
 192 +       tmp &= ~mask;           /* retain other bits */
 193 +       write_val = tmp | val;
 194 +
 195 +       writel(write_val, phy_dwc3->base + offset);
 196 +
 197 +       /* Read back to see if val was written */
 198 +       tmp = readl(phy_dwc3->base + offset);
 199 +       tmp &= mask;            /* clear other bits */
 200 +
 201 +       if (tmp != val)
 202 +               dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
 203 +                       val, offset);
 204 +}
 205 +
 206 +static int wait_for_latch(void __iomem *addr)
 207 +{
 208 +       u32 retry = 10;
 209 +
 210 +       while (true) {
 211 +               if (!readl(addr))
 212 +                       break;
 213 +
 214 +               if (--retry == 0)
 215 +                       return -ETIMEDOUT;
 216 +
 217 +               usleep_range(10, 20);
 218 +       }
 219 +
 220 +       return 0;
 221 +}
 222 +
 223 +/**
 224 + * Write SSPHY register
 225 + *
 226 + * @base - QCOM DWC3 PHY base virtual address.
 227 + * @addr - SSPHY address to write.
 228 + * @val - value to write.
 229 + */
 230 +static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3,
 231 +                                       u32 addr, u32 val)
 232 +{
 233 +       int ret;
 234 +
 235 +       writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
 236 +       writel(SS_CR_CAP_ADDR_REG, phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 237 +
 238 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 239 +       if (ret)
 240 +               goto err_wait;
 241 +
 242 +       writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
 243 +       writel(SS_CR_CAP_DATA_REG, phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
 244 +
 245 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
 246 +       if (ret)
 247 +               goto err_wait;
 248 +
 249 +       writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
 250 +
 251 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
 252 +
 253 +err_wait:
 254 +       if (ret)
 255 +               dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
 256 +       return ret;
 257 +}
 258 +
 259 +/**
 260 + * Read SSPHY register.
 261 + *
 262 + * @base - QCOM DWC3 PHY base virtual address.
 263 + * @addr - SSPHY address to read.
 264 + */
 265 +static int qcom_dwc3_ss_read_phycreg(void __iomem *base, u32 addr, u32 *val)
 266 +{
 267 +       int ret;
 268 +
 269 +       writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
 270 +       writel(SS_CR_CAP_ADDR_REG, base + CR_PROTOCOL_CAP_ADDR_REG);
 271 +
 272 +       ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG);
 273 +       if (ret)
 274 +               goto err_wait;
 275 +
 276 +       /*
 277 +        * Due to hardware bug, first read of SSPHY register might be
 278 +        * incorrect. Hence as workaround, SW should perform SSPHY register
 279 +        * read twice, but use only second read and ignore first read.
 280 +        */
 281 +       writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
 282 +
 283 +       ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
 284 +       if (ret)
 285 +               goto err_wait;
 286 +
 287 +       /* throwaway read */
 288 +       readl(base + CR_PROTOCOL_DATA_OUT_REG);
 289 +
 290 +       writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
 291 +
 292 +       ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
 293 +       if (ret)
 294 +               goto err_wait;
 295 +
 296 +       *val = readl(base + CR_PROTOCOL_DATA_OUT_REG);
 297 +
 298 +err_wait:
 299 +       return ret;
 300 +}
 301 +
 302 +static int qcom_dwc3_hs_phy_init(struct phy *phy)
 303 +{
 304 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 305 +       int ret;
 306 +       u32 val;
 307 +
 308 +       ret = clk_prepare_enable(phy_dwc3->xo_clk);
 309 +       if (ret)
 310 +               return ret;
 311 +
 312 +       ret = clk_prepare_enable(phy_dwc3->ref_clk);
 313 +       if (ret) {
 314 +               clk_disable_unprepare(phy_dwc3->xo_clk);
 315 +               return ret;
 316 +       }
 317 +
 318 +       /*
 319 +        * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
 320 +        * enable clamping, and disable RETENTION (power-on default is ENABLED)
 321 +        */
 322 +       val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
 323 +               HSUSB_CTRL_RETENABLEN  | HSUSB_CTRL_COMMONONN |
 324 +               HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
 325 +               HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
 326 +               HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
 327 +
 328 +       /* use core clock if external reference is not present */
 329 +       if (!phy_dwc3->xo_clk)
 330 +               val |= HSUSB_CTRL_USE_CLKCORE;
 331 +
 332 +       writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
 333 +       usleep_range(2000, 2200);
 334 +
 335 +       /* Disable (bypass) VBUS and ID filters */
 336 +       writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
 337 +
 338 +       return 0;
 339 +}
 340 +
 341 +static int qcom_dwc3_hs_phy_exit(struct phy *phy)
 342 +{
 343 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 344 +
 345 +       clk_disable_unprepare(phy_dwc3->ref_clk);
 346 +       clk_disable_unprepare(phy_dwc3->xo_clk);
 347 +
 348 +       return 0;
 349 +}
 350 +
 351 +static int qcom_dwc3_ss_phy_init(struct phy *phy)
 352 +{
 353 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 354 +       int ret;
 355 +       u32 data = 0;
 356 +
 357 +       ret = clk_prepare_enable(phy_dwc3->xo_clk);
 358 +       if (ret)
 359 +               return ret;
 360 +
 361 +       ret = clk_prepare_enable(phy_dwc3->ref_clk);
 362 +       if (ret) {
 363 +               clk_disable_unprepare(phy_dwc3->xo_clk);
 364 +               return ret;
 365 +       }
 366 +
 367 +       /* reset phy */
 368 +       data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 369 +       writel(data | SSUSB_CTRL_SS_PHY_RESET,
 370 +               phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 371 +       usleep_range(2000, 2200);
 372 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 373 +
 374 +       /* clear REF_PAD if we don't have XO clk */
 375 +       if (!phy_dwc3->xo_clk)
 376 +               data &= ~SSUSB_CTRL_REF_USE_PAD;
 377 +       else
 378 +               data |= SSUSB_CTRL_REF_USE_PAD;
 379 +
 380 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 381 +
 382 +       /* wait for ref clk to become stable, this can take up to 30ms */
 383 +       msleep(30);
 384 +
 385 +       data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
 386 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 387 +
 388 +       /*
 389 +        * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
 390 +        * in HS mode instead of SS mode. Workaround it by asserting
 391 +        * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
 392 +        */
 393 +       ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data);
 394 +       if (ret)
 395 +               goto err_phy_trans;
 396 +
 397 +       data |= (1 << 7);
 398 +       ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data);
 399 +       if (ret)
 400 +               goto err_phy_trans;
 401 +
 402 +       ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data);
 403 +       if (ret)
 404 +               goto err_phy_trans;
 405 +
 406 +       data &= ~0xff0;
 407 +       data |= 0x20;
 408 +       ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data);
 409 +       if (ret)
 410 +               goto err_phy_trans;
 411 +
 412 +       /*
 413 +        * Fix RX Equalization setting as follows
 414 +        * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
 415 +        * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
 416 +        * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
 417 +        * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
 418 +        */
 419 +       ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
 420 +                       SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
 421 +       if (ret)
 422 +               goto err_phy_trans;
 423 +
 424 +       data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
 425 +       data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
 426 +       data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
 427 +       data |= phy_dwc3->rx_eq << RX_OVRD_IN_HI_RX_EQ_SHIFT;
 428 +       data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
 429 +       ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
 430 +               SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
 431 +       if (ret)
 432 +               goto err_phy_trans;
 433 +
 434 +       /*
 435 +        * Set EQ and TX launch amplitudes as follows
 436 +        * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
 437 +        * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
 438 +        * LANE0.TX_OVRD_DRV_LO.EN set to 1.
 439 +        */
 440 +       ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
 441 +               SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
 442 +       if (ret)
 443 +               goto err_phy_trans;
 444 +
 445 +       data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
 446 +       data |= phy_dwc3->tx_deamp_3_5db << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
 447 +       data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
 448 +       data |= 0x6E;
 449 +       data |= TX_OVRD_DRV_LO_EN;
 450 +       ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
 451 +               SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
 452 +       if (ret)
 453 +               goto err_phy_trans;
 454 +
 455 +       qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x30, phy_dwc3->mpll);
 456 +
 457 +       /*
 458 +        * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
 459 +        * TX_FULL_SWING [26:20] amplitude to 110
 460 +        * TX_DEEMPH_6DB [19:14] to 32
 461 +        * TX_DEEMPH_3_5DB [13:8] set based on SoC version
 462 +        * LOS_BIAS [7:3] to 9
 463 +        */
 464 +       data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
 465 +
 466 +       data &= ~PHY_PARAM_CTRL1_MASK;
 467 +
 468 +       data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
 469 +               PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
 470 +               PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
 471 +               PHY_PARAM_CTRL1_LOS_BIAS(0x9);
 472 +
 473 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
 474 +                                    PHY_PARAM_CTRL1_MASK, data);
 475 +
 476 +err_phy_trans:
 477 +       return ret;
 478 +}
 479 +
 480 +static int qcom_dwc3_ss_phy_exit(struct phy *phy)
 481 +{
 482 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 483 +
 484 +       /* Sequence to put SSPHY in low power state:
 485 +        * 1. Clear REF_PHY_EN in PHY_CTRL_REG
 486 +        * 2. Clear REF_USE_PAD in PHY_CTRL_REG
 487 +        * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
 488 +        */
 489 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 490 +               SSUSB_CTRL_SS_PHY_EN, 0x0);
 491 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 492 +               SSUSB_CTRL_REF_USE_PAD, 0x0);
 493 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 494 +               SSUSB_CTRL_TEST_POWERDOWN, 0x0);
 495 +
 496 +       clk_disable_unprepare(phy_dwc3->ref_clk);
 497 +       clk_disable_unprepare(phy_dwc3->xo_clk);
 498 +
 499 +       return 0;
 500 +}
 501 +
 502 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
 503 +       .ops = {
 504 +               .init           = qcom_dwc3_hs_phy_init,
 505 +               .exit           = qcom_dwc3_hs_phy_exit,
 506 +               .owner          = THIS_MODULE,
 507 +       },
 508 +       .clk_rate = 60000000,
 509 +};
 510 +
 511 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = {
 512 +       .ops = {
 513 +               .init           = qcom_dwc3_ss_phy_init,
 514 +               .exit           = qcom_dwc3_ss_phy_exit,
 515 +               .owner          = THIS_MODULE,
 516 +       },
 517 +       .clk_rate = 125000000,
 518 +};
 519 +
 520 +static const struct of_device_id qcom_dwc3_phy_table[] = {
 521 +       { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata },
 522 +       { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata },
 523 +       { /* Sentinel */ }
 524 +};
 525 +MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
 526 +
 527 +static int qcom_dwc3_phy_probe(struct platform_device *pdev)
 528 +{
 529 +       struct qcom_dwc3_usb_phy        *phy_dwc3;
 530 +       struct phy_provider             *phy_provider;
 531 +       struct phy                      *generic_phy;
 532 +       struct resource                 *res;
 533 +       const struct of_device_id *match;
 534 +       const struct qcom_dwc3_phy_drvdata *data;
 535 +       struct device_node *np;
 536 +
 537 +       phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
 538 +       if (!phy_dwc3)
 539 +               return -ENOMEM;
 540 +
 541 +       match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node);
 542 +       data = match->data;
 543 +
 544 +       phy_dwc3->dev = &pdev->dev;
 545 +
 546 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 547 +       phy_dwc3->base = devm_ioremap_resource(phy_dwc3->dev, res);
 548 +       if (IS_ERR(phy_dwc3->base))
 549 +               return PTR_ERR(phy_dwc3->base);
 550 +
 551 +       phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
 552 +       if (IS_ERR(phy_dwc3->ref_clk)) {
 553 +               dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
 554 +               return PTR_ERR(phy_dwc3->ref_clk);
 555 +       }
 556 +
 557 +       clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
 558 +
 559 +       phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
 560 +       if (IS_ERR(phy_dwc3->xo_clk)) {
 561 +               dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
 562 +               phy_dwc3->xo_clk = NULL;
 563 +       }
 564 +
 565 +       /* Parse device node to probe HSIO settings */
 566 +       np = of_node_get(pdev->dev.of_node);
 567 +       if (!of_compat_cmp(match->compatible, "qcom,dwc3-ss-usb-phy",
 568 +                          strlen(match->compatible))) {
 569 +
 570 +               if (of_property_read_u32(np, "rx_eq", &phy_dwc3->rx_eq) ||
 571 +                   of_property_read_u32(np, "tx_deamp_3_5db",
 572 +                                        &phy_dwc3->tx_deamp_3_5db) ||
 573 +                   of_property_read_u32(np, "mpll", &phy_dwc3->mpll)) {
 574 +
 575 +                       dev_err(phy_dwc3->dev, "cannot get HSIO settings from device node, using default values\n");
 576 +
 577 +                       /* Default HSIO settings */
 578 +                       phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
 579 +                       phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
 580 +                       phy_dwc3->mpll = SSPHY_MPLL_VALUE;
 581 +               }
 582 +       }
 583 +
 584 +       generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node,
 585 +                                     &data->ops);
 586 +
 587 +       if (IS_ERR(generic_phy))
 588 +               return PTR_ERR(generic_phy);
 589 +
 590 +       phy_set_drvdata(generic_phy, phy_dwc3);
 591 +       platform_set_drvdata(pdev, phy_dwc3);
 592 +
 593 +       phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
 594 +                       of_phy_simple_xlate);
 595 +
 596 +       if (IS_ERR(phy_provider))
 597 +               return PTR_ERR(phy_provider);
 598 +
 599 +       return 0;
 600 +}
 601 +
 602 +static struct platform_driver qcom_dwc3_phy_driver = {
 603 +       .probe          = qcom_dwc3_phy_probe,
 604 +       .driver         = {
 605 +               .name   = "qcom-dwc3-usb-phy",
 606 +               .owner  = THIS_MODULE,
 607 +               .of_match_table = qcom_dwc3_phy_table,
 608 +       },
 609 +};
 610 +
 611 +module_platform_driver(qcom_dwc3_phy_driver);
 612 +
 613 +MODULE_ALIAS("platform:phy-qcom-dwc3");
 614 +MODULE_LICENSE("GPL v2");
 615 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 616 +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
 617 +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");