target/linux/ipq806x/patches-4.9/0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch

   1 From 88e1d6d9c113fe50810d1b03eb1fdbf015e5d1bd Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:22 -0700
   4 Subject: [PATCH 36/69] clk: Avoid sending high rates to downstream clocks
   5  during set_rate
   6
   7 If a clock is on and we call clk_set_rate() on it we may get into
   8 a situation where the clock temporarily increases in rate
   9 dramatically while we walk the tree and call .set_rate() ops. For
  10 example, consider a case where a PLL feeds into a divider.
  11 Initially the divider is set to divide by 1 and the PLL is
  12 running fairly slow (100MHz). The downstream consumer of the
  13 divider output can only handle rates =< 400 MHz, but the divider
  14 can only choose between divisors of 1 and 4.
  15
  16  +-----+   +----------------+
  17  | PLL |-->| div 1 or div 4 |---> consumer device
  18  +-----+   +----------------+
  19
  20 To achieve a rate of 400MHz on the output of the divider, we
  21 would have to set the rate of the PLL to 1.6 GHz and then divide
  22 it by 4. The current code would set the PLL to 1.6GHz first while
  23 the divider is still set to 1, thus causing the downstream
  24 consumer of the clock to receive a few clock cycles of 1.6GHz
  25 clock (far beyond it's maximum acceptable rate). We should be
  26 changing the divider first before increasing the PLL rate to
  27 avoid this problem.
  28
  29 Therefore, set the rate of any child clocks that are increasing
  30 in rate from their current rate so that they can increase their
  31 dividers if necessary. We assume that there isn't such a thing as
  32 minimum rate requirements.
  33
  34 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  35
  36 Conflicts:
  37         drivers/clk/clk.c
  38 ---
  39  drivers/clk/clk.c | 22 +++++++++++++++-------
  40  1 file changed, 15 insertions(+), 7 deletions(-)
  41
  42 --- a/drivers/clk/clk.c
  43 +++ b/drivers/clk/clk.c
  44 @@ -1466,12 +1466,12 @@ static struct clk_core *clk_propagate_ra
  45   * walk down a subtree and set the new rates notifying the rate
  46   * change on the way
  47   */
  48 -static void clk_change_rate(struct clk_core *core)
  49 +static void
  50 +clk_change_rate(struct clk_core *core, unsigned long best_parent_rate)
  51  {
  52         struct clk_core *child;
  53         struct hlist_node *tmp;
  54         unsigned long old_rate;
  55 -       unsigned long best_parent_rate = 0;
  56         bool skip_set_rate = false;
  57         struct clk_core *old_parent;
  58         struct clk_core *parent = NULL;
  59 @@ -1523,6 +1523,7 @@ static void clk_change_rate(struct clk_c
  60         trace_clk_set_rate_complete(core, core->new_rate);
  61
  62         core->rate = clk_recalc(core, best_parent_rate);
  63 +       core->rate = core->new_rate;
  64
  65         if (core->flags & CLK_SET_RATE_UNGATE) {
  66                 unsigned long flags;
  67 @@ -1550,12 +1551,13 @@ static void clk_change_rate(struct clk_c
  68                 /* Skip children who will be reparented to another clock */
  69                 if (child->new_parent && child->new_parent != core)
  70                         continue;
  71 -               clk_change_rate(child);
  72 +               if (child->new_rate != child->rate)
  73 +                       clk_change_rate(child, core->new_rate);
  74         }
  75
  76 -       /* handle the new child who might not be in core->children yet */
  77 -       if (core->new_child)
  78 -               clk_change_rate(core->new_child);
  79 +       /* handle the new child who might not be in clk->children yet */
  80 +       if (core->new_child && core->new_child->new_rate != core->new_child->rate)
  81 +               clk_change_rate(core->new_child, core->new_rate);
  82  }
  83
  84  static int clk_core_set_rate_nolock(struct clk_core *core,
  85 @@ -1563,6 +1565,7 @@ static int clk_core_set_rate_nolock(stru
  86  {
  87         struct clk_core *top, *fail_clk;
  88         unsigned long rate = req_rate;
  89 +       unsigned long parent_rate;
  90
  91         if (!core)
  92                 return 0;
  93 @@ -1588,8 +1591,13 @@ static int clk_core_set_rate_nolock(stru
  94                 return -EBUSY;
  95         }
  96
  97 +       if (top->parent)
  98 +               parent_rate = top->parent->rate;
  99 +       else
 100 +               parent_rate = 0;
 101 +
 102         /* change the rates */
 103 -       clk_change_rate(top);
 104 +       clk_change_rate(top, parent_rate);
 105
 106         core->req_rate = req_rate;
 107