target/linux/ipq806x/patches-4.9/0043-clk-qcom-Add-Krait-clock-controller-driver.patch

   1 From 7fb5976eb0231a06f484a6bde5e5fbfee7ee4f4a Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:30 -0700
   4 Subject: [PATCH 43/69] clk: qcom: Add Krait clock controller driver
   5
   6 The Krait CPU clocks are made up of a primary mux and secondary
   7 mux for each CPU and the L2, controlled via cp15 accessors. For
   8 Kraits within KPSSv1 each secondary mux accepts a different aux
   9 source, but on KPSSv2 each secondary mux accepts the same aux
  10 source.
  11
  12 Cc: <devicetree@vger.kernel.org>
  13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  14 ---
  15  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  22 ++
  16  drivers/clk/qcom/Kconfig                           |   8 +
  17  drivers/clk/qcom/Makefile                          |   1 +
  18  drivers/clk/qcom/krait-cc.c                        | 352 +++++++++++++++++++++
  19  4 files changed, 383 insertions(+)
  20  create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
  21  create mode 100644 drivers/clk/qcom/krait-cc.c
  22
  23 --- /dev/null
  24 +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
  25 @@ -0,0 +1,22 @@
  26 +Krait Clock Controller
  27 +
  28 +PROPERTIES
  29 +
  30 +- compatible:
  31 +       Usage: required
  32 +       Value type: <string>
  33 +       Definition: must be one of:
  34 +                       "qcom,krait-cc-v1"
  35 +                       "qcom,krait-cc-v2"
  36 +
  37 +- #clock-cells:
  38 +       Usage: required
  39 +       Value type: <u32>
  40 +       Definition: must be 1
  41 +
  42 +Example:
  43 +
  44 +       kraitcc: clock-controller {
  45 +               compatible = "qcom,krait-cc-v1";
  46 +               #clock-cells = <1>;
  47 +       };
  48 --- a/drivers/clk/qcom/Kconfig
  49 +++ b/drivers/clk/qcom/Kconfig
  50 @@ -196,6 +196,14 @@ config KPSS_XCC
  51           if you want to support CPU frequency scaling on devices such
  52           as MSM8960, APQ8064, etc.
  53
  54 +config KRAITCC
  55 +       tristate "Krait Clock Controller"
  56 +       depends on COMMON_CLK_QCOM && ARM
  57 +       select KRAIT_CLOCKS
  58 +       help
  59 +         Support for the Krait CPU clocks on Qualcomm devices.
  60 +         Say Y if you want to support CPU frequency scaling.
  61 +
  62  config KRAIT_CLOCKS
  63         bool
  64         select KRAIT_L2_ACCESSORS
  65 --- a/drivers/clk/qcom/Makefile
  66 +++ b/drivers/clk/qcom/Makefile
  67 @@ -35,3 +35,4 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
  68  obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
  69  obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
  70  obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  71 +obj-$(CONFIG_KRAITCC) += krait-cc.o
  72 --- /dev/null
  73 +++ b/drivers/clk/qcom/krait-cc.c
  74 @@ -0,0 +1,352 @@
  75 +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  76 + *
  77 + * This program is free software; you can redistribute it and/or modify
  78 + * it under the terms of the GNU General Public License version 2 and
  79 + * only version 2 as published by the Free Software Foundation.
  80 + *
  81 + * This program is distributed in the hope that it will be useful,
  82 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  83 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  84 + * GNU General Public License for more details.
  85 + */
  86 +
  87 +#include <linux/kernel.h>
  88 +#include <linux/init.h>
  89 +#include <linux/module.h>
  90 +#include <linux/platform_device.h>
  91 +#include <linux/err.h>
  92 +#include <linux/io.h>
  93 +#include <linux/of.h>
  94 +#include <linux/of_device.h>
  95 +#include <linux/clk.h>
  96 +#include <linux/clk-provider.h>
  97 +#include <linux/slab.h>
  98 +
  99 +#include "clk-krait.h"
 100 +
 101 +static unsigned int sec_mux_map[] = {
 102 +       2,
 103 +       0,
 104 +};
 105 +
 106 +static unsigned int pri_mux_map[] = {
 107 +       1,
 108 +       2,
 109 +       0,
 110 +};
 111 +
 112 +static int
 113 +krait_add_div(struct device *dev, int id, const char *s, unsigned offset)
 114 +{
 115 +       struct krait_div2_clk *div;
 116 +       struct clk_init_data init = {
 117 +               .num_parents = 1,
 118 +               .ops = &krait_div2_clk_ops,
 119 +               .flags = CLK_SET_RATE_PARENT,
 120 +       };
 121 +       const char *p_names[1];
 122 +       struct clk *clk;
 123 +
 124 +       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 125 +       if (!div)
 126 +               return -ENOMEM;
 127 +
 128 +       div->width = 2;
 129 +       div->shift = 6;
 130 +       div->lpl = id >= 0;
 131 +       div->offset = offset;
 132 +       div->hw.init = &init;
 133 +
 134 +       init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
 135 +       if (!init.name)
 136 +               return -ENOMEM;
 137 +
 138 +       init.parent_names = p_names;
 139 +       p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
 140 +       if (!p_names[0]) {
 141 +               kfree(init.name);
 142 +               return -ENOMEM;
 143 +       }
 144 +
 145 +       clk = devm_clk_register(dev, &div->hw);
 146 +       kfree(p_names[0]);
 147 +       kfree(init.name);
 148 +
 149 +       return PTR_ERR_OR_ZERO(clk);
 150 +}
 151 +
 152 +static int
 153 +krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset,
 154 +                 bool unique_aux)
 155 +{
 156 +       struct krait_mux_clk *mux;
 157 +       static const char *sec_mux_list[] = {
 158 +               "acpu_aux",
 159 +               "qsb",
 160 +       };
 161 +       struct clk_init_data init = {
 162 +               .parent_names = sec_mux_list,
 163 +               .num_parents = ARRAY_SIZE(sec_mux_list),
 164 +               .ops = &krait_mux_clk_ops,
 165 +               .flags = CLK_SET_RATE_PARENT,
 166 +       };
 167 +       struct clk *clk;
 168 +
 169 +       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 170 +       if (!mux)
 171 +               return -ENOMEM;
 172 +
 173 +       mux->offset = offset;
 174 +       mux->lpl = id >= 0;
 175 +       mux->has_safe_parent = true;
 176 +       mux->safe_sel = 2;
 177 +       mux->mask = 0x3;
 178 +       mux->shift = 2;
 179 +       mux->parent_map = sec_mux_map;
 180 +       mux->hw.init = &init;
 181 +
 182 +       init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
 183 +       if (!init.name)
 184 +               return -ENOMEM;
 185 +
 186 +       if (unique_aux) {
 187 +               sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
 188 +               if (!sec_mux_list[0]) {
 189 +                       clk = ERR_PTR(-ENOMEM);
 190 +                       goto err_aux;
 191 +               }
 192 +       }
 193 +
 194 +       clk = devm_clk_register(dev, &mux->hw);
 195 +
 196 +       if (unique_aux)
 197 +               kfree(sec_mux_list[0]);
 198 +err_aux:
 199 +       kfree(init.name);
 200 +       return PTR_ERR_OR_ZERO(clk);
 201 +}
 202 +
 203 +static struct clk *
 204 +krait_add_pri_mux(struct device *dev, int id, const char *s, unsigned offset)
 205 +{
 206 +       struct krait_mux_clk *mux;
 207 +       const char *p_names[3];
 208 +       struct clk_init_data init = {
 209 +               .parent_names = p_names,
 210 +               .num_parents = ARRAY_SIZE(p_names),
 211 +               .ops = &krait_mux_clk_ops,
 212 +               .flags = CLK_SET_RATE_PARENT,
 213 +       };
 214 +       struct clk *clk;
 215 +
 216 +       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 217 +       if (!mux)
 218 +               return ERR_PTR(-ENOMEM);
 219 +
 220 +       mux->has_safe_parent = true;
 221 +       mux->safe_sel = 0;
 222 +       mux->mask = 0x3;
 223 +       mux->shift = 0;
 224 +       mux->offset = offset;
 225 +       mux->lpl = id >= 0;
 226 +       mux->parent_map = pri_mux_map;
 227 +       mux->hw.init = &init;
 228 +
 229 +       init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
 230 +       if (!init.name)
 231 +               return ERR_PTR(-ENOMEM);
 232 +
 233 +       p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
 234 +       if (!p_names[0]) {
 235 +               clk = ERR_PTR(-ENOMEM);
 236 +               goto err_p0;
 237 +       }
 238 +
 239 +       p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
 240 +       if (!p_names[1]) {
 241 +               clk = ERR_PTR(-ENOMEM);
 242 +               goto err_p1;
 243 +       }
 244 +
 245 +       p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
 246 +       if (!p_names[2]) {
 247 +               clk = ERR_PTR(-ENOMEM);
 248 +               goto err_p2;
 249 +       }
 250 +
 251 +       clk = devm_clk_register(dev, &mux->hw);
 252 +
 253 +       kfree(p_names[2]);
 254 +err_p2:
 255 +       kfree(p_names[1]);
 256 +err_p1:
 257 +       kfree(p_names[0]);
 258 +err_p0:
 259 +       kfree(init.name);
 260 +       return clk;
 261 +}
 262 +
 263 +/* id < 0 for L2, otherwise id == physical CPU number */
 264 +static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
 265 +{
 266 +       int ret;
 267 +       unsigned offset;
 268 +       void *p = NULL;
 269 +       const char *s;
 270 +       struct clk *clk;
 271 +
 272 +       if (id >= 0) {
 273 +               offset = 0x4501 + (0x1000 * id);
 274 +               s = p = kasprintf(GFP_KERNEL, "%d", id);
 275 +               if (!s)
 276 +                       return ERR_PTR(-ENOMEM);
 277 +       } else {
 278 +               offset = 0x500;
 279 +               s = "_l2";
 280 +       }
 281 +
 282 +       ret = krait_add_div(dev, id, s, offset);
 283 +       if (ret) {
 284 +               clk = ERR_PTR(ret);
 285 +               goto err;
 286 +       }
 287 +
 288 +       ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
 289 +       if (ret) {
 290 +               clk = ERR_PTR(ret);
 291 +               goto err;
 292 +       }
 293 +
 294 +       clk = krait_add_pri_mux(dev, id, s, offset);
 295 +err:
 296 +       kfree(p);
 297 +       return clk;
 298 +}
 299 +
 300 +static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
 301 +{
 302 +       unsigned int idx = clkspec->args[0];
 303 +       struct clk **clks = data;
 304 +
 305 +       if (idx >= 5) {
 306 +               pr_err("%s: invalid clock index %d\n", __func__, idx);
 307 +               return ERR_PTR(-EINVAL);
 308 +       }
 309 +
 310 +       return clks[idx] ? : ERR_PTR(-ENODEV);
 311 +}
 312 +
 313 +static const struct of_device_id krait_cc_match_table[] = {
 314 +       { .compatible = "qcom,krait-cc-v1", (void *)1UL },
 315 +       { .compatible = "qcom,krait-cc-v2" },
 316 +       {}
 317 +};
 318 +MODULE_DEVICE_TABLE(of, krait_cc_match_table);
 319 +
 320 +static int krait_cc_probe(struct platform_device *pdev)
 321 +{
 322 +       struct device *dev = &pdev->dev;
 323 +       const struct of_device_id *id;
 324 +       unsigned long cur_rate, aux_rate;
 325 +       int cpu;
 326 +       struct clk *clk;
 327 +       struct clk **clks;
 328 +       struct clk *l2_pri_mux_clk;
 329 +
 330 +       id = of_match_device(krait_cc_match_table, dev);
 331 +       if (!id)
 332 +               return -ENODEV;
 333 +
 334 +       /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
 335 +       clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
 336 +       if (IS_ERR(clk))
 337 +               return PTR_ERR(clk);
 338 +
 339 +       if (!id->data) {
 340 +               clk = clk_register_fixed_factor(dev, "acpu_aux",
 341 +                                               "gpll0_vote", 0, 1, 2);
 342 +               if (IS_ERR(clk))
 343 +                       return PTR_ERR(clk);
 344 +       }
 345 +
 346 +       /* Krait configurations have at most 4 CPUs and one L2 */
 347 +       clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
 348 +       if (!clks)
 349 +               return -ENOMEM;
 350 +
 351 +       for_each_possible_cpu(cpu) {
 352 +               clk = krait_add_clks(dev, cpu, id->data);
 353 +               if (IS_ERR(clk))
 354 +                       return PTR_ERR(clk);
 355 +               clks[cpu] = clk;
 356 +       }
 357 +
 358 +       l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
 359 +       if (IS_ERR(l2_pri_mux_clk))
 360 +               return PTR_ERR(l2_pri_mux_clk);
 361 +       clks[4] = l2_pri_mux_clk;
 362 +
 363 +       /*
 364 +        * We don't want the CPU or L2 clocks to be turned off at late init
 365 +        * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
 366 +        * refcount of these clocks. Any cpufreq/hotplug manager can assume
 367 +        * that the clocks have already been prepared and enabled by the time
 368 +        * they take over.
 369 +        */
 370 +       for_each_online_cpu(cpu) {
 371 +               clk_prepare_enable(l2_pri_mux_clk);
 372 +               WARN(clk_prepare_enable(clks[cpu]),
 373 +                       "Unable to turn on CPU%d clock", cpu);
 374 +       }
 375 +
 376 +       /*
 377 +        * Force reinit of HFPLLs and muxes to overwrite any potential
 378 +        * incorrect configuration of HFPLLs and muxes by the bootloader.
 379 +        * While at it, also make sure the cores are running at known rates
 380 +        * and print the current rate.
 381 +        *
 382 +        * The clocks are set to aux clock rate first to make sure the
 383 +        * secondary mux is not sourcing off of QSB. The rate is then set to
 384 +        * two different rates to force a HFPLL reinit under all
 385 +        * circumstances.
 386 +        */
 387 +       cur_rate = clk_get_rate(l2_pri_mux_clk);
 388 +       aux_rate = 384000000;
 389 +       if (cur_rate == 1) {
 390 +               pr_info("L2 @ QSB rate. Forcing new rate.\n");
 391 +               cur_rate = aux_rate;
 392 +       }
 393 +       clk_set_rate(l2_pri_mux_clk, aux_rate);
 394 +       clk_set_rate(l2_pri_mux_clk, 2);
 395 +       clk_set_rate(l2_pri_mux_clk, cur_rate);
 396 +       pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
 397 +       for_each_possible_cpu(cpu) {
 398 +               clk = clks[cpu];
 399 +               cur_rate = clk_get_rate(clk);
 400 +               if (cur_rate == 1) {
 401 +                       pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
 402 +                       cur_rate = aux_rate;
 403 +               }
 404 +               clk_set_rate(clk, aux_rate);
 405 +               clk_set_rate(clk, 2);
 406 +               clk_set_rate(clk, cur_rate);
 407 +               pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
 408 +       }
 409 +
 410 +       of_clk_add_provider(dev->of_node, krait_of_get, clks);
 411 +
 412 +       return 0;
 413 +}
 414 +
 415 +static struct platform_driver krait_cc_driver = {
 416 +       .probe = krait_cc_probe,
 417 +       .driver = {
 418 +               .name = "krait-cc",
 419 +               .of_match_table = krait_cc_match_table,
 420 +       },
 421 +};
 422 +module_platform_driver(krait_cc_driver);
 423 +
 424 +MODULE_DESCRIPTION("Krait CPU Clock Driver");
 425 +MODULE_LICENSE("GPL v2");
 426 +MODULE_ALIAS("platform:krait-cc");