target/linux/ipq806x/patches-4.9/0045-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch

   1 From patchwork Fri Dec  8 09:42:29 2017
   2 Content-Type: text/plain; charset="utf-8"
   3 MIME-Version: 1.0
   4 Content-Transfer-Encoding: 7bit
   5 Subject: [v4,11/12] cpufreq: Add module to register cpufreq on Krait CPUs
   6 From: Sricharan R <sricharan@codeaurora.org>
   7 X-Patchwork-Id: 10102075
   8 Message-Id: <1512726150-7204-12-git-send-email-sricharan@codeaurora.org>
   9 To: mturquette@baylibre.com, sboyd@codeaurora.org,
  10  devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
  11  linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
  12  viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
  13 Cc: sricharan@codeaurora.org
  14 Date: Fri,  8 Dec 2017 15:12:29 +0530
  15
  16 From: Stephen Boyd <sboyd@codeaurora.org>
  17
  18 Register a cpufreq-generic device whenever we detect that a
  19 "qcom,krait" compatible CPU is present in DT.
  20
  21 Cc: <devicetree@vger.kernel.org>
  22 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  23 ---
  24  .../devicetree/bindings/arm/msm/qcom,pvs.txt       |  38 ++++
  25  drivers/cpufreq/Kconfig.arm                        |   9 +
  26  drivers/cpufreq/Makefile                           |   1 +
  27  drivers/cpufreq/qcom-cpufreq.c                     | 204 +++++++++++++++++++++
  28  4 files changed, 252 insertions(+)
  29  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
  30  create mode 100644 drivers/cpufreq/qcom-cpufreq.c
  31
  32 --- /dev/null
  33 +++ b/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
  34 @@ -0,0 +1,38 @@
  35 +Qualcomm Process Voltage Scaling Tables
  36 +
  37 +The node name is required to be "qcom,pvs". There shall only be one
  38 +such node present in the root of the tree.
  39 +
  40 +PROPERTIES
  41 +
  42 +- qcom,pvs-format-a or qcom,pvs-format-b:
  43 +       Usage: required
  44 +       Value type: <empty>
  45 +       Definition: Indicates the format of qcom,speedX-pvsY-bin-vZ properties.
  46 +                   If qcom,pvs-format-a is used the table is two columns
  47 +                   (frequency and voltage in that order). If qcom,pvs-format-b                     is used the table is three columns (frequency, voltage,
  48 +                   and current in that order).
  49 +
  50 +- qcom,speedX-pvsY-bin-vZ:
  51 +       Usage: required
  52 +       Value type: <prop-encoded-array>
  53 +       Definition: The PVS table corresponding to the speed bin X, pvs bin Y,
  54 +                   and version Z.
  55 +Example:
  56 +
  57 +       qcom,pvs {
  58 +               qcom,pvs-format-a;
  59 +               qcom,speed0-pvs0-bin-v0 =
  60 +                       <  384000000  950000 >,
  61 +                       <  486000000  975000 >,
  62 +                       <  594000000 1000000 >,
  63 +                       <  702000000 1025000 >,
  64 +                       <  810000000 1075000 >,
  65 +                       <  918000000 1100000 >,
  66 +                       < 1026000000 1125000 >,
  67 +                       < 1134000000 1175000 >,
  68 +                       < 1242000000 1200000 >,
  69 +                       < 1350000000 1225000 >,
  70 +                       < 1458000000 1237500 >,
  71 +                       < 1512000000 1250000 >;
  72 +       };
  73 --- a/drivers/cpufreq/Kconfig.arm
  74 +++ b/drivers/cpufreq/Kconfig.arm
  75 @@ -88,6 +88,15 @@ config ARM_OMAP2PLUS_CPUFREQ
  76         depends on ARCH_OMAP2PLUS
  77         default ARCH_OMAP2PLUS
  78
  79 +config ARM_QCOM_CPUFREQ
  80 +       tristate "Qualcomm based"
  81 +       depends on ARCH_QCOM
  82 +       select PM_OPP
  83 +       help
  84 +         This adds the CPUFreq driver for Qualcomm SoC based boards.
  85 +
  86 +         If in doubt, say N.
  87 +
  88  config ARM_S3C_CPUFREQ
  89         bool
  90         help
  91 --- a/drivers/cpufreq/Makefile
  92 +++ b/drivers/cpufreq/Makefile
  93 @@ -62,6 +62,7 @@ obj-$(CONFIG_ARM_MT8173_CPUFREQ)      += mt81
  94  obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)    += omap-cpufreq.o
  95  obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)       += pxa2xx-cpufreq.o
  96  obj-$(CONFIG_PXA3xx)                   += pxa3xx-cpufreq.o
  97 +obj-$(CONFIG_ARM_QCOM_CPUFREQ)         += qcom-cpufreq.o
  98  obj-$(CONFIG_ARM_S3C24XX_CPUFREQ)      += s3c24xx-cpufreq.o
  99  obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o
 100  obj-$(CONFIG_ARM_S3C2410_CPUFREQ)      += s3c2410-cpufreq.o
 101 --- /dev/null
 102 +++ b/drivers/cpufreq/qcom-cpufreq.c
 103 @@ -0,0 +1,204 @@
 104 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 105 + *
 106 + * This program is free software; you can redistribute it and/or modify
 107 + * it under the terms of the GNU General Public License version 2 and
 108 + * only version 2 as published by the Free Software Foundation.
 109 + *
 110 + * This program is distributed in the hope that it will be useful,
 111 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 112 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 113 + * GNU General Public License for more details.
 114 + */
 115 +
 116 +#include <linux/cpu.h>
 117 +#include <linux/err.h>
 118 +#include <linux/init.h>
 119 +#include <linux/io.h>
 120 +#include <linux/kernel.h>
 121 +#include <linux/module.h>
 122 +#include <linux/of.h>
 123 +#include <linux/platform_device.h>
 124 +#include <linux/pm_opp.h>
 125 +#include <linux/slab.h>
 126 +#include "cpufreq-dt.h"
 127 +
 128 +static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
 129 +{
 130 +       void __iomem *base;
 131 +       u32 pte_efuse;
 132 +
 133 +       *speed = *pvs = *pvs_ver = 0;
 134 +
 135 +       base = ioremap(0x007000c0, 4);
 136 +       if (!base) {
 137 +               pr_warn("Unable to read efuse data. Defaulting to 0!\n");
 138 +               return;
 139 +       }
 140 +
 141 +       pte_efuse = readl_relaxed(base);
 142 +       iounmap(base);
 143 +
 144 +       *speed = pte_efuse & 0xf;
 145 +       if (*speed == 0xf)
 146 +               *speed = (pte_efuse >> 4) & 0xf;
 147 +
 148 +       if (*speed == 0xf) {
 149 +               *speed = 0;
 150 +               pr_warn("Speed bin: Defaulting to %d\n", *speed);
 151 +       } else {
 152 +               pr_info("Speed bin: %d\n", *speed);
 153 +       }
 154 +
 155 +       *pvs = (pte_efuse >> 10) & 0x7;
 156 +       if (*pvs == 0x7)
 157 +               *pvs = (pte_efuse >> 13) & 0x7;
 158 +
 159 +       if (*pvs == 0x7) {
 160 +               *pvs = 0;
 161 +               pr_warn("PVS bin: Defaulting to %d\n", *pvs);
 162 +       } else {
 163 +               pr_info("PVS bin: %d\n", *pvs);
 164 +       }
 165 +}
 166 +
 167 +static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver)
 168 +{
 169 +       u32 pte_efuse, redundant_sel;
 170 +       void __iomem *base;
 171 +
 172 +       *speed = 0;
 173 +       *pvs = 0;
 174 +       *pvs_ver = 0;
 175 +
 176 +       base = ioremap(0xfc4b80b0, 8);
 177 +       if (!base) {
 178 +               pr_warn("Unable to read efuse data. Defaulting to 0!\n");
 179 +               return;
 180 +       }
 181 +
 182 +       pte_efuse = readl_relaxed(base);
 183 +       redundant_sel = (pte_efuse >> 24) & 0x7;
 184 +       *speed = pte_efuse & 0x7;
 185 +       /* 4 bits of PVS are in efuse register bits 31, 8-6. */
 186 +       *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 187 +       *pvs_ver = (pte_efuse >> 4) & 0x3;
 188 +
 189 +       switch (redundant_sel) {
 190 +       case 1:
 191 +               *speed = (pte_efuse >> 27) & 0xf;
 192 +               break;
 193 +       case 2:
 194 +               *pvs = (pte_efuse >> 27) & 0xf;
 195 +               break;
 196 +       }
 197 +
 198 +       /* Check SPEED_BIN_BLOW_STATUS */
 199 +       if (pte_efuse & BIT(3)) {
 200 +               pr_info("Speed bin: %d\n", *speed);
 201 +       } else {
 202 +               pr_warn("Speed bin not set. Defaulting to 0!\n");
 203 +               *speed = 0;
 204 +       }
 205 +
 206 +       /* Check PVS_BLOW_STATUS */
 207 +       pte_efuse = readl_relaxed(base + 0x4) & BIT(21);
 208 +       if (pte_efuse) {
 209 +               pr_info("PVS bin: %d\n", *pvs);
 210 +       } else {
 211 +               pr_warn("PVS bin not set. Defaulting to 0!\n");
 212 +               *pvs = 0;
 213 +       }
 214 +
 215 +       pr_info("PVS version: %d\n", *pvs_ver);
 216 +       iounmap(base);
 217 +}
 218 +
 219 +static int __init qcom_cpufreq_populate_opps(void)
 220 +{
 221 +       int len, rows, cols, i, k, speed, pvs, pvs_ver;
 222 +       char table_name[] = "qcom,speedXX-pvsXX-bin-vXX";
 223 +       struct device_node *np;
 224 +       struct device *dev;
 225 +       int cpu = 0;
 226 +
 227 +       np = of_find_node_by_name(NULL, "qcom,pvs");
 228 +       if (!np)
 229 +               return -ENODEV;
 230 +
 231 +       if (of_property_read_bool(np, "qcom,pvs-format-a")) {
 232 +               get_krait_bin_format_a(&speed, &pvs, &pvs_ver);
 233 +               cols = 2;
 234 +       } else if (of_property_read_bool(np, "qcom,pvs-format-b")) {
 235 +               get_krait_bin_format_b(&speed, &pvs, &pvs_ver);
 236 +               cols = 3;
 237 +       } else {
 238 +               return -ENODEV;
 239 +       }
 240 +
 241 +       snprintf(table_name, sizeof(table_name),
 242 +                "qcom,speed%d-pvs%d-bin-v%d", speed, pvs, pvs_ver);
 243 +
 244 +       if (!of_find_property(np, table_name, &len))
 245 +               return -EINVAL;
 246 +
 247 +       len /= sizeof(u32);
 248 +       if (len % cols || len == 0)
 249 +               return -EINVAL;
 250 +
 251 +       rows = len / cols;
 252 +
 253 +       for (i = 0, k = 0; i < rows; i++) {
 254 +               u32 freq, volt;
 255 +
 256 +               of_property_read_u32_index(np, table_name, k++, &freq);
 257 +               of_property_read_u32_index(np, table_name, k++, &volt);
 258 +               while (k % cols)
 259 +                       k++; /* Skip uA entries if present */
 260 +               for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
 261 +                       dev = get_cpu_device(cpu);
 262 +                       if (!dev)
 263 +                               return -ENODEV;
 264 +                       if (dev_pm_opp_add(dev, freq, volt))
 265 +                               pr_warn("failed to add OPP %u\n", freq);
 266 +               }
 267 +       }
 268 +
 269 +       return 0;
 270 +}
 271 +
 272 +static int __init qcom_cpufreq_driver_init(void)
 273 +{
 274 +       struct cpufreq_dt_platform_data pdata = { .independent_clocks = true };
 275 +       struct platform_device_info devinfo = {
 276 +               .name = "cpufreq-dt",
 277 +               .data = &pdata,
 278 +               .size_data = sizeof(pdata),
 279 +       };
 280 +       struct device *cpu_dev;
 281 +       struct device_node *np;
 282 +       int ret;
 283 +
 284 +       cpu_dev = get_cpu_device(0);
 285 +       if (!cpu_dev)
 286 +               return -ENODEV;
 287 +
 288 +       np = of_node_get(cpu_dev->of_node);
 289 +       if (!np)
 290 +               return -ENOENT;
 291 +
 292 +       if (!of_device_is_compatible(np, "qcom,krait")) {
 293 +               of_node_put(np);
 294 +               return -ENODEV;
 295 +       }
 296 +       of_node_put(np);
 297 +
 298 +       ret = qcom_cpufreq_populate_opps();
 299 +       if (ret)
 300 +               return ret;
 301 +
 302 +       return PTR_ERR_OR_ZERO(platform_device_register_full(&devinfo));
 303 +}
 304 +module_init(qcom_cpufreq_driver_init);
 305 +
 306 +MODULE_DESCRIPTION("Qualcomm CPUfreq driver");
 307 +MODULE_LICENSE("GPL v2");